1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/Target/TargetAsmInfo.h"
33 #include "llvm/Target/TargetFrameInfo.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
41 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
42 const TargetInstrInfo &tii)
43 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
45 // Cache some information.
46 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
47 Is64Bit = Subtarget->is64Bit();
48 IsWin64 = Subtarget->isTargetWin64();
49 StackAlign = TM.getFrameInfo()->getStackAlignment();
61 // getDwarfRegNum - This function maps LLVM register identifiers to the
62 // Dwarf specific numbering, used in debug info and exception tables.
64 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
65 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
66 unsigned Flavour = DWARFFlavour::X86_64;
67 if (!Subtarget->is64Bit()) {
68 if (Subtarget->isTargetDarwin()) {
70 Flavour = DWARFFlavour::X86_32_DarwinEH;
72 Flavour = DWARFFlavour::X86_32_Generic;
73 } else if (Subtarget->isTargetCygMing()) {
74 // Unsupported by now, just quick fallback
75 Flavour = DWARFFlavour::X86_32_Generic;
77 Flavour = DWARFFlavour::X86_32_Generic;
81 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
84 // getX86RegNum - This function maps LLVM register identifiers to their X86
85 // specific numbering, which is used in various places encoding instructions.
87 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
89 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
90 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
91 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
92 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
93 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
95 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
97 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
99 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
102 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
104 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
106 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
108 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
110 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
112 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
114 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
116 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
119 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
120 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
121 return RegNo-X86::ST0;
123 case X86::XMM0: case X86::XMM8: case X86::MM0:
125 case X86::XMM1: case X86::XMM9: case X86::MM1:
127 case X86::XMM2: case X86::XMM10: case X86::MM2:
129 case X86::XMM3: case X86::XMM11: case X86::MM3:
131 case X86::XMM4: case X86::XMM12: case X86::MM4:
133 case X86::XMM5: case X86::XMM13: case X86::MM5:
135 case X86::XMM6: case X86::XMM14: case X86::MM6:
137 case X86::XMM7: case X86::XMM15: case X86::MM7:
141 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
142 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
147 const TargetRegisterClass *
148 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
149 if (RC == &X86::CCRRegClass) {
151 return &X86::GR64RegClass;
153 return &X86::GR32RegClass;
159 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
160 static const unsigned CalleeSavedRegs32Bit[] = {
161 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
164 static const unsigned CalleeSavedRegs32EHRet[] = {
165 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
168 static const unsigned CalleeSavedRegs64Bit[] = {
169 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
172 static const unsigned CalleeSavedRegsWin64[] = {
173 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
174 X86::R12, X86::R13, X86::R14, X86::R15, 0
179 return CalleeSavedRegsWin64;
181 return CalleeSavedRegs64Bit;
184 MachineFrameInfo *MFI = MF->getFrameInfo();
185 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
186 if (MMI && MMI->callsEHReturn())
187 return CalleeSavedRegs32EHRet;
189 return CalleeSavedRegs32Bit;
193 const TargetRegisterClass* const*
194 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
195 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
196 &X86::GR32RegClass, &X86::GR32RegClass,
197 &X86::GR32RegClass, &X86::GR32RegClass, 0
199 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
200 &X86::GR32RegClass, &X86::GR32RegClass,
201 &X86::GR32RegClass, &X86::GR32RegClass,
202 &X86::GR32RegClass, &X86::GR32RegClass, 0
204 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
205 &X86::GR64RegClass, &X86::GR64RegClass,
206 &X86::GR64RegClass, &X86::GR64RegClass,
207 &X86::GR64RegClass, &X86::GR64RegClass, 0
209 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
210 &X86::GR64RegClass, &X86::GR64RegClass,
211 &X86::GR64RegClass, &X86::GR64RegClass,
212 &X86::GR64RegClass, &X86::GR64RegClass,
213 &X86::GR64RegClass, &X86::GR64RegClass, 0
218 return CalleeSavedRegClassesWin64;
220 return CalleeSavedRegClasses64Bit;
223 MachineFrameInfo *MFI = MF->getFrameInfo();
224 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
225 if (MMI && MMI->callsEHReturn())
226 return CalleeSavedRegClasses32EHRet;
228 return CalleeSavedRegClasses32Bit;
233 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
234 BitVector Reserved(getNumRegs());
235 Reserved.set(X86::RSP);
236 Reserved.set(X86::ESP);
237 Reserved.set(X86::SP);
238 Reserved.set(X86::SPL);
240 Reserved.set(X86::RBP);
241 Reserved.set(X86::EBP);
242 Reserved.set(X86::BP);
243 Reserved.set(X86::BPL);
248 //===----------------------------------------------------------------------===//
249 // Stack Frame Processing methods
250 //===----------------------------------------------------------------------===//
252 // hasFP - Return true if the specified function should have a dedicated frame
253 // pointer register. This is true if the function has variable sized allocas or
254 // if frame pointer elimination is disabled.
256 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
257 MachineFrameInfo *MFI = MF.getFrameInfo();
258 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
260 return (NoFramePointerElim ||
261 needsStackRealignment(MF) ||
262 MFI->hasVarSizedObjects() ||
263 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
264 (MMI && MMI->callsUnwindInit()));
267 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
268 MachineFrameInfo *MFI = MF.getFrameInfo();;
270 return (MFI->getMaxAlignment() > StackAlign);
273 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
274 return !MF.getFrameInfo()->hasVarSizedObjects();
277 void X86RegisterInfo::
278 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
279 MachineBasicBlock::iterator I) const {
280 if (!hasReservedCallFrame(MF)) {
281 // If the stack pointer can be changed after prologue, turn the
282 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
283 // adjcallstackdown instruction into 'add ESP, <amt>'
284 // TODO: consider using push / pop instead of sub + store / add
285 MachineInstr *Old = I;
286 uint64_t Amount = Old->getOperand(0).getImm();
288 // We need to keep the stack aligned properly. To do this, we round the
289 // amount of space needed for the outgoing arguments up to the next
290 // alignment boundary.
291 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
293 MachineInstr *New = 0;
294 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
295 New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
296 .addReg(StackPtr).addImm(Amount);
298 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
299 // factor out the amount the callee already popped.
300 uint64_t CalleeAmt = Old->getOperand(1).getImm();
303 unsigned Opc = (Amount < 128) ?
304 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
305 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
306 New = BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount);
310 // Replace the pseudo instruction with a new instruction...
311 if (New) MBB.insert(I, New);
313 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
314 // If we are performing frame pointer elimination and if the callee pops
315 // something off the stack pointer, add it back. We do this until we have
316 // more advanced stack pointer tracking ability.
317 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
318 unsigned Opc = (CalleeAmt < 128) ?
319 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
320 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
322 BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
330 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
331 int SPAdj, RegScavenger *RS) const{
332 assert(SPAdj == 0 && "Unexpected");
335 MachineInstr &MI = *II;
336 MachineFunction &MF = *MI.getParent()->getParent();
337 while (!MI.getOperand(i).isFrameIndex()) {
339 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
342 int FrameIndex = MI.getOperand(i).getIndex();
343 // This must be part of a four operand memory reference. Replace the
344 // FrameIndex with base register with EBP. Add an offset to the offset.
345 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false);
347 // Now add the frame object offset to the offset from EBP.
348 int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
349 MI.getOperand(i+3).getImm()+SlotSize;
352 Offset += MF.getFrameInfo()->getStackSize();
354 Offset += SlotSize; // Skip the saved EBP
355 // Skip the RETADDR move area
356 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
357 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
358 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
361 MI.getOperand(i+3).ChangeToImmediate(Offset);
365 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
366 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
367 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
368 if (TailCallReturnAddrDelta < 0) {
369 // create RETURNADDR area
379 CreateFixedObject(-TailCallReturnAddrDelta,
380 (-1*SlotSize)+TailCallReturnAddrDelta);
383 assert((TailCallReturnAddrDelta <= 0) &&
384 "The Delta should always be zero or negative");
385 // Create a frame entry for the EBP register that must be saved.
386 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
388 TailCallReturnAddrDelta);
389 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
390 "Slot for EBP register must be last in order to be found!");
394 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
395 /// stack pointer by a constant value.
397 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
398 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
399 const TargetInstrInfo &TII) {
400 bool isSub = NumBytes < 0;
401 uint64_t Offset = isSub ? -NumBytes : NumBytes;
404 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
405 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
407 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
408 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
409 uint64_t Chunk = (1LL << 31) - 1;
412 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
413 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
418 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
420 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
421 unsigned StackPtr, uint64_t *NumBytes = NULL) {
422 if (MBBI == MBB.begin()) return;
424 MachineBasicBlock::iterator PI = prior(MBBI);
425 unsigned Opc = PI->getOpcode();
426 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
427 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
428 PI->getOperand(0).getReg() == StackPtr) {
430 *NumBytes += PI->getOperand(2).getImm();
432 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
433 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
434 PI->getOperand(0).getReg() == StackPtr) {
436 *NumBytes -= PI->getOperand(2).getImm();
441 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
443 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
444 MachineBasicBlock::iterator &MBBI,
445 unsigned StackPtr, uint64_t *NumBytes = NULL) {
448 if (MBBI == MBB.end()) return;
450 MachineBasicBlock::iterator NI = next(MBBI);
451 if (NI == MBB.end()) return;
453 unsigned Opc = NI->getOpcode();
454 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
455 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
456 NI->getOperand(0).getReg() == StackPtr) {
458 *NumBytes -= NI->getOperand(2).getImm();
461 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
462 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
463 NI->getOperand(0).getReg() == StackPtr) {
465 *NumBytes += NI->getOperand(2).getImm();
471 /// mergeSPUpdates - Checks the instruction before/after the passed
472 /// instruction. If it is an ADD/SUB instruction it is deleted
473 /// argument and the stack adjustment is returned as a positive value for ADD
474 /// and a negative for SUB.
475 static int mergeSPUpdates(MachineBasicBlock &MBB,
476 MachineBasicBlock::iterator &MBBI,
478 bool doMergeWithPrevious) {
480 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
481 (!doMergeWithPrevious && MBBI == MBB.end()))
486 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
487 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
488 unsigned Opc = PI->getOpcode();
489 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
490 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
491 PI->getOperand(0).getReg() == StackPtr){
492 Offset += PI->getOperand(2).getImm();
494 if (!doMergeWithPrevious) MBBI = NI;
495 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
496 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
497 PI->getOperand(0).getReg() == StackPtr) {
498 Offset -= PI->getOperand(2).getImm();
500 if (!doMergeWithPrevious) MBBI = NI;
506 void X86RegisterInfo::emitFrameMoves(MachineFunction &MF,
507 unsigned FrameLabelId,
508 unsigned ReadyLabelId) const {
509 MachineFrameInfo *MFI = MF.getFrameInfo();
510 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
514 uint64_t StackSize = MFI->getStackSize();
515 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
516 const TargetData *TD = MF.getTarget().getTargetData();
518 // Calculate amount of bytes used for return address storing
520 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
521 TargetFrameInfo::StackGrowsUp ?
522 TD->getPointerSize() : -TD->getPointerSize());
525 // Show update of SP.
528 MachineLocation SPDst(MachineLocation::VirtualFP);
529 MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
530 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
532 MachineLocation SPDst(MachineLocation::VirtualFP);
533 MachineLocation SPSrc(MachineLocation::VirtualFP,
534 -StackSize+stackGrowth);
535 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
538 //FIXME: Verify & implement for FP
539 MachineLocation SPDst(StackPtr);
540 MachineLocation SPSrc(StackPtr, stackGrowth);
541 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
544 // Add callee saved registers to move list.
545 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
547 // FIXME: This is dirty hack. The code itself is pretty mess right now.
548 // It should be rewritten from scratch and generalized sometimes.
550 // Determine maximum offset (minumum due to stack growth)
551 int64_t MaxOffset = 0;
552 for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
553 MaxOffset = std::min(MaxOffset,
554 MFI->getObjectOffset(CSI[I].getFrameIdx()));
557 int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
558 for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
559 int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
560 unsigned Reg = CSI[I].getReg();
561 Offset = (MaxOffset-Offset+saveAreaOffset);
562 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
563 MachineLocation CSSrc(Reg);
564 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
569 MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
570 MachineLocation FPSrc(FramePtr);
571 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
574 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
575 MachineLocation FPSrc(MachineLocation::VirtualFP);
576 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
580 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
581 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
582 MachineFrameInfo *MFI = MF.getFrameInfo();
583 const Function* Fn = MF.getFunction();
584 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
585 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
586 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
587 MachineBasicBlock::iterator MBBI = MBB.begin();
588 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
589 !Fn->doesNotThrow() ||
590 UnwindTablesMandatory;
591 // Prepare for frame info.
592 unsigned FrameLabelId = 0;
594 // Get the number of bytes to allocate from the FrameInfo.
595 uint64_t StackSize = MFI->getStackSize();
596 // Add RETADDR move area to callee saved frame size.
597 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
598 if (TailCallReturnAddrDelta < 0)
599 X86FI->setCalleeSavedFrameSize(
600 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
601 uint64_t NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
603 // Insert stack pointer adjustment for later moving of return addr. Only
604 // applies to tail call optimized functions where the callee argument stack
605 // size is bigger than the callers.
606 if (TailCallReturnAddrDelta < 0) {
607 BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
608 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
612 // Get the offset of the stack slot for the EBP register... which is
613 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
614 // Update the frame offset adjustment.
615 MFI->setOffsetAdjustment(SlotSize-NumBytes);
617 // Save EBP into the appropriate stack slot...
618 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
620 NumBytes -= SlotSize;
622 if (needsFrameMoves) {
623 // Mark effective beginning of when frame pointer becomes valid.
624 FrameLabelId = MMI->NextLabelID();
625 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId).addImm(0);
628 // Update EBP with the new base value...
629 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
633 unsigned ReadyLabelId = 0;
634 if (needsFrameMoves) {
635 // Mark effective beginning of when frame pointer is ready.
636 ReadyLabelId = MMI->NextLabelID();
637 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId).addImm(0);
640 // Skip the callee-saved push instructions.
641 while (MBBI != MBB.end() &&
642 (MBBI->getOpcode() == X86::PUSH32r ||
643 MBBI->getOpcode() == X86::PUSH64r))
646 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
647 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
648 // Check, whether EAX is livein for this function
649 bool isEAXAlive = false;
650 for (MachineRegisterInfo::livein_iterator
651 II = MF.getRegInfo().livein_begin(),
652 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
653 unsigned Reg = II->first;
654 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
655 Reg == X86::AH || Reg == X86::AL);
658 // Function prologue calls _alloca to probe the stack when allocating
659 // more than 4k bytes in one go. Touching the stack at 4K increments is
660 // necessary to ensure that the guard pages used by the OS virtual memory
661 // manager are allocated in correct sequence.
663 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
664 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
665 .addExternalSymbol("_alloca");
668 BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX);
669 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
670 // allocated bytes for EAX.
671 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
672 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
673 .addExternalSymbol("_alloca");
675 MachineInstr *MI = addRegOffset(BuildMI(TII.get(X86::MOV32rm),X86::EAX),
676 StackPtr, NumBytes-4);
677 MBB.insert(MBBI, MI);
680 // If there is an SUB32ri of ESP immediately before this instruction,
681 // merge the two. This can be the case when tail call elimination is
682 // enabled and the callee has more arguments then the caller.
683 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
684 // If there is an ADD32ri or SUB32ri of ESP immediately after this
685 // instruction, merge the two instructions.
686 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
689 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
694 emitFrameMoves(MF, FrameLabelId, ReadyLabelId);
696 // If it's main() on Cygwin\Mingw32 we should align stack as well
697 if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
698 Subtarget->isTargetCygMing()) {
699 BuildMI(MBB, MBBI, TII.get(X86::AND32ri), X86::ESP)
700 .addReg(X86::ESP).addImm(-StackAlign);
703 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(StackAlign);
704 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
708 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
709 MachineBasicBlock &MBB) const {
710 const MachineFrameInfo *MFI = MF.getFrameInfo();
711 const Function* Fn = MF.getFunction();
712 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
713 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
714 MachineBasicBlock::iterator MBBI = prior(MBB.end());
715 unsigned RetOpcode = MBBI->getOpcode();
720 case X86::TCRETURNdi:
721 case X86::TCRETURNri:
722 case X86::TCRETURNri64:
723 case X86::TCRETURNdi64:
727 case X86::TAILJMPm: break; // These are ok
729 assert(0 && "Can only insert epilog into returning blocks");
732 // Get the number of bytes to allocate from the FrameInfo
733 uint64_t StackSize = MFI->getStackSize();
734 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
735 uint64_t NumBytes = StackSize - CSSize;
739 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
740 NumBytes -= SlotSize;
743 // Skip the callee-saved pop instructions.
744 while (MBBI != MBB.begin()) {
745 MachineBasicBlock::iterator PI = prior(MBBI);
746 unsigned Opc = PI->getOpcode();
747 if (Opc != X86::POP32r && Opc != X86::POP64r &&
748 !PI->getDesc().isTerminator())
753 // If there is an ADD32ri or SUB32ri of ESP immediately before this
754 // instruction, merge the two instructions.
755 if (NumBytes || MFI->hasVarSizedObjects())
756 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
758 // If dynamic alloca is used, then reset esp to point to the last callee-saved
759 // slot before popping them off! Also, if it's main() on Cygwin/Mingw32 we
760 // aligned stack in the prologue, - revert stack changes back. Note: we're
761 // assuming, that frame pointer was forced for main()
762 if (MFI->hasVarSizedObjects() ||
763 (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
764 Subtarget->isTargetCygMing())) {
765 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
767 MachineInstr *MI = addRegOffset(BuildMI(TII.get(Opc), StackPtr),
769 MBB.insert(MBBI, MI);
771 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
777 // adjust stack pointer back: ESP += numbytes
779 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
781 // We're returning from function via eh_return.
782 if (RetOpcode == X86::EH_RETURN) {
783 MBBI = prior(MBB.end());
784 MachineOperand &DestAddr = MBBI->getOperand(0);
785 assert(DestAddr.isRegister() && "Offset should be in register!");
786 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
787 addReg(DestAddr.getReg());
788 // Tail call return: adjust the stack pointer and jump to callee
789 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
790 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
791 MBBI = prior(MBB.end());
792 MachineOperand &JumpTarget = MBBI->getOperand(0);
793 MachineOperand &StackAdjust = MBBI->getOperand(1);
794 assert( StackAdjust.isImmediate() && "Expecting immediate value.");
796 // Adjust stack pointer.
797 int StackAdj = StackAdjust.getImm();
798 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
800 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
801 // Incoporate the retaddr area.
802 Offset = StackAdj-MaxTCDelta;
803 assert(Offset >= 0 && "Offset should never be negative");
805 // Check for possible merge with preceeding ADD instruction.
806 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
807 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
809 // Jump to label or value in register.
810 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
811 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
812 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
813 else if (RetOpcode== X86::TCRETURNri64) {
814 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
816 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
817 // Delete the pseudo instruction TCRETURN.
819 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
820 (X86FI->getTCReturnAddrDelta() < 0)) {
821 // Add the return addr area delta back since we are not tail calling.
822 int delta = -1*X86FI->getTCReturnAddrDelta();
823 MBBI = prior(MBB.end());
824 // Check for possible merge with preceeding ADD instruction.
825 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
826 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
830 unsigned X86RegisterInfo::getRARegister() const {
832 return X86::RIP; // Should have dwarf #16
834 return X86::EIP; // Should have dwarf #8
837 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
838 return hasFP(MF) ? FramePtr : StackPtr;
842 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
843 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
845 return Offset + MF.getFrameInfo()->getStackSize();
847 Offset += SlotSize; // Skip the saved EBP
848 // Skip the RETADDR move area
849 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
850 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
851 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
855 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
857 // Calculate amount of bytes used for return address storing
858 int stackGrowth = (Is64Bit ? -8 : -4);
860 // Initial state of the frame pointer is esp+4.
861 MachineLocation Dst(MachineLocation::VirtualFP);
862 MachineLocation Src(StackPtr, stackGrowth);
863 Moves.push_back(MachineMove(0, Dst, Src));
865 // Add return address to move list
866 MachineLocation CSDst(StackPtr, stackGrowth);
867 MachineLocation CSSrc(getRARegister());
868 Moves.push_back(MachineMove(0, CSDst, CSSrc));
871 unsigned X86RegisterInfo::getEHExceptionRegister() const {
872 assert(0 && "What is the exception register");
876 unsigned X86RegisterInfo::getEHHandlerRegister() const {
877 assert(0 && "What is the exception handler register");
882 unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
889 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
891 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
893 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
895 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
901 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
903 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
905 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
907 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
909 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
911 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
913 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
915 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
917 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
919 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
921 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
923 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
925 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
927 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
929 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
931 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
938 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
940 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
942 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
944 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
946 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
948 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
950 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
952 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
954 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
956 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
958 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
960 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
962 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
964 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
966 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
968 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
974 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
976 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
978 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
980 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
982 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
984 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
986 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
988 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
990 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
992 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
994 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
996 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
998 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1000 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1002 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1004 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1009 default: return Reg;
1010 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1012 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1014 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1016 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1018 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1020 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1022 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1024 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1026 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1028 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1030 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1032 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1034 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1036 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1038 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1040 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1049 #include "X86GenRegisterInfo.inc"