1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/ErrorHandling.h"
43 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
44 const TargetInstrInfo &tii)
45 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
46 X86::ADJCALLSTACKDOWN64 :
47 X86::ADJCALLSTACKDOWN32,
48 tm.getSubtarget<X86Subtarget>().is64Bit() ?
49 X86::ADJCALLSTACKUP64 :
50 X86::ADJCALLSTACKUP32),
52 // Cache some information.
53 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
54 Is64Bit = Subtarget->is64Bit();
55 IsWin64 = Subtarget->isTargetWin64();
56 StackAlign = TM.getFrameInfo()->getStackAlignment();
69 /// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
70 /// specific numbering, used in debug info and exception tables.
71 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
72 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
73 unsigned Flavour = DWARFFlavour::X86_64;
75 if (!Subtarget->is64Bit()) {
76 if (Subtarget->isTargetDarwin()) {
78 Flavour = DWARFFlavour::X86_32_DarwinEH;
80 Flavour = DWARFFlavour::X86_32_Generic;
81 } else if (Subtarget->isTargetCygMing()) {
82 // Unsupported by now, just quick fallback
83 Flavour = DWARFFlavour::X86_32_Generic;
85 Flavour = DWARFFlavour::X86_32_Generic;
89 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
92 /// getX86RegNum - This function maps LLVM register identifiers to their X86
93 /// specific numbering, which is used in various places encoding instructions.
94 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
96 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
97 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
98 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
99 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
100 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
102 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
104 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
106 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
109 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
111 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
113 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
115 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
117 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
119 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
121 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
123 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
126 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
127 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
128 return RegNo-X86::ST0;
130 case X86::XMM0: case X86::XMM8: case X86::MM0:
132 case X86::XMM1: case X86::XMM9: case X86::MM1:
134 case X86::XMM2: case X86::XMM10: case X86::MM2:
136 case X86::XMM3: case X86::XMM11: case X86::MM3:
138 case X86::XMM4: case X86::XMM12: case X86::MM4:
140 case X86::XMM5: case X86::XMM13: case X86::MM5:
142 case X86::XMM6: case X86::XMM14: case X86::MM6:
144 case X86::XMM7: case X86::XMM15: case X86::MM7:
189 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
190 llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
195 const TargetRegisterClass *
196 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
197 const TargetRegisterClass *B,
198 unsigned SubIdx) const {
202 if (B == &X86::GR8RegClass) {
203 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
205 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
206 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
207 A == &X86::GR64_NOREXRegClass ||
208 A == &X86::GR64_NOSPRegClass ||
209 A == &X86::GR64_NOREX_NOSPRegClass)
210 return &X86::GR64_ABCDRegClass;
211 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
212 A == &X86::GR32_NOREXRegClass ||
213 A == &X86::GR32_NOSPRegClass)
214 return &X86::GR32_ABCDRegClass;
215 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
216 A == &X86::GR16_NOREXRegClass)
217 return &X86::GR16_ABCDRegClass;
218 } else if (B == &X86::GR8_NOREXRegClass) {
219 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
220 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
221 return &X86::GR64_NOREXRegClass;
222 else if (A == &X86::GR64_ABCDRegClass)
223 return &X86::GR64_ABCDRegClass;
224 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
225 A == &X86::GR32_NOSPRegClass)
226 return &X86::GR32_NOREXRegClass;
227 else if (A == &X86::GR32_ABCDRegClass)
228 return &X86::GR32_ABCDRegClass;
229 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
230 return &X86::GR16_NOREXRegClass;
231 else if (A == &X86::GR16_ABCDRegClass)
232 return &X86::GR16_ABCDRegClass;
235 case X86::sub_8bit_hi:
236 if (B == &X86::GR8_ABCD_HRegClass) {
237 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
238 A == &X86::GR64_NOREXRegClass ||
239 A == &X86::GR64_NOSPRegClass ||
240 A == &X86::GR64_NOREX_NOSPRegClass)
241 return &X86::GR64_ABCDRegClass;
242 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
243 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
244 return &X86::GR32_ABCDRegClass;
245 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
246 A == &X86::GR16_NOREXRegClass)
247 return &X86::GR16_ABCDRegClass;
251 if (B == &X86::GR16RegClass) {
252 if (A->getSize() == 4 || A->getSize() == 8)
254 } else if (B == &X86::GR16_ABCDRegClass) {
255 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
256 A == &X86::GR64_NOREXRegClass ||
257 A == &X86::GR64_NOSPRegClass ||
258 A == &X86::GR64_NOREX_NOSPRegClass)
259 return &X86::GR64_ABCDRegClass;
260 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
261 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
262 return &X86::GR32_ABCDRegClass;
263 } else if (B == &X86::GR16_NOREXRegClass) {
264 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
265 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
266 return &X86::GR64_NOREXRegClass;
267 else if (A == &X86::GR64_ABCDRegClass)
268 return &X86::GR64_ABCDRegClass;
269 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
270 A == &X86::GR32_NOSPRegClass)
271 return &X86::GR32_NOREXRegClass;
272 else if (A == &X86::GR32_ABCDRegClass)
273 return &X86::GR64_ABCDRegClass;
277 if (B == &X86::GR32RegClass || B == &X86::GR32_NOSPRegClass) {
278 if (A->getSize() == 8)
280 } else if (B == &X86::GR32_ABCDRegClass) {
281 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
282 A == &X86::GR64_NOREXRegClass ||
283 A == &X86::GR64_NOSPRegClass ||
284 A == &X86::GR64_NOREX_NOSPRegClass)
285 return &X86::GR64_ABCDRegClass;
286 } else if (B == &X86::GR32_NOREXRegClass) {
287 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
288 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
289 return &X86::GR64_NOREXRegClass;
290 else if (A == &X86::GR64_ABCDRegClass)
291 return &X86::GR64_ABCDRegClass;
295 if (B == &X86::FR32RegClass)
299 if (B == &X86::FR64RegClass)
303 if (B == &X86::VR128RegClass)
310 const TargetRegisterClass *
311 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
313 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
314 case 0: // Normal GPRs.
315 if (TM.getSubtarget<X86Subtarget>().is64Bit())
316 return &X86::GR64RegClass;
317 return &X86::GR32RegClass;
318 case 1: // Normal GRPs except the stack pointer (for encoding reasons).
319 if (TM.getSubtarget<X86Subtarget>().is64Bit())
320 return &X86::GR64_NOSPRegClass;
321 return &X86::GR32_NOSPRegClass;
325 const TargetRegisterClass *
326 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
327 if (RC == &X86::CCRRegClass) {
329 return &X86::GR64RegClass;
331 return &X86::GR32RegClass;
337 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
338 bool callsEHReturn = false;
339 bool ghcCall = false;
342 callsEHReturn = MF->getMMI().callsEHReturn();
343 const Function *F = MF->getFunction();
344 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
347 static const unsigned GhcCalleeSavedRegs[] = {
351 static const unsigned CalleeSavedRegs32Bit[] = {
352 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
355 static const unsigned CalleeSavedRegs32EHRet[] = {
356 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
359 static const unsigned CalleeSavedRegs64Bit[] = {
360 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
363 static const unsigned CalleeSavedRegs64EHRet[] = {
364 X86::RAX, X86::RDX, X86::RBX, X86::R12,
365 X86::R13, X86::R14, X86::R15, X86::RBP, 0
368 static const unsigned CalleeSavedRegsWin64[] = {
369 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
370 X86::R12, X86::R13, X86::R14, X86::R15,
371 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
372 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
373 X86::XMM14, X86::XMM15, 0
377 return GhcCalleeSavedRegs;
378 } else if (Is64Bit) {
380 return CalleeSavedRegsWin64;
382 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
384 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
388 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
389 BitVector Reserved(getNumRegs());
390 // Set the stack-pointer register and its aliases as reserved.
391 Reserved.set(X86::RSP);
392 Reserved.set(X86::ESP);
393 Reserved.set(X86::SP);
394 Reserved.set(X86::SPL);
396 // Set the instruction pointer register and its aliases as reserved.
397 Reserved.set(X86::RIP);
398 Reserved.set(X86::EIP);
399 Reserved.set(X86::IP);
401 // Set the frame-pointer register and its aliases as reserved if needed.
403 Reserved.set(X86::RBP);
404 Reserved.set(X86::EBP);
405 Reserved.set(X86::BP);
406 Reserved.set(X86::BPL);
409 // Mark the x87 stack registers as reserved, since they don't behave normally
410 // with respect to liveness. We don't fully model the effects of x87 stack
411 // pushes and pops after stackification.
412 Reserved.set(X86::ST0);
413 Reserved.set(X86::ST1);
414 Reserved.set(X86::ST2);
415 Reserved.set(X86::ST3);
416 Reserved.set(X86::ST4);
417 Reserved.set(X86::ST5);
418 Reserved.set(X86::ST6);
419 Reserved.set(X86::ST7);
423 //===----------------------------------------------------------------------===//
424 // Stack Frame Processing methods
425 //===----------------------------------------------------------------------===//
427 /// hasFP - Return true if the specified function should have a dedicated frame
428 /// pointer register. This is true if the function has variable sized allocas
429 /// or if frame pointer elimination is disabled.
430 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
431 const MachineFrameInfo *MFI = MF.getFrameInfo();
432 const MachineModuleInfo &MMI = MF.getMMI();
434 return (DisableFramePointerElim(MF) ||
435 needsStackRealignment(MF) ||
436 MFI->hasVarSizedObjects() ||
437 MFI->isFrameAddressTaken() ||
438 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
439 MMI.callsUnwindInit());
442 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
443 const MachineFrameInfo *MFI = MF.getFrameInfo();
444 return (RealignStack &&
445 !MFI->hasVarSizedObjects());
448 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
449 const MachineFrameInfo *MFI = MF.getFrameInfo();
450 const Function *F = MF.getFunction();
451 bool requiresRealignment =
452 RealignStack && ((MFI->getMaxAlignment() > StackAlign) ||
453 F->hasFnAttr(Attribute::StackAlignment));
455 // FIXME: Currently we don't support stack realignment for functions with
456 // variable-sized allocas.
457 // FIXME: Temporary disable the error - it seems to be too conservative.
458 if (0 && requiresRealignment && MFI->hasVarSizedObjects())
460 "Stack realignment in presense of dynamic allocas is not supported");
462 return (requiresRealignment && !MFI->hasVarSizedObjects());
465 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
466 return !MF.getFrameInfo()->hasVarSizedObjects();
469 bool X86RegisterInfo::hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
470 int &FrameIdx) const {
471 if (Reg == FramePtr && hasFP(MF)) {
472 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
479 X86RegisterInfo::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
480 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
481 const MachineFrameInfo *MFI = MF.getFrameInfo();
482 int Offset = MFI->getObjectOffset(FI) - TFI.getOffsetOfLocalArea();
483 uint64_t StackSize = MFI->getStackSize();
485 if (needsStackRealignment(MF)) {
487 // Skip the saved EBP.
490 unsigned Align = MFI->getObjectAlignment(FI);
491 assert((-(Offset + StackSize)) % Align == 0);
493 return Offset + StackSize;
495 // FIXME: Support tail calls
498 return Offset + StackSize;
500 // Skip the saved EBP.
503 // Skip the RETADDR move area
504 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
505 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
506 if (TailCallReturnAddrDelta < 0)
507 Offset -= TailCallReturnAddrDelta;
513 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
516 return X86::SUB64ri8;
517 return X86::SUB64ri32;
520 return X86::SUB32ri8;
525 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
528 return X86::ADD64ri8;
529 return X86::ADD64ri32;
532 return X86::ADD32ri8;
537 void X86RegisterInfo::
538 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
539 MachineBasicBlock::iterator I) const {
540 if (!hasReservedCallFrame(MF)) {
541 // If the stack pointer can be changed after prologue, turn the
542 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
543 // adjcallstackdown instruction into 'add ESP, <amt>'
544 // TODO: consider using push / pop instead of sub + store / add
545 MachineInstr *Old = I;
546 uint64_t Amount = Old->getOperand(0).getImm();
548 // We need to keep the stack aligned properly. To do this, we round the
549 // amount of space needed for the outgoing arguments up to the next
550 // alignment boundary.
551 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
553 MachineInstr *New = 0;
554 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
555 New = BuildMI(MF, Old->getDebugLoc(),
556 TII.get(getSUBriOpcode(Is64Bit, Amount)),
561 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
563 // Factor out the amount the callee already popped.
564 uint64_t CalleeAmt = Old->getOperand(1).getImm();
568 unsigned Opc = getADDriOpcode(Is64Bit, Amount);
569 New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
576 // The EFLAGS implicit def is dead.
577 New->getOperand(3).setIsDead();
579 // Replace the pseudo instruction with a new instruction.
583 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
584 // If we are performing frame pointer elimination and if the callee pops
585 // something off the stack pointer, add it back. We do this until we have
586 // more advanced stack pointer tracking ability.
587 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
588 unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
589 MachineInstr *Old = I;
591 BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
596 // The EFLAGS implicit def is dead.
597 New->getOperand(3).setIsDead();
606 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
607 int SPAdj, FrameIndexValue *Value,
608 RegScavenger *RS) const{
609 assert(SPAdj == 0 && "Unexpected");
612 MachineInstr &MI = *II;
613 MachineFunction &MF = *MI.getParent()->getParent();
615 while (!MI.getOperand(i).isFI()) {
617 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
620 int FrameIndex = MI.getOperand(i).getIndex();
623 unsigned Opc = MI.getOpcode();
624 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
625 if (needsStackRealignment(MF))
626 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
630 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
632 // This must be part of a four operand memory reference. Replace the
633 // FrameIndex with base register with EBP. Add an offset to the offset.
634 MI.getOperand(i).ChangeToRegister(BasePtr, false);
636 // Now add the frame object offset to the offset from EBP.
639 // Tail call jmp happens after FP is popped.
640 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
641 const MachineFrameInfo *MFI = MF.getFrameInfo();
642 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI.getOffsetOfLocalArea();
644 FIOffset = getFrameIndexOffset(MF, FrameIndex);
646 if (MI.getOperand(i+3).isImm()) {
647 // Offset is a 32-bit integer.
648 int Offset = FIOffset + (int)(MI.getOperand(i + 3).getImm());
649 MI.getOperand(i + 3).ChangeToImmediate(Offset);
651 // Offset is symbolic. This is extremely rare.
652 uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
653 MI.getOperand(i+3).setOffset(Offset);
659 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
660 RegScavenger *RS) const {
661 MachineFrameInfo *MFI = MF.getFrameInfo();
663 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
664 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
666 if (TailCallReturnAddrDelta < 0) {
667 // create RETURNADDR area
676 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
677 (-1U*SlotSize)+TailCallReturnAddrDelta,
682 assert((TailCallReturnAddrDelta <= 0) &&
683 "The Delta should always be zero or negative");
684 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
686 // Create a frame entry for the EBP register that must be saved.
687 int FrameIdx = MFI->CreateFixedObject(SlotSize,
689 TFI.getOffsetOfLocalArea() +
690 TailCallReturnAddrDelta,
692 assert(FrameIdx == MFI->getObjectIndexBegin() &&
693 "Slot for EBP register must be last in order to be found!");
698 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
699 /// stack pointer by a constant value.
701 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
702 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
703 const TargetInstrInfo &TII) {
704 bool isSub = NumBytes < 0;
705 uint64_t Offset = isSub ? -NumBytes : NumBytes;
706 unsigned Opc = isSub ?
707 getSUBriOpcode(Is64Bit, Offset) :
708 getADDriOpcode(Is64Bit, Offset);
709 uint64_t Chunk = (1LL << 31) - 1;
710 DebugLoc DL = MBB.findDebugLoc(MBBI);
713 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
715 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
718 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
723 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
725 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
726 unsigned StackPtr, uint64_t *NumBytes = NULL) {
727 if (MBBI == MBB.begin()) return;
729 MachineBasicBlock::iterator PI = prior(MBBI);
730 unsigned Opc = PI->getOpcode();
731 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
732 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
733 PI->getOperand(0).getReg() == StackPtr) {
735 *NumBytes += PI->getOperand(2).getImm();
737 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
738 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
739 PI->getOperand(0).getReg() == StackPtr) {
741 *NumBytes -= PI->getOperand(2).getImm();
746 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
748 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
749 MachineBasicBlock::iterator &MBBI,
750 unsigned StackPtr, uint64_t *NumBytes = NULL) {
751 // FIXME: THIS ISN'T RUN!!!
754 if (MBBI == MBB.end()) return;
756 MachineBasicBlock::iterator NI = llvm::next(MBBI);
757 if (NI == MBB.end()) return;
759 unsigned Opc = NI->getOpcode();
760 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
761 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
762 NI->getOperand(0).getReg() == StackPtr) {
764 *NumBytes -= NI->getOperand(2).getImm();
767 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
768 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
769 NI->getOperand(0).getReg() == StackPtr) {
771 *NumBytes += NI->getOperand(2).getImm();
777 /// mergeSPUpdates - Checks the instruction before/after the passed
778 /// instruction. If it is an ADD/SUB instruction it is deleted argument and the
779 /// stack adjustment is returned as a positive value for ADD and a negative for
781 static int mergeSPUpdates(MachineBasicBlock &MBB,
782 MachineBasicBlock::iterator &MBBI,
784 bool doMergeWithPrevious) {
785 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
786 (!doMergeWithPrevious && MBBI == MBB.end()))
789 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
790 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI);
791 unsigned Opc = PI->getOpcode();
794 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
795 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
796 PI->getOperand(0).getReg() == StackPtr){
797 Offset += PI->getOperand(2).getImm();
799 if (!doMergeWithPrevious) MBBI = NI;
800 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
801 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
802 PI->getOperand(0).getReg() == StackPtr) {
803 Offset -= PI->getOperand(2).getImm();
805 if (!doMergeWithPrevious) MBBI = NI;
811 void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
813 unsigned FramePtr) const {
814 MachineFrameInfo *MFI = MF.getFrameInfo();
815 MachineModuleInfo &MMI = MF.getMMI();
817 // Add callee saved registers to move list.
818 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
819 if (CSI.empty()) return;
821 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
822 const TargetData *TD = MF.getTarget().getTargetData();
823 bool HasFP = hasFP(MF);
825 // Calculate amount of bytes used for return address storing.
827 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
828 TargetFrameInfo::StackGrowsUp ?
829 TD->getPointerSize() : -TD->getPointerSize());
831 // FIXME: This is dirty hack. The code itself is pretty mess right now.
832 // It should be rewritten from scratch and generalized sometimes.
834 // Determine maximum offset (minumum due to stack growth).
835 int64_t MaxOffset = 0;
836 for (std::vector<CalleeSavedInfo>::const_iterator
837 I = CSI.begin(), E = CSI.end(); I != E; ++I)
838 MaxOffset = std::min(MaxOffset,
839 MFI->getObjectOffset(I->getFrameIdx()));
841 // Calculate offsets.
842 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
843 for (std::vector<CalleeSavedInfo>::const_iterator
844 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
845 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
846 unsigned Reg = I->getReg();
847 Offset = MaxOffset - Offset + saveAreaOffset;
849 // Don't output a new machine move if we're re-saving the frame
850 // pointer. This happens when the PrologEpilogInserter has inserted an extra
851 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
852 // generates one when frame pointers are used. If we generate a "machine
853 // move" for this extra "PUSH", the linker will lose track of the fact that
854 // the frame pointer should have the value of the first "PUSH" when it's
857 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
858 // another bug. I.e., one where we generate a prolog like this:
866 // The immediate re-push of EBP is unnecessary. At the least, it's an
867 // optimization bug. EBP can be used as a scratch register in certain
868 // cases, but probably not when we have a frame pointer.
869 if (HasFP && FramePtr == Reg)
872 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
873 MachineLocation CSSrc(Reg);
874 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
878 /// emitPrologue - Push callee-saved registers onto the stack, which
879 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
880 /// space for local variables. Also emit labels used by the exception handler to
881 /// generate the exception handling frames.
882 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
883 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
884 MachineBasicBlock::iterator MBBI = MBB.begin();
885 MachineFrameInfo *MFI = MF.getFrameInfo();
886 const Function *Fn = MF.getFunction();
887 const X86Subtarget *Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
888 MachineModuleInfo &MMI = MF.getMMI();
889 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
890 bool needsFrameMoves = MMI.hasDebugInfo() ||
891 !Fn->doesNotThrow() || UnwindTablesMandatory;
892 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
893 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
894 bool HasFP = hasFP(MF);
897 // Add RETADDR move area to callee saved frame size.
898 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
899 if (TailCallReturnAddrDelta < 0)
900 X86FI->setCalleeSavedFrameSize(
901 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
903 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
904 // function, and use up to 128 bytes of stack space, don't have a frame
905 // pointer, calls, or dynamic alloca then we do not need to adjust the
906 // stack pointer (we fit in the Red Zone).
907 if (Is64Bit && !Fn->hasFnAttr(Attribute::NoRedZone) &&
908 !needsStackRealignment(MF) &&
909 !MFI->hasVarSizedObjects() && // No dynamic alloca.
910 !MFI->adjustsStack() && // No calls.
911 !Subtarget->isTargetWin64()) { // Win64 has no Red Zone
912 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
913 if (HasFP) MinSize += SlotSize;
914 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
915 MFI->setStackSize(StackSize);
916 } else if (Subtarget->isTargetWin64()) {
917 // We need to always allocate 32 bytes as register spill area.
918 // FIXME: We might reuse these 32 bytes for leaf functions.
920 MFI->setStackSize(StackSize);
923 // Insert stack pointer adjustment for later moving of return addr. Only
924 // applies to tail call optimized functions where the callee argument stack
925 // size is bigger than the callers.
926 if (TailCallReturnAddrDelta < 0) {
928 BuildMI(MBB, MBBI, DL,
929 TII.get(getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta)),
932 .addImm(-TailCallReturnAddrDelta);
933 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
936 // Mapping for machine moves:
938 // DST: VirtualFP AND
939 // SRC: VirtualFP => DW_CFA_def_cfa_offset
940 // ELSE => DW_CFA_def_cfa
942 // SRC: VirtualFP AND
943 // DST: Register => DW_CFA_def_cfa_register
946 // OFFSET < 0 => DW_CFA_offset_extended_sf
947 // REG < 64 => DW_CFA_offset + Reg
948 // ELSE => DW_CFA_offset_extended
950 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
951 const TargetData *TD = MF.getTarget().getTargetData();
952 uint64_t NumBytes = 0;
953 int stackGrowth = -TD->getPointerSize();
956 // Calculate required stack adjustment.
957 uint64_t FrameSize = StackSize - SlotSize;
958 if (needsStackRealignment(MF))
959 FrameSize = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
961 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
963 // Get the offset of the stack slot for the EBP register, which is
964 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
965 // Update the frame offset adjustment.
966 MFI->setOffsetAdjustment(-NumBytes);
968 // Save EBP/RBP into the appropriate stack slot.
969 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
970 .addReg(FramePtr, RegState::Kill);
972 if (needsFrameMoves) {
973 // Mark the place where EBP/RBP was saved.
974 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
975 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(FrameLabel);
977 // Define the current CFA rule to use the provided offset.
979 MachineLocation SPDst(MachineLocation::VirtualFP);
980 MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
981 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
983 // FIXME: Verify & implement for FP
984 MachineLocation SPDst(StackPtr);
985 MachineLocation SPSrc(StackPtr, stackGrowth);
986 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
989 // Change the rule for the FramePtr to be an "offset" rule.
990 MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth);
991 MachineLocation FPSrc(FramePtr);
992 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
995 // Update EBP with the new base value...
996 BuildMI(MBB, MBBI, DL,
997 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
1000 if (needsFrameMoves) {
1001 // Mark effective beginning of when frame pointer becomes valid.
1002 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
1003 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(FrameLabel);
1005 // Define the current CFA to use the EBP/RBP register.
1006 MachineLocation FPDst(FramePtr);
1007 MachineLocation FPSrc(MachineLocation::VirtualFP);
1008 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
1011 // Mark the FramePtr as live-in in every block except the entry.
1012 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
1014 I->addLiveIn(FramePtr);
1017 if (needsStackRealignment(MF)) {
1019 BuildMI(MBB, MBBI, DL,
1020 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
1021 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
1023 // The EFLAGS implicit def is dead.
1024 MI->getOperand(3).setIsDead();
1027 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1030 // Skip the callee-saved push instructions.
1031 bool PushedRegs = false;
1032 int StackOffset = 2 * stackGrowth;
1034 while (MBBI != MBB.end() &&
1035 (MBBI->getOpcode() == X86::PUSH32r ||
1036 MBBI->getOpcode() == X86::PUSH64r)) {
1040 if (!HasFP && needsFrameMoves) {
1041 // Mark callee-saved push instruction.
1042 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
1043 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(Label);
1045 // Define the current CFA rule to use the provided offset.
1046 unsigned Ptr = StackSize ?
1047 MachineLocation::VirtualFP : StackPtr;
1048 MachineLocation SPDst(Ptr);
1049 MachineLocation SPSrc(Ptr, StackOffset);
1050 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
1051 StackOffset += stackGrowth;
1055 DL = MBB.findDebugLoc(MBBI);
1057 // Adjust stack pointer: ESP -= numbytes.
1058 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1059 // Check, whether EAX is livein for this function.
1060 bool isEAXAlive = false;
1061 for (MachineRegisterInfo::livein_iterator
1062 II = MF.getRegInfo().livein_begin(),
1063 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
1064 unsigned Reg = II->first;
1065 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
1066 Reg == X86::AH || Reg == X86::AL);
1069 // Function prologue calls _alloca to probe the stack when allocating more
1070 // than 4k bytes in one go. Touching the stack at 4K increments is necessary
1071 // to ensure that the guard pages used by the OS virtual memory manager are
1072 // allocated in correct sequence.
1074 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1076 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1077 .addExternalSymbol("_alloca")
1078 .addReg(StackPtr, RegState::Define | RegState::Implicit);
1081 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1082 .addReg(X86::EAX, RegState::Kill);
1084 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
1085 // allocated bytes for EAX.
1086 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1087 .addImm(NumBytes - 4);
1088 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1089 .addExternalSymbol("_alloca")
1090 .addReg(StackPtr, RegState::Define | RegState::Implicit);
1093 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
1095 StackPtr, false, NumBytes - 4);
1096 MBB.insert(MBBI, MI);
1098 } else if (NumBytes) {
1099 // If there is an SUB32ri of ESP immediately before this instruction, merge
1100 // the two. This can be the case when tail call elimination is enabled and
1101 // the callee has more arguments then the caller.
1102 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
1104 // If there is an ADD32ri or SUB32ri of ESP immediately after this
1105 // instruction, merge the two instructions.
1106 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
1109 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1112 if ((NumBytes || PushedRegs) && needsFrameMoves) {
1113 // Mark end of stack pointer adjustment.
1114 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
1115 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(Label);
1117 if (!HasFP && NumBytes) {
1118 // Define the current CFA rule to use the provided offset.
1120 MachineLocation SPDst(MachineLocation::VirtualFP);
1121 MachineLocation SPSrc(MachineLocation::VirtualFP,
1122 -StackSize + stackGrowth);
1123 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
1125 // FIXME: Verify & implement for FP
1126 MachineLocation SPDst(StackPtr);
1127 MachineLocation SPSrc(StackPtr, stackGrowth);
1128 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
1132 // Emit DWARF info specifying the offsets of the callee-saved registers.
1134 emitCalleeSavedFrameMoves(MF, Label, HasFP ? FramePtr : StackPtr);
1138 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1139 MachineBasicBlock &MBB) const {
1140 const MachineFrameInfo *MFI = MF.getFrameInfo();
1141 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1142 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1143 unsigned RetOpcode = MBBI->getOpcode();
1144 DebugLoc DL = MBBI->getDebugLoc();
1146 switch (RetOpcode) {
1148 llvm_unreachable("Can only insert epilog into returning blocks");
1151 case X86::TCRETURNdi:
1152 case X86::TCRETURNri:
1153 case X86::TCRETURNmi:
1154 case X86::TCRETURNdi64:
1155 case X86::TCRETURNri64:
1156 case X86::TCRETURNmi64:
1157 case X86::EH_RETURN:
1158 case X86::EH_RETURN64:
1159 break; // These are ok
1162 // Get the number of bytes to allocate from the FrameInfo.
1163 uint64_t StackSize = MFI->getStackSize();
1164 uint64_t MaxAlign = MFI->getMaxAlignment();
1165 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1166 uint64_t NumBytes = 0;
1169 // Calculate required stack adjustment.
1170 uint64_t FrameSize = StackSize - SlotSize;
1171 if (needsStackRealignment(MF))
1172 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
1174 NumBytes = FrameSize - CSSize;
1177 BuildMI(MBB, MBBI, DL,
1178 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1180 NumBytes = StackSize - CSSize;
1183 // Skip the callee-saved pop instructions.
1184 MachineBasicBlock::iterator LastCSPop = MBBI;
1185 while (MBBI != MBB.begin()) {
1186 MachineBasicBlock::iterator PI = prior(MBBI);
1187 unsigned Opc = PI->getOpcode();
1189 if (Opc != X86::POP32r && Opc != X86::POP64r &&
1190 !PI->getDesc().isTerminator())
1196 DL = MBBI->getDebugLoc();
1198 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1199 // instruction, merge the two instructions.
1200 if (NumBytes || MFI->hasVarSizedObjects())
1201 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1203 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1204 // slot before popping them off! Same applies for the case, when stack was
1206 if (needsStackRealignment(MF)) {
1207 // We cannot use LEA here, because stack pointer was realigned. We need to
1208 // deallocate local frame back.
1210 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1211 MBBI = prior(LastCSPop);
1214 BuildMI(MBB, MBBI, DL,
1215 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1216 StackPtr).addReg(FramePtr);
1217 } else if (MFI->hasVarSizedObjects()) {
1219 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1221 addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1222 FramePtr, false, -CSSize);
1223 MBB.insert(MBBI, MI);
1225 BuildMI(MBB, MBBI, DL,
1226 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr)
1229 } else if (NumBytes) {
1230 // Adjust stack pointer back: ESP += numbytes.
1231 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1234 // We're returning from function via eh_return.
1235 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1236 MBBI = prior(MBB.end());
1237 MachineOperand &DestAddr = MBBI->getOperand(0);
1238 assert(DestAddr.isReg() && "Offset should be in register!");
1239 BuildMI(MBB, MBBI, DL,
1240 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1241 StackPtr).addReg(DestAddr.getReg());
1242 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1243 RetOpcode == X86::TCRETURNmi ||
1244 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
1245 RetOpcode == X86::TCRETURNmi64) {
1246 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
1247 // Tail call return: adjust the stack pointer and jump to callee.
1248 MBBI = prior(MBB.end());
1249 MachineOperand &JumpTarget = MBBI->getOperand(0);
1250 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
1251 assert(StackAdjust.isImm() && "Expecting immediate value.");
1253 // Adjust stack pointer.
1254 int StackAdj = StackAdjust.getImm();
1255 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1257 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1259 // Incoporate the retaddr area.
1260 Offset = StackAdj-MaxTCDelta;
1261 assert(Offset >= 0 && "Offset should never be negative");
1264 // Check for possible merge with preceeding ADD instruction.
1265 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1266 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1269 // Jump to label or value in register.
1270 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1271 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
1272 ? X86::TAILJMPd : X86::TAILJMPd64)).
1273 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1274 JumpTarget.getTargetFlags());
1275 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1276 MachineInstrBuilder MIB =
1277 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
1278 ? X86::TAILJMPm : X86::TAILJMPm64));
1279 for (unsigned i = 0; i != 5; ++i)
1280 MIB.addOperand(MBBI->getOperand(i));
1281 } else if (RetOpcode == X86::TCRETURNri64) {
1282 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)).
1283 addReg(JumpTarget.getReg(), RegState::Kill);
1285 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
1286 addReg(JumpTarget.getReg(), RegState::Kill);
1289 MachineInstr *NewMI = prior(MBBI);
1290 for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i)
1291 NewMI->addOperand(MBBI->getOperand(i));
1293 // Delete the pseudo instruction TCRETURN.
1295 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1296 (X86FI->getTCReturnAddrDelta() < 0)) {
1297 // Add the return addr area delta back since we are not tail calling.
1298 int delta = -1*X86FI->getTCReturnAddrDelta();
1299 MBBI = prior(MBB.end());
1301 // Check for possible merge with preceeding ADD instruction.
1302 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1303 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1307 unsigned X86RegisterInfo::getRARegister() const {
1308 return Is64Bit ? X86::RIP // Should have dwarf #16.
1309 : X86::EIP; // Should have dwarf #8.
1312 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1313 return hasFP(MF) ? FramePtr : StackPtr;
1317 X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
1318 // Calculate amount of bytes used for return address storing
1319 int stackGrowth = (Is64Bit ? -8 : -4);
1321 // Initial state of the frame pointer is esp+stackGrowth.
1322 MachineLocation Dst(MachineLocation::VirtualFP);
1323 MachineLocation Src(StackPtr, stackGrowth);
1324 Moves.push_back(MachineMove(0, Dst, Src));
1326 // Add return address to move list
1327 MachineLocation CSDst(StackPtr, stackGrowth);
1328 MachineLocation CSSrc(getRARegister());
1329 Moves.push_back(MachineMove(0, CSDst, CSSrc));
1332 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1333 llvm_unreachable("What is the exception register");
1337 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1338 llvm_unreachable("What is the exception handler register");
1343 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
1344 switch (VT.getSimpleVT().SimpleTy) {
1345 default: return Reg;
1350 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1352 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1354 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1356 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1362 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1364 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1366 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1368 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1370 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1372 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1374 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1376 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1378 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1380 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1382 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1384 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1386 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1388 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1390 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1392 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1398 default: return Reg;
1399 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1401 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1403 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1405 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1407 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1409 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1411 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1413 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1415 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1417 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1419 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1421 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1423 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1425 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1427 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1429 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1434 default: return Reg;
1435 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1437 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1439 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1441 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1443 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1445 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1447 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1449 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1451 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1453 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1455 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1457 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1459 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1461 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1463 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1465 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1470 default: return Reg;
1471 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1473 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1475 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1477 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1479 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1481 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1483 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1485 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1487 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1489 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1491 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1493 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1495 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1497 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1499 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1501 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1510 #include "X86GenRegisterInfo.inc"
1513 struct MSAH : public MachineFunctionPass {
1515 MSAH() : MachineFunctionPass(&ID) {}
1517 virtual bool runOnMachineFunction(MachineFunction &MF) {
1518 const X86TargetMachine *TM =
1519 static_cast<const X86TargetMachine *>(&MF.getTarget());
1520 const X86RegisterInfo *X86RI = TM->getRegisterInfo();
1521 MachineRegisterInfo &RI = MF.getRegInfo();
1522 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1523 unsigned StackAlignment = X86RI->getStackAlignment();
1525 // Be over-conservative: scan over all vreg defs and find whether vector
1526 // registers are used. If yes, there is a possibility that vector register
1527 // will be spilled and thus require dynamic stack realignment.
1528 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1529 RegNum < RI.getLastVirtReg(); ++RegNum)
1530 if (RI.getRegClass(RegNum)->getAlignment() > StackAlignment) {
1531 FuncInfo->setReserveFP(true);
1539 virtual const char *getPassName() const {
1540 return "X86 Maximal Stack Alignment Check";
1543 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
1544 AU.setPreservesCFG();
1545 MachineFunctionPass::getAnalysisUsage(AU);
1553 llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }