1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86FrameLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/MachineValueType.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/Type.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Target/TargetFrameLowering.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Target/TargetOptions.h"
44 #define GET_REGINFO_TARGET_DESC
45 #include "X86GenRegisterInfo.inc"
48 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
49 cl::desc("Enable use of a base pointer for complex stack frames"));
51 X86RegisterInfo::X86RegisterInfo(const Triple &TT)
52 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
53 X86_MC::getDwarfRegFlavour(TT, false),
54 X86_MC::getDwarfRegFlavour(TT, true),
55 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
56 X86_MC::InitLLVM2SEHRegisterMapping(this);
58 // Cache some information.
59 Is64Bit = TT.isArch64Bit();
60 IsWin64 = Is64Bit && TT.isOSWindows();
62 // Use a callee-saved register as the base pointer. These registers must
63 // not conflict with any ABI requirements. For example, in 32-bit mode PIC
64 // requires GOT in the EBX register before function calls via PLT GOT pointer.
67 // This matches the simplified 32-bit pointer code in the data layout
69 // FIXME: Should use the data layout?
70 bool Use64BitReg = TT.getEnvironment() != Triple::GNUX32;
71 StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
72 FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
73 BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
83 X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
84 // ExeDepsFixer and PostRAScheduler require liveness.
89 X86RegisterInfo::getSEHRegNum(unsigned i) const {
90 return getEncodingValue(i);
93 const TargetRegisterClass *
94 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
96 // The sub_8bit sub-register index is more constrained in 32-bit mode.
97 // It behaves just like the sub_8bit_hi index.
98 if (!Is64Bit && Idx == X86::sub_8bit)
99 Idx = X86::sub_8bit_hi;
101 // Forward to TableGen's default version.
102 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
105 const TargetRegisterClass *
106 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
107 const TargetRegisterClass *B,
108 unsigned SubIdx) const {
109 // The sub_8bit sub-register index is more constrained in 32-bit mode.
110 if (!Is64Bit && SubIdx == X86::sub_8bit) {
111 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
115 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
118 const TargetRegisterClass *
119 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
120 const MachineFunction &MF) const {
121 // Don't allow super-classes of GR8_NOREX. This class is only used after
122 // extracting sub_8bit_hi sub-registers. The H sub-registers cannot be copied
123 // to the full GR8 register class in 64-bit mode, so we cannot allow the
124 // reigster class inflation.
126 // The GR8_NOREX class is always used in a way that won't be constrained to a
127 // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
129 if (RC == &X86::GR8_NOREXRegClass)
132 const TargetRegisterClass *Super = RC;
133 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
135 switch (Super->getID()) {
136 case X86::GR8RegClassID:
137 case X86::GR16RegClassID:
138 case X86::GR32RegClassID:
139 case X86::GR64RegClassID:
140 case X86::FR32RegClassID:
141 case X86::FR64RegClassID:
142 case X86::RFP32RegClassID:
143 case X86::RFP64RegClassID:
144 case X86::RFP80RegClassID:
145 case X86::VR128RegClassID:
146 case X86::VR256RegClassID:
147 // Don't return a super-class that would shrink the spill size.
148 // That can happen with the vector and float classes.
149 if (Super->getSize() == RC->getSize())
157 const TargetRegisterClass *
158 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
159 unsigned Kind) const {
160 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
162 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
163 case 0: // Normal GPRs.
164 if (Subtarget.isTarget64BitLP64())
165 return &X86::GR64RegClass;
166 return &X86::GR32RegClass;
167 case 1: // Normal GPRs except the stack pointer (for encoding reasons).
168 if (Subtarget.isTarget64BitLP64())
169 return &X86::GR64_NOSPRegClass;
170 return &X86::GR32_NOSPRegClass;
171 case 2: // NOREX GPRs.
172 if (Subtarget.isTarget64BitLP64())
173 return &X86::GR64_NOREXRegClass;
174 return &X86::GR32_NOREXRegClass;
175 case 3: // NOREX GPRs except the stack pointer (for encoding reasons).
176 if (Subtarget.isTarget64BitLP64())
177 return &X86::GR64_NOREX_NOSPRegClass;
178 return &X86::GR32_NOREX_NOSPRegClass;
179 case 4: // Available for tailcall (not callee-saved GPRs).
180 return getGPRsForTailCall(MF);
184 const TargetRegisterClass *
185 X86RegisterInfo::getGPRsForTailCall(const MachineFunction &MF) const {
186 const Function *F = MF.getFunction();
187 if (IsWin64 || (F && F->getCallingConv() == CallingConv::X86_64_Win64))
188 return &X86::GR64_TCW64RegClass;
190 return &X86::GR64_TCRegClass;
192 bool hasHipeCC = (F ? F->getCallingConv() == CallingConv::HiPE : false);
194 return &X86::GR32RegClass;
195 return &X86::GR32_TCRegClass;
198 const TargetRegisterClass *
199 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
200 if (RC == &X86::CCRRegClass) {
202 return &X86::GR64RegClass;
204 return &X86::GR32RegClass;
210 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
211 MachineFunction &MF) const {
212 const X86FrameLowering *TFI = getFrameLowering(MF);
214 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
215 switch (RC->getID()) {
218 case X86::GR32RegClassID:
220 case X86::GR64RegClassID:
222 case X86::VR128RegClassID:
223 return Is64Bit ? 10 : 4;
224 case X86::VR64RegClassID:
230 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
231 const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();
232 bool HasSSE = Subtarget.hasSSE1();
233 bool HasAVX = Subtarget.hasAVX();
234 bool HasAVX512 = Subtarget.hasAVX512();
235 bool CallsEHReturn = MF->getMMI().callsEHReturn();
237 assert(MF && "MachineFunction required");
238 switch (MF->getFunction()->getCallingConv()) {
239 case CallingConv::GHC:
240 case CallingConv::HiPE:
241 return CSR_NoRegs_SaveList;
242 case CallingConv::AnyReg:
244 return CSR_64_AllRegs_AVX_SaveList;
245 return CSR_64_AllRegs_SaveList;
246 case CallingConv::PreserveMost:
247 return CSR_64_RT_MostRegs_SaveList;
248 case CallingConv::PreserveAll:
250 return CSR_64_RT_AllRegs_AVX_SaveList;
251 return CSR_64_RT_AllRegs_SaveList;
252 case CallingConv::CXX_FAST_TLS:
254 return CSR_64_TLS_Darwin_SaveList;
256 case CallingConv::Intel_OCL_BI: {
257 if (HasAVX512 && IsWin64)
258 return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
259 if (HasAVX512 && Is64Bit)
260 return CSR_64_Intel_OCL_BI_AVX512_SaveList;
261 if (HasAVX && IsWin64)
262 return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
263 if (HasAVX && Is64Bit)
264 return CSR_64_Intel_OCL_BI_AVX_SaveList;
265 if (!HasAVX && !IsWin64 && Is64Bit)
266 return CSR_64_Intel_OCL_BI_SaveList;
269 case CallingConv::HHVM:
270 return CSR_64_HHVM_SaveList;
271 case CallingConv::Cold:
273 return CSR_64_MostRegs_SaveList;
275 case CallingConv::X86_64_Win64:
276 return CSR_Win64_SaveList;
277 case CallingConv::X86_64_SysV:
279 return CSR_64EHRet_SaveList;
280 return CSR_64_SaveList;
281 case CallingConv::X86_INTR:
284 return CSR_64_AllRegs_AVX_SaveList;
286 return CSR_64_AllRegs_SaveList;
289 return CSR_32_AllRegs_SSE_SaveList;
291 return CSR_32_AllRegs_SaveList;
299 return CSR_Win64_SaveList;
301 return CSR_64EHRet_SaveList;
302 return CSR_64_SaveList;
305 return CSR_32EHRet_SaveList;
306 return CSR_32_SaveList;
310 X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
311 CallingConv::ID CC) const {
312 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
313 bool HasSSE = Subtarget.hasSSE1();
314 bool HasAVX = Subtarget.hasAVX();
315 bool HasAVX512 = Subtarget.hasAVX512();
318 case CallingConv::GHC:
319 case CallingConv::HiPE:
320 return CSR_NoRegs_RegMask;
321 case CallingConv::AnyReg:
323 return CSR_64_AllRegs_AVX_RegMask;
324 return CSR_64_AllRegs_RegMask;
325 case CallingConv::PreserveMost:
326 return CSR_64_RT_MostRegs_RegMask;
327 case CallingConv::PreserveAll:
329 return CSR_64_RT_AllRegs_AVX_RegMask;
330 return CSR_64_RT_AllRegs_RegMask;
331 case CallingConv::CXX_FAST_TLS:
333 return CSR_64_TLS_Darwin_RegMask;
335 case CallingConv::Intel_OCL_BI: {
336 if (HasAVX512 && IsWin64)
337 return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
338 if (HasAVX512 && Is64Bit)
339 return CSR_64_Intel_OCL_BI_AVX512_RegMask;
340 if (HasAVX && IsWin64)
341 return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
342 if (HasAVX && Is64Bit)
343 return CSR_64_Intel_OCL_BI_AVX_RegMask;
344 if (!HasAVX && !IsWin64 && Is64Bit)
345 return CSR_64_Intel_OCL_BI_RegMask;
348 case CallingConv::HHVM:
349 return CSR_64_HHVM_RegMask;
350 case CallingConv::Cold:
352 return CSR_64_MostRegs_RegMask;
354 case CallingConv::X86_64_Win64:
355 return CSR_Win64_RegMask;
356 case CallingConv::X86_64_SysV:
357 return CSR_64_RegMask;
358 case CallingConv::X86_INTR:
361 return CSR_64_AllRegs_AVX_RegMask;
363 return CSR_64_AllRegs_RegMask;
366 return CSR_32_AllRegs_SSE_RegMask;
368 return CSR_32_AllRegs_RegMask;
374 // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
378 return CSR_Win64_RegMask;
379 return CSR_64_RegMask;
381 return CSR_32_RegMask;
385 X86RegisterInfo::getNoPreservedMask() const {
386 return CSR_NoRegs_RegMask;
389 const uint32_t *X86RegisterInfo::getDarwinTLSCallPreservedMask() const {
390 return CSR_64_TLS_Darwin_RegMask;
393 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
394 BitVector Reserved(getNumRegs());
395 const X86FrameLowering *TFI = getFrameLowering(MF);
397 // Set the stack-pointer register and its aliases as reserved.
398 for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
402 // Set the instruction pointer register and its aliases as reserved.
403 for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
407 // Set the frame-pointer register and its aliases as reserved if needed.
408 if (TFI->hasFP(MF)) {
409 for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
414 // Set the base-pointer register and its aliases as reserved if needed.
415 if (hasBasePointer(MF)) {
416 CallingConv::ID CC = MF.getFunction()->getCallingConv();
417 const uint32_t *RegMask = getCallPreservedMask(MF, CC);
418 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
420 "Stack realignment in presence of dynamic allocas is not supported with"
421 "this calling convention.");
423 unsigned BasePtr = getX86SubSuperRegister(getBaseRegister(), MVT::i64);
424 for (MCSubRegIterator I(BasePtr, this, /*IncludeSelf=*/true);
429 // Mark the segment registers as reserved.
430 Reserved.set(X86::CS);
431 Reserved.set(X86::SS);
432 Reserved.set(X86::DS);
433 Reserved.set(X86::ES);
434 Reserved.set(X86::FS);
435 Reserved.set(X86::GS);
437 // Mark the floating point stack registers as reserved.
438 for (unsigned n = 0; n != 8; ++n)
439 Reserved.set(X86::ST0 + n);
441 // Reserve the registers that only exist in 64-bit mode.
443 // These 8-bit registers are part of the x86-64 extension even though their
444 // super-registers are old 32-bits.
445 Reserved.set(X86::SIL);
446 Reserved.set(X86::DIL);
447 Reserved.set(X86::BPL);
448 Reserved.set(X86::SPL);
450 for (unsigned n = 0; n != 8; ++n) {
452 for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
456 for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
460 if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) {
461 for (unsigned n = 16; n != 32; ++n) {
462 for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
470 void X86RegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
471 // Check if the EFLAGS register is marked as live-out. This shouldn't happen,
472 // because the calling convention defines the EFLAGS register as NOT
475 // Unfortunatelly the EFLAGS show up as live-out after branch folding. Adding
476 // an assert to track this and clear the register afterwards to avoid
477 // unnecessary crashes during release builds.
478 assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
479 "EFLAGS are not live-out from a patchpoint.");
481 // Also clean other registers that don't need preserving (IP).
482 for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
483 Mask[Reg / 32] &= ~(1U << (Reg % 32));
486 //===----------------------------------------------------------------------===//
487 // Stack Frame Processing methods
488 //===----------------------------------------------------------------------===//
490 static bool CantUseSP(const MachineFrameInfo *MFI) {
491 return MFI->hasVarSizedObjects() || MFI->hasOpaqueSPAdjustment();
494 bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
495 const MachineFrameInfo *MFI = MF.getFrameInfo();
497 if (!EnableBasePointer)
500 // When we need stack realignment, we can't address the stack from the frame
501 // pointer. When we have dynamic allocas or stack-adjusting inline asm, we
502 // can't address variables from the stack pointer. MS inline asm can
503 // reference locals while also adjusting the stack pointer. When we can't
504 // use both the SP and the FP, we need a separate base pointer register.
505 bool CantUseFP = needsStackRealignment(MF);
506 return CantUseFP && CantUseSP(MFI);
509 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
510 if (!TargetRegisterInfo::canRealignStack(MF))
513 const MachineFrameInfo *MFI = MF.getFrameInfo();
514 const MachineRegisterInfo *MRI = &MF.getRegInfo();
516 // Stack realignment requires a frame pointer. If we already started
517 // register allocation with frame pointer elimination, it is too late now.
518 if (!MRI->canReserveReg(FramePtr))
521 // If a base pointer is necessary. Check that it isn't too late to reserve
524 return MRI->canReserveReg(BasePtr);
528 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
529 unsigned Reg, int &FrameIdx) const {
530 // Since X86 defines assignCalleeSavedSpillSlots which always return true
531 // this function neither used nor tested.
532 llvm_unreachable("Unused function on X86. Otherwise need a test case.");
536 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
537 int SPAdj, unsigned FIOperandNum,
538 RegScavenger *RS) const {
539 MachineInstr &MI = *II;
540 MachineFunction &MF = *MI.getParent()->getParent();
541 const X86FrameLowering *TFI = getFrameLowering(MF);
542 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
545 unsigned Opc = MI.getOpcode();
546 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm ||
547 Opc == X86::TCRETURNmi || Opc == X86::TCRETURNmi64;
549 if (hasBasePointer(MF))
550 BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
551 else if (needsStackRealignment(MF))
552 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
556 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
558 // LOCAL_ESCAPE uses a single offset, with no register. It only works in the
559 // simple FP case, and doesn't work with stack realignment. On 32-bit, the
560 // offset is from the traditional base pointer location. On 64-bit, the
561 // offset is from the SP at the end of the prologue, not the FP location. This
562 // matches the behavior of llvm.frameaddress.
563 unsigned IgnoredFrameReg;
564 if (Opc == TargetOpcode::LOCAL_ESCAPE) {
565 MachineOperand &FI = MI.getOperand(FIOperandNum);
567 Offset = TFI->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
568 FI.ChangeToImmediate(Offset);
572 // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
573 // register as source operand, semantic is the same and destination is
574 // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
575 if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
576 BasePtr = getX86SubSuperRegister(BasePtr, MVT::i64);
578 // This must be part of a four operand memory reference. Replace the
579 // FrameIndex with base register with EBP. Add an offset to the offset.
580 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
582 // Now add the frame object offset to the offset from EBP.
585 // Tail call jmp happens after FP is popped.
586 const MachineFrameInfo *MFI = MF.getFrameInfo();
587 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
589 FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
591 if (BasePtr == StackPtr)
594 // The frame index format for stackmaps and patchpoints is different from the
595 // X86 format. It only has a FI and an offset.
596 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
597 assert(BasePtr == FramePtr && "Expected the FP as base register");
598 int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
599 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
603 if (MI.getOperand(FIOperandNum+3).isImm()) {
604 // Offset is a 32-bit integer.
605 int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
606 int Offset = FIOffset + Imm;
607 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
608 "Requesting 64-bit offset in 32-bit immediate!");
609 MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
611 // Offset is symbolic. This is extremely rare.
612 uint64_t Offset = FIOffset +
613 (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
614 MI.getOperand(FIOperandNum + 3).setOffset(Offset);
618 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
619 const X86FrameLowering *TFI = getFrameLowering(MF);
620 return TFI->hasFP(MF) ? FramePtr : StackPtr;
624 X86RegisterInfo::getPtrSizedFrameRegister(const MachineFunction &MF) const {
625 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
626 unsigned FrameReg = getFrameRegister(MF);
627 if (Subtarget.isTarget64BitILP32())
628 FrameReg = getX86SubSuperRegister(FrameReg, MVT::i32);
633 unsigned getX86SubSuperRegisterOrZero(unsigned Reg, MVT::SimpleValueType VT,
640 default: return getX86SubSuperRegisterOrZero(Reg, MVT::i64);
641 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
643 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
645 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
647 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
649 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
651 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
653 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
655 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
661 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
663 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
665 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
667 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
669 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
671 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
673 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
675 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
677 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
679 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
681 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
683 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
685 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
687 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
689 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
691 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
698 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
700 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
702 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
704 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
706 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
708 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
710 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
712 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
714 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
716 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
718 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
720 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
722 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
724 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
726 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
728 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
734 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
736 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
738 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
740 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
742 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
744 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
746 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
748 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
750 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
752 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
754 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
756 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
758 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
760 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
762 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
764 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
770 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
772 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
774 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
776 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
778 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
780 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
782 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
784 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
786 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
788 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
790 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
792 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
794 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
796 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
798 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
800 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
806 unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT,
808 unsigned Res = getX86SubSuperRegisterOrZero(Reg, VT, High);
809 assert(Res != 0 && "Unexpected register or VT");
813 unsigned get512BitSuperRegister(unsigned Reg) {
814 if (Reg >= X86::XMM0 && Reg <= X86::XMM31)
815 return X86::ZMM0 + (Reg - X86::XMM0);
816 if (Reg >= X86::YMM0 && Reg <= X86::YMM31)
817 return X86::ZMM0 + (Reg - X86::YMM0);
818 if (Reg >= X86::ZMM0 && Reg <= X86::ZMM31)
820 llvm_unreachable("Unexpected SIMD register");