1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // This file contains the X86 implementation of the MRegisterInfo class. This
4 // file is responsible for the frame pointer elimination optimization on X86.
6 //===----------------------------------------------------------------------===//
9 #include "X86RegisterInfo.h"
10 #include "X86InstrBuilder.h"
11 #include "llvm/Constants.h"
12 #include "llvm/Type.h"
13 #include "llvm/CodeGen/MachineInstrBuilder.h"
14 #include "llvm/CodeGen/MachineFunction.h"
15 #include "llvm/CodeGen/MachineFrameInfo.h"
16 #include "llvm/Target/TargetMachine.h"
17 #include "llvm/Target/TargetFrameInfo.h"
18 #include "Support/CommandLine.h"
22 NoFPElim("disable-fp-elim",
23 cl::desc("Disable frame pointer elimination optimization"));
26 static unsigned getIdx(const TargetRegisterClass *RC) {
27 switch (RC->getSize()) {
28 default: assert(0 && "Invalid data size!");
36 void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
37 MachineBasicBlock::iterator &MBBI,
38 unsigned SrcReg, int FrameIdx,
39 const TargetRegisterClass *RC) const {
40 static const unsigned Opcode[] =
41 { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FSTPr80 };
42 MachineInstr *MI = addFrameReference(BuildMI(Opcode[getIdx(RC)], 5),
43 FrameIdx).addReg(SrcReg);
44 MBBI = MBB.insert(MBBI, MI)+1;
47 void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
48 MachineBasicBlock::iterator &MBBI,
49 unsigned DestReg, int FrameIdx,
50 const TargetRegisterClass *RC) const{
51 static const unsigned Opcode[] =
52 { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FLDr80 };
53 MachineInstr *MI = addFrameReference(BuildMI(Opcode[getIdx(RC)], 4, DestReg),
55 MBBI = MBB.insert(MBBI, MI)+1;
58 void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
59 MachineBasicBlock::iterator &MBBI,
60 unsigned DestReg, unsigned SrcReg,
61 const TargetRegisterClass *RC) const {
62 static const unsigned Opcode[] =
63 { X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV };
64 MachineInstr *MI = BuildMI(Opcode[getIdx(RC)],1,DestReg).addReg(SrcReg);
65 MBBI = MBB.insert(MBBI, MI)+1;
68 const unsigned* X86RegisterInfo::getCalleeSaveRegs() const {
69 static const unsigned CalleeSaveRegs[] = {
70 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
72 return CalleeSaveRegs;
76 //===----------------------------------------------------------------------===//
77 // Stack Frame Processing methods
78 //===----------------------------------------------------------------------===//
80 // hasFP - Return true if the specified function should have a dedicated frame
81 // pointer register. This is true if the function has variable sized allocas or
82 // if frame pointer elimination is disabled.
84 static bool hasFP(MachineFunction &MF) {
85 return NoFPElim || MF.getFrameInfo()->hasVarSizedObjects();
88 // hasSPAdjust - Return true if this function has ESP adjustment instructions in
89 // the prolog and epilog which allocate local stack space. This is neccesary
90 // because we elide these instructions if there are no function calls in the
91 // current function (ie, this is a leaf function). In this case, we can refer
92 // beyond the stack pointer because we know that nothing will trample on that
95 static bool hasSPAdjust(MachineFunction &MF) {
96 assert(!hasFP(MF) && "Can only eliminate SP adjustment if no frame-pointer!");
97 return MF.getFrameInfo()->hasCalls();
100 void X86RegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF,
101 MachineBasicBlock &MBB,
102 MachineBasicBlock::iterator &I) const {
103 MachineInstr *New = 0, *Old = *I;;
105 // If we have a frame pointer, turn the adjcallstackup instruction into a
106 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
108 unsigned Amount = Old->getOperand(0).getImmedValue();
110 // We need to keep the stack aligned properly. To do this, we round the
111 // amount of space needed for the outgoing arguments up to the next
112 // alignment boundary.
113 unsigned Align = MF.getTarget().getFrameInfo().getStackAlignment();
114 Amount = (Amount+Align-1)/Align*Align;
116 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
117 New=BuildMI(X86::SUBri32, 2, X86::ESP).addReg(X86::ESP).addZImm(Amount);
119 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
120 New=BuildMI(X86::ADDri32, 2, X86::ESP).addReg(X86::ESP).addZImm(Amount);
126 *I = New; // Replace the pseudo instruction with a new instruction...
128 I = MBB.erase(I);// Just delete the pseudo instruction...
132 void X86RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
133 MachineBasicBlock::iterator &II) const {
135 MachineInstr &MI = **II;
136 while (!MI.getOperand(i).isFrameIndex()) {
138 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
141 int FrameIndex = MI.getOperand(i).getFrameIndex();
143 // This must be part of a four operand memory reference. Replace the
144 // FrameIndex with base register with EBP. Add add an offset to the offset.
145 MI.SetMachineOperandReg(i, hasFP(MF) ? X86::EBP : X86::ESP);
147 // Now add the frame object offset to the offset from EBP.
148 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
149 MI.getOperand(i+3).getImmedValue()+4;
151 if (!hasFP(MF) && hasSPAdjust(MF)) {
152 const MachineFrameInfo *MFI = MF.getFrameInfo();
153 Offset += MFI->getStackSize();
156 MI.SetMachineOperandConst(i+3, MachineOperand::MO_SignExtendedImmed, Offset);
159 void X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
162 // Create a frame entry for the EBP register that must be saved.
163 int FrameIdx = MF.getFrameInfo()->CreateStackObject(4, 4);
164 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexEnd()-1 &&
165 "Slot for EBP register must be last in order to be found!");
169 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
170 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
171 MachineBasicBlock::iterator MBBI = MBB.begin();
172 MachineFrameInfo *MFI = MF.getFrameInfo();
175 // Get the number of bytes to allocate from the FrameInfo
176 unsigned NumBytes = MFI->getStackSize();
178 // Get the offset of the stack slot for the EBP register... which is
179 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
180 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1)+4;
182 MI = addRegOffset(BuildMI(X86::MOVrm32, 5), // mov [ESP-<offset>], EBP
183 X86::ESP, EBPOffset).addReg(X86::EBP);
184 MBBI = MBB.insert(MBBI, MI)+1;
186 MI = BuildMI(X86::MOVrr32, 2, X86::EBP).addReg(X86::ESP);
187 MBBI = MBB.insert(MBBI, MI)+1;
189 // If we don't have a frame pointer, and the function contains no call sites
190 // (it's a leaf function), we don't have to emit ANY stack adjustment
191 // instructions at all, we can just refer to the area beyond the stack
192 // pointer. This can be important for small functions.
194 if (!hasSPAdjust(MF)) return;
196 // When we have no frame pointer, we reserve argument space for call sites
197 // in the function immediately on entry to the current function. This
198 // eliminates the need for add/sub ESP brackets around call sites.
200 NumBytes += MFI->getMaxCallFrameSize();
202 // Round the size to a multiple of the alignment (don't forget the 4 byte
204 unsigned Align = MF.getTarget().getFrameInfo().getStackAlignment();
205 NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
207 // Update frame info to pretend that this is part of the stack...
208 MFI->setStackSize(NumBytes);
212 // adjust stack pointer: ESP -= numbytes
213 MI = BuildMI(X86::SUBri32, 2, X86::ESP).addReg(X86::ESP).addZImm(NumBytes);
214 MBBI = 1+MBB.insert(MBBI, MI);
218 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
219 MachineBasicBlock &MBB) const {
220 const MachineFrameInfo *MFI = MF.getFrameInfo();
221 MachineBasicBlock::iterator MBBI = MBB.end()-1;
223 assert((*MBBI)->getOpcode() == X86::RET &&
224 "Can only insert epilog into returning blocks");
227 // Get the offset of the stack slot for the EBP register... which is
228 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
229 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1)+4;
232 MI = BuildMI(X86::MOVrr32, 1,X86::ESP).addReg(X86::EBP);
233 MBBI = 1+MBB.insert(MBBI, MI);
235 // mov EBP, [ESP-<offset>]
236 MI = addRegOffset(BuildMI(X86::MOVmr32, 5, X86::EBP), X86::ESP, EBPOffset);
237 MBBI = 1+MBB.insert(MBBI, MI);
239 if (!hasSPAdjust(MF)) return;
241 // Get the number of bytes allocated from the FrameInfo...
242 unsigned NumBytes = MFI->getStackSize();
244 if (NumBytes) { // adjust stack pointer back: ESP += numbytes
245 MI =BuildMI(X86::ADDri32, 2, X86::ESP).addReg(X86::ESP).addZImm(NumBytes);
246 MBBI = 1+MBB.insert(MBBI, MI);
252 //===----------------------------------------------------------------------===//
253 // Register Class Implementation Code
254 //===----------------------------------------------------------------------===//
256 //===----------------------------------------------------------------------===//
257 // 8 Bit Integer Registers
260 const unsigned ByteRegClassRegs[] = {
261 X86::AL, X86::CL, X86::DL, X86::BL, X86::AH, X86::CH, X86::DH, X86::BH,
264 TargetRegisterClass X86ByteRegisterClassInstance(1, 1, ByteRegClassRegs,
265 ByteRegClassRegs+sizeof(ByteRegClassRegs)/sizeof(ByteRegClassRegs[0]));
267 //===----------------------------------------------------------------------===//
268 // 16 Bit Integer Registers
270 const unsigned ShortRegClassRegs[] = {
271 X86::AX, X86::CX, X86::DX, X86::BX, X86::SI, X86::DI, X86::BP, X86::SP
274 struct R16CL : public TargetRegisterClass {
275 R16CL():TargetRegisterClass(2, 2, ShortRegClassRegs, ShortRegClassRegs+8) {}
276 iterator allocation_order_end(MachineFunction &MF) const {
277 if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
278 return end()-2; // Don't allocate SP or BP
280 return end()-1; // Don't allocate SP
282 } X86ShortRegisterClassInstance;
284 //===----------------------------------------------------------------------===//
285 // 32 Bit Integer Registers
287 const unsigned IntRegClassRegs[] = {
288 X86::EAX, X86::ECX, X86::EDX, X86::EBX,
289 X86::ESI, X86::EDI, X86::EBP, X86::ESP
292 struct R32CL : public TargetRegisterClass {
293 R32CL() : TargetRegisterClass(4, 4, IntRegClassRegs, IntRegClassRegs+8) {}
294 iterator allocation_order_end(MachineFunction &MF) const {
295 if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
296 return end()-2; // Don't allocate ESP or EBP
298 return end()-1; // Don't allocate ESP
300 } X86IntRegisterClassInstance;
302 //===----------------------------------------------------------------------===//
303 // Pseudo Floating Point Registers
305 const unsigned PFPRegClassRegs[] = {
306 #define PFP(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) X86::ENUM,
307 #include "X86RegisterInfo.def"
310 TargetRegisterClass X86FPRegisterClassInstance(10, 4, PFPRegClassRegs,
311 PFPRegClassRegs+sizeof(PFPRegClassRegs)/sizeof(PFPRegClassRegs[0]));
313 //===----------------------------------------------------------------------===//
314 // Register class array...
316 const TargetRegisterClass * const X86RegClasses[] = {
317 &X86ByteRegisterClassInstance,
318 &X86ShortRegisterClassInstance,
319 &X86IntRegisterClassInstance,
320 &X86FPRegisterClassInstance,
325 // Create static lists to contain register alias sets...
326 #define ALIASLIST(NAME, ...) \
327 static const unsigned NAME[] = { __VA_ARGS__ };
328 #include "X86RegisterInfo.def"
331 // X86Regs - Turn the X86RegisterInfo.def file into a bunch of register
334 static const MRegisterDesc X86Regs[] = {
335 #define R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
336 { NAME, ALIAS_SET, FLAGS, TSFLAGS },
337 #include "X86RegisterInfo.def"
340 X86RegisterInfo::X86RegisterInfo()
341 : MRegisterInfo(X86Regs, sizeof(X86Regs)/sizeof(X86Regs[0]),
343 X86RegClasses+sizeof(X86RegClasses)/sizeof(X86RegClasses[0]),
344 X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {
349 const TargetRegisterClass*
350 X86RegisterInfo::getRegClassForType(const Type* Ty) const {
351 switch (Ty->getPrimitiveID()) {
353 case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
354 default: assert(0 && "Invalid type to getClass!");
356 case Type::SByteTyID:
357 case Type::UByteTyID: return &X86ByteRegisterClassInstance;
358 case Type::ShortTyID:
359 case Type::UShortTyID: return &X86ShortRegisterClassInstance;
362 case Type::PointerTyID: return &X86IntRegisterClassInstance;
364 case Type::FloatTyID:
365 case Type::DoubleTyID: return &X86FPRegisterClassInstance;