1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/MachineValueType.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Type.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Target/TargetFrameLowering.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetOptions.h"
43 #define GET_REGINFO_TARGET_DESC
44 #include "X86GenRegisterInfo.inc"
47 ForceStackAlign("force-align-stack",
48 cl::desc("Force align the stack to the minimum alignment"
49 " needed for the function."),
50 cl::init(false), cl::Hidden);
53 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
54 cl::desc("Enable use of a base pointer for complex stack frames"));
56 X86RegisterInfo::X86RegisterInfo(const Triple &TT)
57 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
58 X86_MC::getDwarfRegFlavour(TT, false),
59 X86_MC::getDwarfRegFlavour(TT, true),
60 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
61 X86_MC::InitLLVM2SEHRegisterMapping(this);
63 // Cache some information.
64 Is64Bit = TT.isArch64Bit();
65 IsWin64 = Is64Bit && TT.isOSWindows();
67 // Use a callee-saved register as the base pointer. These registers must
68 // not conflict with any ABI requirements. For example, in 32-bit mode PIC
69 // requires GOT in the EBX register before function calls via PLT GOT pointer.
72 // This matches the simplified 32-bit pointer code in the data layout
74 // FIXME: Should use the data layout?
75 bool Use64BitReg = TT.getEnvironment() != Triple::GNUX32;
76 StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
77 FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
78 BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
88 X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
89 // ExeDepsFixer and PostRAScheduler require liveness.
94 X86RegisterInfo::getSEHRegNum(unsigned i) const {
95 return getEncodingValue(i);
98 const TargetRegisterClass *
99 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
100 unsigned Idx) const {
101 // The sub_8bit sub-register index is more constrained in 32-bit mode.
102 // It behaves just like the sub_8bit_hi index.
103 if (!Is64Bit && Idx == X86::sub_8bit)
104 Idx = X86::sub_8bit_hi;
106 // Forward to TableGen's default version.
107 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
110 const TargetRegisterClass *
111 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
112 const TargetRegisterClass *B,
113 unsigned SubIdx) const {
114 // The sub_8bit sub-register index is more constrained in 32-bit mode.
115 if (!Is64Bit && SubIdx == X86::sub_8bit) {
116 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
120 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
123 const TargetRegisterClass *
124 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
125 const MachineFunction &MF) const {
126 // Don't allow super-classes of GR8_NOREX. This class is only used after
127 // extracting sub_8bit_hi sub-registers. The H sub-registers cannot be copied
128 // to the full GR8 register class in 64-bit mode, so we cannot allow the
129 // reigster class inflation.
131 // The GR8_NOREX class is always used in a way that won't be constrained to a
132 // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
134 if (RC == &X86::GR8_NOREXRegClass)
137 const TargetRegisterClass *Super = RC;
138 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
140 switch (Super->getID()) {
141 case X86::GR8RegClassID:
142 case X86::GR16RegClassID:
143 case X86::GR32RegClassID:
144 case X86::GR64RegClassID:
145 case X86::FR32RegClassID:
146 case X86::FR64RegClassID:
147 case X86::RFP32RegClassID:
148 case X86::RFP64RegClassID:
149 case X86::RFP80RegClassID:
150 case X86::VR128RegClassID:
151 case X86::VR256RegClassID:
152 // Don't return a super-class that would shrink the spill size.
153 // That can happen with the vector and float classes.
154 if (Super->getSize() == RC->getSize())
162 const TargetRegisterClass *
163 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
164 unsigned Kind) const {
165 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
167 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
168 case 0: // Normal GPRs.
169 if (Subtarget.isTarget64BitLP64())
170 return &X86::GR64RegClass;
171 return &X86::GR32RegClass;
172 case 1: // Normal GPRs except the stack pointer (for encoding reasons).
173 if (Subtarget.isTarget64BitLP64())
174 return &X86::GR64_NOSPRegClass;
175 return &X86::GR32_NOSPRegClass;
176 case 2: // Available for tailcall (not callee-saved GPRs).
178 return &X86::GR64_TCW64RegClass;
180 return &X86::GR64_TCRegClass;
182 const Function *F = MF.getFunction();
183 bool hasHipeCC = (F ? F->getCallingConv() == CallingConv::HiPE : false);
185 return &X86::GR32RegClass;
186 return &X86::GR32_TCRegClass;
190 const TargetRegisterClass *
191 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
192 if (RC == &X86::CCRRegClass) {
194 return &X86::GR64RegClass;
196 return &X86::GR32RegClass;
202 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
203 MachineFunction &MF) const {
204 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
206 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
207 switch (RC->getID()) {
210 case X86::GR32RegClassID:
212 case X86::GR64RegClassID:
214 case X86::VR128RegClassID:
215 return Is64Bit ? 10 : 4;
216 case X86::VR64RegClassID:
222 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
223 const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();
224 bool HasAVX = Subtarget.hasAVX();
225 bool HasAVX512 = Subtarget.hasAVX512();
226 bool CallsEHReturn = MF->getMMI().callsEHReturn();
228 assert(MF && "MachineFunction required");
229 switch (MF->getFunction()->getCallingConv()) {
230 case CallingConv::GHC:
231 case CallingConv::HiPE:
232 return CSR_NoRegs_SaveList;
233 case CallingConv::AnyReg:
235 return CSR_64_AllRegs_AVX_SaveList;
236 return CSR_64_AllRegs_SaveList;
237 case CallingConv::PreserveMost:
238 return CSR_64_RT_MostRegs_SaveList;
239 case CallingConv::PreserveAll:
241 return CSR_64_RT_AllRegs_AVX_SaveList;
242 return CSR_64_RT_AllRegs_SaveList;
243 case CallingConv::Intel_OCL_BI: {
244 if (HasAVX512 && IsWin64)
245 return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
246 if (HasAVX512 && Is64Bit)
247 return CSR_64_Intel_OCL_BI_AVX512_SaveList;
248 if (HasAVX && IsWin64)
249 return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
250 if (HasAVX && Is64Bit)
251 return CSR_64_Intel_OCL_BI_AVX_SaveList;
252 if (!HasAVX && !IsWin64 && Is64Bit)
253 return CSR_64_Intel_OCL_BI_SaveList;
256 case CallingConv::Cold:
258 return CSR_64_MostRegs_SaveList;
260 case CallingConv::X86_64_Win64:
261 return CSR_Win64_SaveList;
262 case CallingConv::X86_64_SysV:
264 return CSR_64EHRet_SaveList;
265 return CSR_64_SaveList;
272 return CSR_Win64_SaveList;
274 return CSR_64EHRet_SaveList;
275 return CSR_64_SaveList;
278 return CSR_32EHRet_SaveList;
279 return CSR_32_SaveList;
283 X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
284 CallingConv::ID CC) const {
285 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
286 bool HasAVX = Subtarget.hasAVX();
287 bool HasAVX512 = Subtarget.hasAVX512();
290 case CallingConv::GHC:
291 case CallingConv::HiPE:
292 return CSR_NoRegs_RegMask;
293 case CallingConv::AnyReg:
295 return CSR_64_AllRegs_AVX_RegMask;
296 return CSR_64_AllRegs_RegMask;
297 case CallingConv::PreserveMost:
298 return CSR_64_RT_MostRegs_RegMask;
299 case CallingConv::PreserveAll:
301 return CSR_64_RT_AllRegs_AVX_RegMask;
302 return CSR_64_RT_AllRegs_RegMask;
303 case CallingConv::Intel_OCL_BI: {
304 if (HasAVX512 && IsWin64)
305 return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
306 if (HasAVX512 && Is64Bit)
307 return CSR_64_Intel_OCL_BI_AVX512_RegMask;
308 if (HasAVX && IsWin64)
309 return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
310 if (HasAVX && Is64Bit)
311 return CSR_64_Intel_OCL_BI_AVX_RegMask;
312 if (!HasAVX && !IsWin64 && Is64Bit)
313 return CSR_64_Intel_OCL_BI_RegMask;
316 case CallingConv::Cold:
318 return CSR_64_MostRegs_RegMask;
322 case CallingConv::X86_64_Win64:
323 return CSR_Win64_RegMask;
324 case CallingConv::X86_64_SysV:
325 return CSR_64_RegMask;
328 // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
332 return CSR_Win64_RegMask;
333 return CSR_64_RegMask;
335 return CSR_32_RegMask;
339 X86RegisterInfo::getNoPreservedMask() const {
340 return CSR_NoRegs_RegMask;
343 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
344 BitVector Reserved(getNumRegs());
345 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
347 // Set the stack-pointer register and its aliases as reserved.
348 for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
352 // Set the instruction pointer register and its aliases as reserved.
353 for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
357 // Set the frame-pointer register and its aliases as reserved if needed.
358 if (TFI->hasFP(MF)) {
359 for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
364 // Set the base-pointer register and its aliases as reserved if needed.
365 if (hasBasePointer(MF)) {
366 CallingConv::ID CC = MF.getFunction()->getCallingConv();
367 const uint32_t *RegMask = getCallPreservedMask(MF, CC);
368 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
370 "Stack realignment in presence of dynamic allocas is not supported with"
371 "this calling convention.");
373 unsigned BasePtr = getX86SubSuperRegister(getBaseRegister(), MVT::i64,
375 for (MCSubRegIterator I(BasePtr, this, /*IncludeSelf=*/true);
380 // Mark the segment registers as reserved.
381 Reserved.set(X86::CS);
382 Reserved.set(X86::SS);
383 Reserved.set(X86::DS);
384 Reserved.set(X86::ES);
385 Reserved.set(X86::FS);
386 Reserved.set(X86::GS);
388 // Mark the floating point stack registers as reserved.
389 for (unsigned n = 0; n != 8; ++n)
390 Reserved.set(X86::ST0 + n);
392 // Reserve the registers that only exist in 64-bit mode.
394 // These 8-bit registers are part of the x86-64 extension even though their
395 // super-registers are old 32-bits.
396 Reserved.set(X86::SIL);
397 Reserved.set(X86::DIL);
398 Reserved.set(X86::BPL);
399 Reserved.set(X86::SPL);
401 for (unsigned n = 0; n != 8; ++n) {
403 for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
407 for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
411 if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) {
412 for (unsigned n = 16; n != 32; ++n) {
413 for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
421 //===----------------------------------------------------------------------===//
422 // Stack Frame Processing methods
423 //===----------------------------------------------------------------------===//
425 bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
426 const MachineFrameInfo *MFI = MF.getFrameInfo();
428 if (!EnableBasePointer)
431 // When we need stack realignment, we can't address the stack from the frame
432 // pointer. When we have dynamic allocas or stack-adjusting inline asm, we
433 // can't address variables from the stack pointer. MS inline asm can
434 // reference locals while also adjusting the stack pointer. When we can't
435 // use both the SP and the FP, we need a separate base pointer register.
436 bool CantUseFP = needsStackRealignment(MF);
438 MFI->hasVarSizedObjects() || MFI->hasInlineAsmWithSPAdjust();
439 return CantUseFP && CantUseSP;
442 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
443 if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
446 const MachineFrameInfo *MFI = MF.getFrameInfo();
447 const MachineRegisterInfo *MRI = &MF.getRegInfo();
449 // Stack realignment requires a frame pointer. If we already started
450 // register allocation with frame pointer elimination, it is too late now.
451 if (!MRI->canReserveReg(FramePtr))
454 // If a base pointer is necessary. Check that it isn't too late to reserve
456 if (MFI->hasVarSizedObjects())
457 return MRI->canReserveReg(BasePtr);
461 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
462 const MachineFrameInfo *MFI = MF.getFrameInfo();
463 const Function *F = MF.getFunction();
464 unsigned StackAlign =
465 MF.getSubtarget().getFrameLowering()->getStackAlignment();
466 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
467 F->hasFnAttribute(Attribute::StackAlignment));
469 // If we've requested that we force align the stack do so now.
471 return canRealignStack(MF);
473 return requiresRealignment && canRealignStack(MF);
476 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
477 unsigned Reg, int &FrameIdx) const {
478 // Since X86 defines assignCalleeSavedSpillSlots which always return true
479 // this function neither used nor tested.
480 llvm_unreachable("Unused function on X86. Otherwise need a test case.");
484 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
485 int SPAdj, unsigned FIOperandNum,
486 RegScavenger *RS) const {
487 MachineInstr &MI = *II;
488 MachineFunction &MF = *MI.getParent()->getParent();
489 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
490 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
493 unsigned Opc = MI.getOpcode();
494 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
495 if (hasBasePointer(MF))
496 BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
497 else if (needsStackRealignment(MF))
498 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
502 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
504 // FRAME_ALLOC uses a single offset, with no register. It only works in the
505 // simple FP case, and doesn't work with stack realignment. On 32-bit, the
506 // offset is from the traditional base pointer location. On 64-bit, the
507 // offset is from the SP at the end of the prologue, not the FP location. This
508 // matches the behavior of llvm.frameaddress.
509 if (Opc == TargetOpcode::FRAME_ALLOC) {
510 assert(TFI->hasFP(MF) && "frame alloc requires FP");
511 MachineOperand &FI = MI.getOperand(FIOperandNum);
512 const MachineFrameInfo *MFI = MF.getFrameInfo();
513 int Offset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
514 bool IsWinEH = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
516 Offset += MFI->getStackSize();
519 FI.ChangeToImmediate(Offset);
523 // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
524 // register as source operand, semantic is the same and destination is
525 // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
526 if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
527 BasePtr = getX86SubSuperRegister(BasePtr, MVT::i64, false);
529 // This must be part of a four operand memory reference. Replace the
530 // FrameIndex with base register with EBP. Add an offset to the offset.
531 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
533 // Now add the frame object offset to the offset from EBP.
536 // Tail call jmp happens after FP is popped.
537 const MachineFrameInfo *MFI = MF.getFrameInfo();
538 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
540 FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
542 if (BasePtr == StackPtr)
545 // The frame index format for stackmaps and patchpoints is different from the
546 // X86 format. It only has a FI and an offset.
547 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
548 assert(BasePtr == FramePtr && "Expected the FP as base register");
549 int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
550 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
554 if (MI.getOperand(FIOperandNum+3).isImm()) {
555 // Offset is a 32-bit integer.
556 int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
557 int Offset = FIOffset + Imm;
558 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
559 "Requesting 64-bit offset in 32-bit immediate!");
560 MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
562 // Offset is symbolic. This is extremely rare.
563 uint64_t Offset = FIOffset +
564 (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
565 MI.getOperand(FIOperandNum + 3).setOffset(Offset);
569 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
570 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
571 return TFI->hasFP(MF) ? FramePtr : StackPtr;
575 X86RegisterInfo::getPtrSizedFrameRegister(const MachineFunction &MF) const {
576 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
577 unsigned FrameReg = getFrameRegister(MF);
578 if (Subtarget.isTarget64BitILP32())
579 FrameReg = getX86SubSuperRegister(FrameReg, MVT::i32, false);
584 unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT,
587 default: llvm_unreachable("Unexpected VT");
591 default: return getX86SubSuperRegister(Reg, MVT::i64);
592 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
594 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
596 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
598 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
600 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
602 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
604 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
606 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
611 default: llvm_unreachable("Unexpected register");
612 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
614 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
616 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
618 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
620 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
622 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
624 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
626 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
628 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
630 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
632 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
634 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
636 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
638 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
640 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
642 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
648 default: llvm_unreachable("Unexpected register");
649 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
651 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
653 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
655 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
657 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
659 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
661 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
663 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
665 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
667 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
669 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
671 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
673 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
675 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
677 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
679 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
684 default: llvm_unreachable("Unexpected register");
685 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
687 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
689 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
691 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
693 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
695 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
697 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
699 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
701 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
703 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
705 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
707 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
709 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
711 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
713 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
715 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
720 default: llvm_unreachable("Unexpected register");
721 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
723 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
725 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
727 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
729 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
731 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
733 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
735 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
737 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
739 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
741 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
743 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
745 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
747 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
749 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
751 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
757 unsigned get512BitSuperRegister(unsigned Reg) {
758 if (Reg >= X86::XMM0 && Reg <= X86::XMM31)
759 return X86::ZMM0 + (Reg - X86::XMM0);
760 if (Reg >= X86::YMM0 && Reg <= X86::YMM31)
761 return X86::ZMM0 + (Reg - X86::YMM0);
762 if (Reg >= X86::ZMM0 && Reg <= X86::ZMM31)
764 llvm_unreachable("Unexpected SIMD register");