1 //===-- X86RegisterInfo.def - X86 Register Information ----------*- C++ -*-===//
3 // This file describes all of the registers that the X86 backend uses. It relies
4 // on an external 'R' macro being defined that takes the arguments specified
5 // below, and is used to make all of the information relevant to registers be in
8 //===----------------------------------------------------------------------===//
10 // NOTE: No include guards desired
12 #errror "Must define R macro before including X86/X86RegisterInfo.def!"
16 #define R8(ENUM, NAME, FLAGS, TSFLAGS) R(ENUM, NAME, FLAGS, TSFLAGS)
20 #define R16(ENUM, NAME, FLAGS, TSFLAGS) R(ENUM, NAME, FLAGS, TSFLAGS)
24 #define R32(ENUM, NAME, FLAGS, TSFLAGS) R(ENUM, NAME, FLAGS, TSFLAGS)
27 // Arguments passed into the R macro
28 // #1: Enum Name - This ends up being a symbol in the X86 namespace
29 // #2: Register name - The name of the register as used by the gnu assembler
30 // #3: Register Flags - A bitfield of flags or'd together from the
31 // MRegisterInfo.h file.
32 // #4: Target Specific Flags - Another bitfield containing X86 specific flags
36 // The first register must always be a 'noop' register for all backends. This
37 // is used as the destination register for instructions that do not produce a
38 // value. Some frontends may use this as an operand register to mean special
39 // things, for example, the Sparc backend uses R#0 to mean %g0 which always
40 // PRODUCES the value 0.
42 // The X86 backend uses this value as an operand register only in memory
43 // references where it means that there is no base or index register.
45 R(NoReg, "none", 0, 0)
47 // 32 bit registers, ordered as the processor does...
48 R32(EAX, "EAX", MRF::INT32, 0)
49 R32(ECX, "ECX", MRF::INT32, 0)
50 R32(EDX, "EDX", MRF::INT32, 0)
51 R32(EBX, "EBX", MRF::INT32, 0)
52 R32(ESP, "ESP", MRF::INT32, 0)
53 R32(EBP, "EBP", MRF::INT32, 0)
54 R32(ESI, "ESI", MRF::INT32, 0)
55 R32(EDI, "EDI", MRF::INT32, 0)
57 // 16 bit registers, aliased with the corresponding 32 bit registers above
58 R16(AX, "AX", MRF::INT16, 0)
59 R16(CX, "CX", MRF::INT16, 0)
60 R16(DX, "DX", MRF::INT16, 0)
61 R16(BX, "BX", MRF::INT16, 0)
62 R16(SP, "SP", MRF::INT16, 0)
63 R16(BP, "BP", MRF::INT16, 0)
64 R16(SI, "SI", MRF::INT16, 0)
65 R16(DI, "DI", MRF::INT16, 0)
67 // 8 bit registers aliased with registers above as well
68 R8(AL, "AL", MRF::INT8, 0)
69 R8(CL, "CL", MRF::INT8, 0)
70 R8(DL, "DL", MRF::INT8, 0)
71 R8(BL, "BL", MRF::INT8, 0)
72 R8(AH, "AH", MRF::INT8, 0)
73 R8(CH, "CH", MRF::INT8, 0)
74 R8(DH, "DH", MRF::INT8, 0)
75 R8(BH, "BH", MRF::INT8, 0)
77 // Flags, Segment registers, etc...
79 // This is a slimy hack to make it possible to say that flags are clobbered...
80 // Ideally we'd model instructions based on which particular flag(s) they
82 R(EFLAGS, "EFLAGS", MRF::INT16, 0)
84 // We are now done with the R* macros