1 //===-- X86RegisterInfo.def - X86 Register Information ----------*- C++ -*-===//
3 // This file describes all of the registers that the X86 backend uses. It relies
4 // on an external 'R' macro being defined that takes the arguments specified
5 // below, and is used to make all of the information relevant to registers be in
8 //===----------------------------------------------------------------------===//
10 // NOTE: No include guards desired
12 #define R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
16 #define R8(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
17 R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
21 #define R16(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
22 R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
26 #define R32(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
27 R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
30 // Pseudo Floating Point registers
32 #define PFP(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
33 R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
36 // Floating Point Stack registers
38 #define FPS(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
39 R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
42 // Arguments passed into the R macros
43 // #1: Enum Name - This ends up being a symbol in the X86 namespace
44 // #2: Register name - The name of the register as used by the gnu assembler
45 // #3: Register Flags - A bitfield of flags or'd together from the
46 // MRegisterInfo.h file.
47 // #4: Target Specific Flags - Another bitfield containing X86 specific flags
49 // #5: Alias set for registers aliased to this register (sets defined below).
52 // The first register must always be a 'noop' register for all backends. This
53 // is used as the destination register for instructions that do not produce a
54 // value. Some frontends may use this as an operand register to mean special
55 // things, for example, the Sparc backend uses R#0 to mean %g0 which always
56 // PRODUCES the value 0.
58 // The X86 backend uses this value as an operand register only in memory
59 // references where it means that there is no base or index register.
61 R(NoReg,"none", 0, 0, 0/*noalias*/)
63 // 32 bit registers, ordered as the processor does...
64 R32(EAX, "EAX", MRF::INT32, 0, A_EAX)
65 R32(ECX, "ECX", MRF::INT32, 0, A_ECX)
66 R32(EDX, "EDX", MRF::INT32, 0, A_EDX)
67 R32(EBX, "EBX", MRF::INT32, 0, A_EBX)
68 R32(ESP, "ESP", MRF::INT32, 0, A_ESP)
69 R32(EBP, "EBP", MRF::INT32, 0, A_EBP)
70 R32(ESI, "ESI", MRF::INT32, 0, A_ESI)
71 R32(EDI, "EDI", MRF::INT32, 0, A_EDI)
73 // 16 bit registers, aliased with the corresponding 32 bit registers above
74 R16( AX, "AX" , MRF::INT16, 0, A_AX)
75 R16( CX, "CX" , MRF::INT16, 0, A_CX)
76 R16( DX, "DX" , MRF::INT16, 0, A_DX)
77 R16( BX, "BX" , MRF::INT16, 0, A_BX)
78 R16( SP, "SP" , MRF::INT16, 0, A_SP)
79 R16( BP, "BP" , MRF::INT16, 0, A_BP)
80 R16( SI, "SI" , MRF::INT16, 0, A_SI)
81 R16( DI, "DI" , MRF::INT16, 0, A_DI)
83 // 8 bit registers aliased with registers above as well
84 R8 ( AL, "AL" , MRF::INT8 , 0, A_AL)
85 R8 ( CL, "CL" , MRF::INT8 , 0, A_CL)
86 R8 ( DL, "DL" , MRF::INT8 , 0, A_DL)
87 R8 ( BL, "BL" , MRF::INT8 , 0, A_BL)
88 R8 ( AH, "AH" , MRF::INT8 , 0, A_AH)
89 R8 ( CH, "CH" , MRF::INT8 , 0, A_CH)
90 R8 ( DH, "DH" , MRF::INT8 , 0, A_DH)
91 R8 ( BH, "BH" , MRF::INT8 , 0, A_BH)
93 // Pseudo Floating Point Registers
94 PFP(FP0, "FP0", MRF::FP80 , 0, 0 /*noalias*/)
95 PFP(FP1, "FP1", MRF::FP80 , 0, 0 /*noalias*/)
96 PFP(FP2, "FP2", MRF::FP80 , 0, 0 /*noalias*/)
97 PFP(FP3, "FP3", MRF::FP80 , 0, 0 /*noalias*/)
98 PFP(FP4, "FP4", MRF::FP80 , 0, 0 /*noalias*/)
99 PFP(FP5, "FP5", MRF::FP80 , 0, 0 /*noalias*/)
100 PFP(FP6, "FP6", MRF::FP80 , 0, 0 /*noalias*/)
102 // Floating point stack registers
103 FPS(ST0, "ST(0)", MRF::FP80, 0, 0)
104 FPS(ST1, "ST(1)", MRF::FP80, 0, 0)
105 FPS(ST2, "ST(2)", MRF::FP80, 0, 0)
106 FPS(ST3, "ST(3)", MRF::FP80, 0, 0)
107 FPS(ST4, "ST(4)", MRF::FP80, 0, 0)
108 FPS(ST5, "ST(5)", MRF::FP80, 0, 0)
109 FPS(ST6, "ST(6)", MRF::FP80, 0, 0)
110 FPS(ST7, "ST(7)", MRF::FP80, 0, 0)
112 // Flags, Segment registers, etc...
114 // This is a slimy hack to make it possible to say that flags are clobbered...
115 // Ideally we'd model instructions based on which particular flag(s) they
117 R(EFLAGS, "EFLAGS", MRF::INT16, 0, 0 /*noalias*/)
120 //===----------------------------------------------------------------------===//
121 // Register alias set handling...
124 // Macro to handle definitions of alias sets that registers use...
126 #define ALIASLIST(NAME, ...)
129 ALIASLIST(A_EAX , X86::AX, X86::AH, X86::AL, 0)
130 ALIASLIST(A_ECX , X86::CX, X86::CH, X86::CL, 0)
131 ALIASLIST(A_EDX , X86::DX, X86::DH, X86::DL, 0)
132 ALIASLIST(A_EBX , X86::BX, X86::BH, X86::BL, 0)
133 ALIASLIST(A_ESP , X86::SP, 0)
134 ALIASLIST(A_EBP , X86::BP, 0)
135 ALIASLIST(A_ESI , X86::SI, 0)
136 ALIASLIST(A_EDI , X86::DI, 0)
137 ALIASLIST(A_AX , X86::EAX, X86::AH, X86::AL, 0)
138 ALIASLIST(A_CX , X86::ECX, X86::CH, X86::CL, 0)
139 ALIASLIST(A_DX , X86::EDX, X86::DH, X86::DL, 0)
140 ALIASLIST(A_BX , X86::EBX, X86::BH, X86::BL, 0)
141 ALIASLIST(A_SP , X86::ESP, 0)
142 ALIASLIST(A_BP , X86::EBP, 0)
143 ALIASLIST(A_SI , X86::ESI, 0)
144 ALIASLIST(A_DI , X86::EDI, 0)
145 ALIASLIST(A_AL , X86::EAX, X86::AX, 0)
146 ALIASLIST(A_CL , X86::ECX, X86::CX, 0)
147 ALIASLIST(A_DL , X86::EDX, X86::DX, 0)
148 ALIASLIST(A_BL , X86::EBX, X86::BX, 0)
149 ALIASLIST(A_AH , X86::EAX, X86::AX, 0)
150 ALIASLIST(A_CH , X86::ECX, X86::CX, 0)
151 ALIASLIST(A_DH , X86::EDX, X86::DX, 0)
152 ALIASLIST(A_BH , X86::EBX, X86::BX, 0)
155 // We are now done with the R* macros