1 //===- X86RegisterInfo.h - X86 Register Information Impl --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86REGISTERINFO_H
15 #define X86REGISTERINFO_H
17 #include "llvm/Target/TargetRegisterInfo.h"
18 #include "X86GenRegisterInfo.h.inc"
22 class TargetInstrInfo;
23 class X86TargetMachine;
25 /// N86 namespace - Native X86 register numbers
29 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
34 /// SubregIndex - The index of various sized subregister classes. Note that
35 /// these indices must be kept in sync with the class indices in the
36 /// X86RegisterInfo.td file.
38 SUBREG_8BIT = 1, SUBREG_8BIT_HI = 2, SUBREG_16BIT = 3, SUBREG_32BIT = 4,
39 SUBREG_SS = 1, SUBREG_SD = 2, SUBREG_XMM = 3
43 /// DWARFFlavour - Flavour of dwarf regnumbers
45 namespace DWARFFlavour {
47 X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2
51 class X86RegisterInfo : public X86GenRegisterInfo {
54 const TargetInstrInfo &TII;
57 /// Is64Bit - Is the target 64-bits.
61 /// IsWin64 - Is the target on of win64 flavours
65 /// SlotSize - Stack slot size in bytes.
69 /// StackAlign - Default stack alignment.
73 /// StackPtr - X86 physical register used as stack ptr.
77 /// FramePtr - X86 physical register used as frame ptr.
82 X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii);
84 /// getX86RegNum - Returns the native X86 register number for the given LLVM
85 /// register identifier.
86 static unsigned getX86RegNum(unsigned RegNo);
88 unsigned getStackAlignment() const { return StackAlign; }
90 /// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum
91 /// (created by TableGen) for target dependencies.
92 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
94 /// Code Generation virtual methods...
97 /// getMatchingSuperRegClass - Return a subclass of the specified register
98 /// class A so that each register in it has a sub-register of the
99 /// specified sub-register index which is in the specified register class B.
100 virtual const TargetRegisterClass *
101 getMatchingSuperRegClass(const TargetRegisterClass *A,
102 const TargetRegisterClass *B, unsigned Idx) const;
104 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
106 const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
108 /// getCrossCopyRegClass - Returns a legal register class to copy a register
109 /// in the specified class to or from. Returns NULL if it is possible to copy
110 /// between a two registers of the specified class.
111 const TargetRegisterClass *
112 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
114 /// getCalleeSavedRegs - Return a null-terminated list of all of the
115 /// callee-save registers on this target.
116 const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
118 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
119 /// register classes to spill each callee-saved register with. The order and
120 /// length of this list match the getCalleeSavedRegs() list.
121 const TargetRegisterClass* const*
122 getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
124 /// getReservedRegs - Returns a bitset indexed by physical register number
125 /// indicating if a register is a special register that has particular uses and
126 /// should be considered unavailable at all times, e.g. SP, RA. This is used by
127 /// register scavenger to determine what registers are free.
128 BitVector getReservedRegs(const MachineFunction &MF) const;
130 bool hasFP(const MachineFunction &MF) const;
132 bool canRealignStack(const MachineFunction &MF) const;
134 bool needsStackRealignment(const MachineFunction &MF) const;
136 bool hasReservedCallFrame(MachineFunction &MF) const;
138 bool hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
139 int &FrameIdx) const;
141 void eliminateCallFramePseudoInstr(MachineFunction &MF,
142 MachineBasicBlock &MBB,
143 MachineBasicBlock::iterator MI) const;
145 unsigned eliminateFrameIndex(MachineBasicBlock::iterator MI,
146 int SPAdj, int *Value = NULL,
147 RegScavenger *RS = NULL) const;
149 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
150 RegScavenger *RS = NULL) const;
152 void emitCalleeSavedFrameMoves(MachineFunction &MF, unsigned LabelId,
153 unsigned FramePtr) const;
154 void emitPrologue(MachineFunction &MF) const;
155 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
157 // Debug information queries.
158 unsigned getRARegister() const;
159 unsigned getFrameRegister(const MachineFunction &MF) const;
160 int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
161 void getInitialFrameState(std::vector<MachineMove> &Moves) const;
163 // Exception handling queries.
164 unsigned getEHExceptionRegister() const;
165 unsigned getEHHandlerRegister() const;
168 // getX86SubSuperRegister - X86 utility function. It returns the sub or super
169 // register of a specific X86 register.
170 // e.g. getX86SubSuperRegister(X86::EAX, EVT::i16) return X86:AX
171 unsigned getX86SubSuperRegister(unsigned, EVT, bool High=false);
173 } // End llvm namespace