1 //===- X86RegisterInfo.h - X86 Register Information Impl --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86REGISTERINFO_H
15 #define X86REGISTERINFO_H
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/Target/MRegisterInfo.h"
20 #include "X86GenRegisterInfo.h.inc"
24 class TargetInstrInfo;
25 class X86TargetMachine;
27 /// N86 namespace - Native X86 register numbers
31 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
35 /// DWARFFlavour - Flavour of dwarf regnumbers
37 namespace DWARFFlavour {
39 X86_64 = 0, X86_32_Darwin = 1, X86_32_ELF = 2
43 class X86RegisterInfo : public X86GenRegisterInfo {
46 const TargetInstrInfo &TII;
49 /// Is64Bit - Is the target 64-bits.
53 /// SlotSize - Stack slot size in bytes.
57 /// StackAlign - Default stack alignment.
61 /// StackPtr - X86 physical register used as stack ptr.
65 /// FramePtr - X86 physical register used as frame ptr.
69 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
70 /// RegOp2MemOpTable2 - Load / store folding opcode maps.
72 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2Addr;
73 DenseMap<unsigned*, unsigned> RegOp2MemOpTable0;
74 DenseMap<unsigned*, unsigned> RegOp2MemOpTable1;
75 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2;
77 /// MemOp2RegOpTable - Load / store unfolding opcode map.
79 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable;
82 X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii);
84 /// getX86RegNum - Returns the native X86 register number for the given LLVM
85 /// register identifier.
86 unsigned getX86RegNum(unsigned RegNo);
88 /// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum
89 /// (created by TableGen) for target dependencies.
90 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
92 /// Code Generation virtual methods...
94 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
95 MachineBasicBlock::iterator MI,
96 const std::vector<CalleeSavedInfo> &CSI) const;
98 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
99 MachineBasicBlock::iterator MI,
100 const std::vector<CalleeSavedInfo> &CSI) const;
102 void storeRegToStackSlot(MachineBasicBlock &MBB,
103 MachineBasicBlock::iterator MI,
104 unsigned SrcReg, bool isKill, int FrameIndex,
105 const TargetRegisterClass *RC) const;
107 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
108 SmallVectorImpl<MachineOperand> &Addr,
109 const TargetRegisterClass *RC,
110 SmallVectorImpl<MachineInstr*> &NewMIs) const;
112 void loadRegFromStackSlot(MachineBasicBlock &MBB,
113 MachineBasicBlock::iterator MI,
114 unsigned DestReg, int FrameIndex,
115 const TargetRegisterClass *RC) const;
117 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
118 SmallVectorImpl<MachineOperand> &Addr,
119 const TargetRegisterClass *RC,
120 SmallVectorImpl<MachineInstr*> &NewMIs) const;
122 void copyRegToReg(MachineBasicBlock &MBB,
123 MachineBasicBlock::iterator MI,
124 unsigned DestReg, unsigned SrcReg,
125 const TargetRegisterClass *DestRC,
126 const TargetRegisterClass *SrcRC) const;
128 const TargetRegisterClass *
129 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
131 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
132 unsigned DestReg, const MachineInstr *Orig) const;
134 /// foldMemoryOperand - If this target supports it, fold a load or store of
135 /// the specified stack slot into the specified machine instruction for the
136 /// specified operand(s). If this is possible, the target should perform the
137 /// folding and return true, otherwise it should return false. If it folds
138 /// the instruction, it is likely that the MachineInstruction the iterator
139 /// references has been changed.
140 MachineInstr* foldMemoryOperand(MachineInstr* MI,
141 SmallVectorImpl<unsigned> &Ops,
142 int FrameIndex) const;
144 /// foldMemoryOperand - Same as the previous version except it allows folding
145 /// of any load and store from / to any address, not just from a specific
147 MachineInstr* foldMemoryOperand(MachineInstr* MI,
148 SmallVectorImpl<unsigned> &Ops,
149 MachineInstr* LoadMI) const;
151 /// canFoldMemoryOperand - Returns true if the specified load / store is
152 /// folding is possible.
153 bool canFoldMemoryOperand(MachineInstr*, SmallVectorImpl<unsigned> &) const;
155 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
156 /// a store or a load and a store into two or more instruction. If this is
157 /// possible, returns true as well as the new instructions by reference.
158 bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
159 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
160 SmallVectorImpl<MachineInstr*> &NewMIs) const;
162 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
163 SmallVectorImpl<SDNode*> &NewNodes) const;
165 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
166 /// instruction after load / store are unfolded from an instruction of the
167 /// specified opcode. It returns zero if the specified unfolding is not
169 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
170 bool UnfoldLoad, bool UnfoldStore) const;
172 /// getCalleeSavedRegs - Return a null-terminated list of all of the
173 /// callee-save registers on this target.
174 const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
176 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
177 /// register classes to spill each callee-saved register with. The order and
178 /// length of this list match the getCalleeSavedRegs() list.
179 const TargetRegisterClass* const*
180 getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
182 /// getReservedRegs - Returns a bitset indexed by physical register number
183 /// indicating if a register is a special register that has particular uses and
184 /// should be considered unavailable at all times, e.g. SP, RA. This is used by
185 /// register scavenger to determine what registers are free.
186 BitVector getReservedRegs(const MachineFunction &MF) const;
188 bool hasFP(const MachineFunction &MF) const;
190 bool hasReservedCallFrame(MachineFunction &MF) const;
192 void eliminateCallFramePseudoInstr(MachineFunction &MF,
193 MachineBasicBlock &MBB,
194 MachineBasicBlock::iterator MI) const;
196 void eliminateFrameIndex(MachineBasicBlock::iterator MI,
197 int SPAdj, RegScavenger *RS = NULL) const;
199 void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
201 void emitPrologue(MachineFunction &MF) const;
202 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
204 // Debug information queries.
205 unsigned getRARegister() const;
206 unsigned getFrameRegister(MachineFunction &MF) const;
207 void getInitialFrameState(std::vector<MachineMove> &Moves) const;
209 // Exception handling queries.
210 unsigned getEHExceptionRegister() const;
211 unsigned getEHHandlerRegister() const;
214 MachineInstr* foldMemoryOperand(MachineInstr* MI,
216 SmallVector<MachineOperand,4> &MOs) const;
219 // getX86SubSuperRegister - X86 utility function. It returns the sub or super
220 // register of a specific X86 register.
221 // e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) return X86:AX
222 unsigned getX86SubSuperRegister(unsigned, MVT::ValueType, bool High=false);
224 } // End llvm namespace