1 //===- X86RegisterInfo.h - X86 Register Information Impl --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86REGISTERINFO_H
15 #define X86REGISTERINFO_H
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/Target/MRegisterInfo.h"
20 #include "X86GenRegisterInfo.h.inc"
24 class TargetInstrInfo;
25 class X86TargetMachine;
27 /// N86 namespace - Native X86 register numbers
31 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
35 class X86RegisterInfo : public X86GenRegisterInfo {
38 const TargetInstrInfo &TII;
41 /// Is64Bit - Is the target 64-bits.
45 /// SlotSize - Stack slot size in bytes.
49 /// StackAlign - Default stack alignment.
53 /// StackPtr - X86 physical register used as stack ptr.
57 /// FramePtr - X86 physical register used as frame ptr.
61 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
62 /// RegOp2MemOpTable2 - Load / store folding opcode maps.
64 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2Addr;
65 DenseMap<unsigned*, unsigned> RegOp2MemOpTable0;
66 DenseMap<unsigned*, unsigned> RegOp2MemOpTable1;
67 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2;
69 /// MemOp2RegOpTable - Load / store unfolding opcode map.
71 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable;
74 X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii);
76 /// getX86RegNum - Returns the native X86 register number for the given LLVM
77 /// register identifier.
78 unsigned getX86RegNum(unsigned RegNo);
80 /// Code Generation virtual methods...
82 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
83 MachineBasicBlock::iterator MI,
84 const std::vector<CalleeSavedInfo> &CSI) const;
86 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
87 MachineBasicBlock::iterator MI,
88 const std::vector<CalleeSavedInfo> &CSI) const;
90 void storeRegToStackSlot(MachineBasicBlock &MBB,
91 MachineBasicBlock::iterator MI,
92 unsigned SrcReg, int FrameIndex,
93 const TargetRegisterClass *RC) const;
95 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
96 SmallVectorImpl<MachineOperand> &Addr,
97 const TargetRegisterClass *RC,
98 SmallVectorImpl<MachineInstr*> &NewMIs) const;
100 void loadRegFromStackSlot(MachineBasicBlock &MBB,
101 MachineBasicBlock::iterator MI,
102 unsigned DestReg, int FrameIndex,
103 const TargetRegisterClass *RC) const;
105 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
106 SmallVectorImpl<MachineOperand> &Addr,
107 const TargetRegisterClass *RC,
108 SmallVectorImpl<MachineInstr*> &NewMIs) const;
110 void copyRegToReg(MachineBasicBlock &MBB,
111 MachineBasicBlock::iterator MI,
112 unsigned DestReg, unsigned SrcReg,
113 const TargetRegisterClass *DestRC,
114 const TargetRegisterClass *SrcRC) const;
116 const TargetRegisterClass *
117 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
119 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
120 unsigned DestReg, const MachineInstr *Orig) const;
122 /// foldMemoryOperand - If this target supports it, fold a load or store of
123 /// the specified stack slot into the specified machine instruction for the
124 /// specified operand. If this is possible, the target should perform the
125 /// folding and return true, otherwise it should return false. If it folds
126 /// the instruction, it is likely that the MachineInstruction the iterator
127 /// references has been changed.
128 MachineInstr* foldMemoryOperand(MachineInstr* MI,
130 int FrameIndex) const;
132 /// foldMemoryOperand - Same as the previous version except it allows folding
133 /// of any load and store from / to any address, not just from a specific
135 MachineInstr* foldMemoryOperand(MachineInstr* MI,
137 MachineInstr* LoadMI) const;
139 /// getOpcodeAfterMemoryFold - Returns the opcode of the would be new
140 /// instruction after load / store is folded into an instruction of the
141 /// specified opcode. It returns zero if the specified unfolding is not
143 unsigned getOpcodeAfterMemoryFold(unsigned Opc, unsigned OpNum) const;
145 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
146 /// a store or a load and a store into two or more instruction. If this is
147 /// possible, returns true as well as the new instructions by reference.
148 bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
149 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
150 SmallVectorImpl<MachineInstr*> &NewMIs) const;
152 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
153 SmallVectorImpl<SDNode*> &NewNodes) const;
155 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
156 /// instruction after load / store are unfolded from an instruction of the
157 /// specified opcode. It returns zero if the specified unfolding is not
159 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
160 bool UnfoldLoad, bool UnfoldStore) const;
162 /// getCalleeSavedRegs - Return a null-terminated list of all of the
163 /// callee-save registers on this target.
164 const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
166 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
167 /// register classes to spill each callee-saved register with. The order and
168 /// length of this list match the getCalleeSavedRegs() list.
169 const TargetRegisterClass* const*
170 getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
172 /// getReservedRegs - Returns a bitset indexed by physical register number
173 /// indicating if a register is a special register that has particular uses and
174 /// should be considered unavailable at all times, e.g. SP, RA. This is used by
175 /// register scavenger to determine what registers are free.
176 BitVector getReservedRegs(const MachineFunction &MF) const;
178 bool hasFP(const MachineFunction &MF) const;
180 bool hasReservedCallFrame(MachineFunction &MF) const;
182 void eliminateCallFramePseudoInstr(MachineFunction &MF,
183 MachineBasicBlock &MBB,
184 MachineBasicBlock::iterator MI) const;
186 void eliminateFrameIndex(MachineBasicBlock::iterator MI,
187 int SPAdj, RegScavenger *RS = NULL) const;
189 void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
191 void emitPrologue(MachineFunction &MF) const;
192 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
194 // Debug information queries.
195 unsigned getRARegister() const;
196 unsigned getFrameRegister(MachineFunction &MF) const;
197 void getInitialFrameState(std::vector<MachineMove> &Moves) const;
199 // Exception handling queries.
200 unsigned getEHExceptionRegister() const;
201 unsigned getEHHandlerRegister() const;
204 MachineInstr* foldMemoryOperand(MachineInstr* MI,
206 SmallVector<MachineOperand,4> &MOs) const;
209 // getX86SubSuperRegister - X86 utility function. It returns the sub or super
210 // register of a specific X86 register.
211 // e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) return X86:AX
212 unsigned getX86SubSuperRegister(unsigned, MVT::ValueType, bool High=false);
214 } // End llvm namespace