1 //===- X86RegisterInfo.td - Describe the X86 Register File ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 Register file, defining the registers themselves,
11 // aliases between the registers, and the register classes built out of the
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Register definitions...
19 let Namespace = "X86" in {
21 // In the register alias definitions below, we define which registers alias
22 // which others. We only specify which registers the small registers alias,
23 // because the register file generator is smart enough to figure out that
24 // AL aliases AX if we tell it that AX aliased AL (for example).
26 // FIXME: X86-64 have different Dwarf numbers.
29 def AL : Register<"AL">, DwarfRegNum<0>;
30 def CL : Register<"CL">, DwarfRegNum<1>;
31 def DL : Register<"DL">, DwarfRegNum<2>;
32 def BL : Register<"BL">, DwarfRegNum<3>;
35 def SIL : Register<"SIL">, DwarfRegNum<4>;
36 def DIL : Register<"DIL">, DwarfRegNum<5>;
37 def BPL : Register<"BPL">, DwarfRegNum<6>;
38 def SPL : Register<"SPL">, DwarfRegNum<7>;
39 def R8B : Register<"R8B">, DwarfRegNum<8>;
40 def R9B : Register<"R9B">, DwarfRegNum<9>;
41 def R10B : Register<"R10B">, DwarfRegNum<10>;
42 def R11B : Register<"R11B">, DwarfRegNum<11>;
43 def R12B : Register<"R12B">, DwarfRegNum<12>;
44 def R13B : Register<"R13B">, DwarfRegNum<13>;
45 def R14B : Register<"R14B">, DwarfRegNum<14>;
46 def R15B : Register<"R15B">, DwarfRegNum<15>;
48 // High registers X86-32 only
49 def AH : Register<"AH">, DwarfRegNum<0>;
50 def CH : Register<"CH">, DwarfRegNum<1>;
51 def DH : Register<"DH">, DwarfRegNum<2>;
52 def BH : Register<"BH">, DwarfRegNum<3>;
55 def AX : RegisterWithSubRegs<"AX", [AH,AL]>, DwarfRegNum<0>;
56 def CX : RegisterWithSubRegs<"CX", [CH,CL]>, DwarfRegNum<1>;
57 def DX : RegisterWithSubRegs<"DX", [DH,DL]>, DwarfRegNum<2>;
58 def BX : RegisterWithSubRegs<"BX", [BH,BL]>, DwarfRegNum<3>;
59 def SP : RegisterWithSubRegs<"SP", [SPL]>, DwarfRegNum<4>;
60 def BP : RegisterWithSubRegs<"BP", [BPL]>, DwarfRegNum<5>;
61 def SI : RegisterWithSubRegs<"SI", [SIL]>, DwarfRegNum<6>;
62 def DI : RegisterWithSubRegs<"DI", [DIL]>, DwarfRegNum<7>;
63 def IP : Register<"IP">, DwarfRegNum<8>;
66 def R8W : RegisterWithSubRegs<"R8W", [R8B]>, DwarfRegNum<8>;
67 def R9W : RegisterWithSubRegs<"R9W", [R9B]>, DwarfRegNum<9>;
68 def R10W : RegisterWithSubRegs<"R10W", [R10B]>, DwarfRegNum<10>;
69 def R11W : RegisterWithSubRegs<"R11W", [R11B]>, DwarfRegNum<11>;
70 def R12W : RegisterWithSubRegs<"R12W", [R12B]>, DwarfRegNum<12>;
71 def R13W : RegisterWithSubRegs<"R13W", [R13B]>, DwarfRegNum<13>;
72 def R14W : RegisterWithSubRegs<"R14W", [R14B]>, DwarfRegNum<14>;
73 def R15W : RegisterWithSubRegs<"R15W", [R15B]>, DwarfRegNum<15>;
76 def EAX : RegisterWithSubRegs<"EAX", [AX]>, DwarfRegNum<0>;
77 def ECX : RegisterWithSubRegs<"ECX", [CX]>, DwarfRegNum<1>;
78 def EDX : RegisterWithSubRegs<"EDX", [DX]>, DwarfRegNum<2>;
79 def EBX : RegisterWithSubRegs<"EBX", [BX]>, DwarfRegNum<3>;
80 def ESP : RegisterWithSubRegs<"ESP", [SP]>, DwarfRegNum<4>;
81 def EBP : RegisterWithSubRegs<"EBP", [BP]>, DwarfRegNum<5>;
82 def ESI : RegisterWithSubRegs<"ESI", [SI]>, DwarfRegNum<6>;
83 def EDI : RegisterWithSubRegs<"EDI", [DI]>, DwarfRegNum<7>;
84 def EIP : RegisterWithSubRegs<"EIP", [IP]>, DwarfRegNum<8>;
87 def R8D : RegisterWithSubRegs<"R8D", [R8W]>, DwarfRegNum<8>;
88 def R9D : RegisterWithSubRegs<"R9D", [R9W]>, DwarfRegNum<9>;
89 def R10D : RegisterWithSubRegs<"R10D", [R10W]>, DwarfRegNum<10>;
90 def R11D : RegisterWithSubRegs<"R11D", [R11W]>, DwarfRegNum<11>;
91 def R12D : RegisterWithSubRegs<"R12D", [R12W]>, DwarfRegNum<12>;
92 def R13D : RegisterWithSubRegs<"R13D", [R13W]>, DwarfRegNum<13>;
93 def R14D : RegisterWithSubRegs<"R14D", [R14W]>, DwarfRegNum<14>;
94 def R15D : RegisterWithSubRegs<"R15D", [R15W]>, DwarfRegNum<15>;
96 // 64-bit registers, X86-64 only
97 def RAX : RegisterWithSubRegs<"RAX", [EAX]>, DwarfRegNum<0>;
98 def RDX : RegisterWithSubRegs<"RDX", [EDX]>, DwarfRegNum<1>;
99 def RCX : RegisterWithSubRegs<"RCX", [ECX]>, DwarfRegNum<2>;
100 def RBX : RegisterWithSubRegs<"RBX", [EBX]>, DwarfRegNum<3>;
101 def RSI : RegisterWithSubRegs<"RSI", [ESI]>, DwarfRegNum<4>;
102 def RDI : RegisterWithSubRegs<"RDI", [EDI]>, DwarfRegNum<5>;
103 def RBP : RegisterWithSubRegs<"RBP", [EBP]>, DwarfRegNum<6>;
104 def RSP : RegisterWithSubRegs<"RSP", [ESP]>, DwarfRegNum<7>;
106 def R8 : RegisterWithSubRegs<"R8", [R8D]>, DwarfRegNum<8>;
107 def R9 : RegisterWithSubRegs<"R9", [R9D]>, DwarfRegNum<9>;
108 def R10 : RegisterWithSubRegs<"R10", [R10D]>, DwarfRegNum<10>;
109 def R11 : RegisterWithSubRegs<"R11", [R11D]>, DwarfRegNum<11>;
110 def R12 : RegisterWithSubRegs<"R12", [R12D]>, DwarfRegNum<12>;
111 def R13 : RegisterWithSubRegs<"R13", [R13D]>, DwarfRegNum<13>;
112 def R14 : RegisterWithSubRegs<"R14", [R14D]>, DwarfRegNum<14>;
113 def R15 : RegisterWithSubRegs<"R15", [R15D]>, DwarfRegNum<15>;
114 def RIP : RegisterWithSubRegs<"RIP", [EIP]>, DwarfRegNum<16>;
116 // MMX Registers. These are actually aliased to ST0 .. ST7
117 def MM0 : Register<"MM0">, DwarfRegNum<29>;
118 def MM1 : Register<"MM1">, DwarfRegNum<30>;
119 def MM2 : Register<"MM2">, DwarfRegNum<31>;
120 def MM3 : Register<"MM3">, DwarfRegNum<32>;
121 def MM4 : Register<"MM4">, DwarfRegNum<33>;
122 def MM5 : Register<"MM5">, DwarfRegNum<34>;
123 def MM6 : Register<"MM6">, DwarfRegNum<35>;
124 def MM7 : Register<"MM7">, DwarfRegNum<36>;
126 // Pseudo Floating Point registers
127 def FP0 : Register<"FP0">, DwarfRegNum<-1>;
128 def FP1 : Register<"FP1">, DwarfRegNum<-1>;
129 def FP2 : Register<"FP2">, DwarfRegNum<-1>;
130 def FP3 : Register<"FP3">, DwarfRegNum<-1>;
131 def FP4 : Register<"FP4">, DwarfRegNum<-1>;
132 def FP5 : Register<"FP5">, DwarfRegNum<-1>;
133 def FP6 : Register<"FP6">, DwarfRegNum<-1>;
135 // XMM Registers, used by the various SSE instruction set extensions
136 def XMM0: Register<"XMM0">, DwarfRegNum<17>;
137 def XMM1: Register<"XMM1">, DwarfRegNum<18>;
138 def XMM2: Register<"XMM2">, DwarfRegNum<19>;
139 def XMM3: Register<"XMM3">, DwarfRegNum<20>;
140 def XMM4: Register<"XMM4">, DwarfRegNum<21>;
141 def XMM5: Register<"XMM5">, DwarfRegNum<22>;
142 def XMM6: Register<"XMM6">, DwarfRegNum<23>;
143 def XMM7: Register<"XMM7">, DwarfRegNum<24>;
146 def XMM8: Register<"XMM8">, DwarfRegNum<25>;
147 def XMM9: Register<"XMM9">, DwarfRegNum<26>;
148 def XMM10: Register<"XMM10">, DwarfRegNum<27>;
149 def XMM11: Register<"XMM11">, DwarfRegNum<28>;
150 def XMM12: Register<"XMM12">, DwarfRegNum<29>;
151 def XMM13: Register<"XMM13">, DwarfRegNum<30>;
152 def XMM14: Register<"XMM14">, DwarfRegNum<31>;
153 def XMM15: Register<"XMM15">, DwarfRegNum<32>;
155 // Floating point stack registers
156 def ST0 : Register<"ST(0)">, DwarfRegNum<11>;
157 def ST1 : Register<"ST(1)">, DwarfRegNum<12>;
158 def ST2 : Register<"ST(2)">, DwarfRegNum<13>;
159 def ST3 : Register<"ST(3)">, DwarfRegNum<14>;
160 def ST4 : Register<"ST(4)">, DwarfRegNum<15>;
161 def ST5 : Register<"ST(5)">, DwarfRegNum<16>;
162 def ST6 : Register<"ST(6)">, DwarfRegNum<17>;
163 def ST7 : Register<"ST(7)">, DwarfRegNum<18>;
166 //===----------------------------------------------------------------------===//
167 // Register Class Definitions... now that we have all of the pieces, define the
168 // top-level register classes. The order specified in the register list is
169 // implicitly defined to be the register allocation order.
172 // List call-clobbered registers before callee-save registers. RBX, RBP, (and
173 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
174 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
176 // FIXME: Allow AH, CH, DH, BH in 64-mode for non-REX instructions,
177 def GR8 : RegisterClass<"X86", [i8], 8,
178 [AL, CL, DL, BL, AH, CH, DH, BH, SIL, DIL, BPL, SPL,
179 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]> {
180 let MethodProtos = [{
181 iterator allocation_order_begin(const MachineFunction &MF) const;
182 iterator allocation_order_end(const MachineFunction &MF) const;
184 let MethodBodies = [{
185 // Does the function dedicate RBP / EBP to being a frame ptr?
186 // If so, don't allocate SPL or BPL.
187 static const unsigned X86_GR8_AO_64_fp[] =
188 {X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
189 X86::R8B, X86::R9B, X86::R10B, X86::R11B,
190 X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B};
191 // If not, just don't allocate SPL.
192 static const unsigned X86_GR8_AO_64[] =
193 {X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
194 X86::R8B, X86::R9B, X86::R10B, X86::R11B,
195 X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL};
196 // In 32-mode, none of the 8-bit registers aliases EBP or ESP.
197 static const unsigned X86_GR8_AO_32[] =
198 {X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH};
201 GR8Class::allocation_order_begin(const MachineFunction &MF) const {
202 const TargetMachine &TM = MF.getTarget();
203 const MRegisterInfo *RI = TM.getRegisterInfo();
204 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
205 if (!Subtarget.is64Bit())
206 return X86_GR8_AO_32;
207 else if (RI->hasFP(MF))
208 return X86_GR8_AO_64_fp;
210 return X86_GR8_AO_64;
214 GR8Class::allocation_order_end(const MachineFunction &MF) const {
215 const TargetMachine &TM = MF.getTarget();
216 const MRegisterInfo *RI = TM.getRegisterInfo();
217 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
218 if (!Subtarget.is64Bit())
219 return X86_GR8_AO_32 + (sizeof(X86_GR8_AO_32) / sizeof(unsigned));
220 else if (RI->hasFP(MF))
221 return X86_GR8_AO_64_fp + (sizeof(X86_GR8_AO_64_fp) / sizeof(unsigned));
223 return X86_GR8_AO_64 + (sizeof(X86_GR8_AO_64) / sizeof(unsigned));
229 def GR16 : RegisterClass<"X86", [i16], 16,
230 [AX, CX, DX, SI, DI, BX, BP, SP,
231 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]> {
232 let MethodProtos = [{
233 iterator allocation_order_begin(const MachineFunction &MF) const;
234 iterator allocation_order_end(const MachineFunction &MF) const;
236 let MethodBodies = [{
237 // Does the function dedicate RBP / EBP to being a frame ptr?
238 // If so, don't allocate SP or BP.
239 static const unsigned X86_GR16_AO_64_fp[] =
240 {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
241 X86::R8W, X86::R9W, X86::R10W, X86::R11W,
242 X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W};
243 static const unsigned X86_GR16_AO_32_fp[] =
244 {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX};
245 // If not, just don't allocate SPL.
246 static const unsigned X86_GR16_AO_64[] =
247 {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
248 X86::R8W, X86::R9W, X86::R10W, X86::R11W,
249 X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::BP};
250 static const unsigned X86_GR16_AO_32[] =
251 {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP};
254 GR16Class::allocation_order_begin(const MachineFunction &MF) const {
255 const TargetMachine &TM = MF.getTarget();
256 const MRegisterInfo *RI = TM.getRegisterInfo();
257 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
258 if (Subtarget.is64Bit()) {
260 return X86_GR16_AO_64_fp;
262 return X86_GR16_AO_64;
265 return X86_GR16_AO_32_fp;
267 return X86_GR16_AO_32;
272 GR16Class::allocation_order_end(const MachineFunction &MF) const {
273 const TargetMachine &TM = MF.getTarget();
274 const MRegisterInfo *RI = TM.getRegisterInfo();
275 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
276 if (Subtarget.is64Bit()) {
278 return X86_GR16_AO_64_fp+(sizeof(X86_GR16_AO_64_fp)/sizeof(unsigned));
280 return X86_GR16_AO_64 + (sizeof(X86_GR16_AO_64) / sizeof(unsigned));
283 return X86_GR16_AO_32_fp+(sizeof(X86_GR16_AO_32_fp)/sizeof(unsigned));
285 return X86_GR16_AO_32 + (sizeof(X86_GR16_AO_32) / sizeof(unsigned));
292 def GR32 : RegisterClass<"X86", [i32], 32,
293 [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
294 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]> {
295 let MethodProtos = [{
296 iterator allocation_order_begin(const MachineFunction &MF) const;
297 iterator allocation_order_end(const MachineFunction &MF) const;
299 let MethodBodies = [{
300 // Does the function dedicate RBP / EBP to being a frame ptr?
301 // If so, don't allocate ESP or EBP.
302 static const unsigned X86_GR32_AO_64_fp[] =
303 {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
304 X86::R8D, X86::R9D, X86::R10D, X86::R11D,
305 X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D};
306 static const unsigned X86_GR32_AO_32_fp[] =
307 {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX};
308 // If not, just don't allocate SPL.
309 static const unsigned X86_GR32_AO_64[] =
310 {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
311 X86::R8D, X86::R9D, X86::R10D, X86::R11D,
312 X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP};
313 static const unsigned X86_GR32_AO_32[] =
314 {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP};
317 GR32Class::allocation_order_begin(const MachineFunction &MF) const {
318 const TargetMachine &TM = MF.getTarget();
319 const MRegisterInfo *RI = TM.getRegisterInfo();
320 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
321 if (Subtarget.is64Bit()) {
323 return X86_GR32_AO_64_fp;
325 return X86_GR32_AO_64;
328 return X86_GR32_AO_32_fp;
330 return X86_GR32_AO_32;
335 GR32Class::allocation_order_end(const MachineFunction &MF) const {
336 const TargetMachine &TM = MF.getTarget();
337 const MRegisterInfo *RI = TM.getRegisterInfo();
338 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
339 if (Subtarget.is64Bit()) {
341 return X86_GR32_AO_64_fp+(sizeof(X86_GR32_AO_64_fp)/sizeof(unsigned));
343 return X86_GR32_AO_64 + (sizeof(X86_GR32_AO_64) / sizeof(unsigned));
346 return X86_GR32_AO_32_fp+(sizeof(X86_GR32_AO_32_fp)/sizeof(unsigned));
348 return X86_GR32_AO_32 + (sizeof(X86_GR32_AO_32) / sizeof(unsigned));
355 def GR64 : RegisterClass<"X86", [i64], 64,
356 [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
357 RBX, R14, R15, R12, R13, RBP, RSP]> {
358 let MethodProtos = [{
359 iterator allocation_order_end(const MachineFunction &MF) const;
361 let MethodBodies = [{
363 GR64Class::allocation_order_end(const MachineFunction &MF) const {
364 const TargetMachine &TM = MF.getTarget();
365 const MRegisterInfo *RI = TM.getRegisterInfo();
366 if (RI->hasFP(MF)) // Does the function dedicate RBP to being a frame ptr?
367 return end()-2; // If so, don't allocate RSP or RBP
369 return end()-1; // If not, just don't allocate RSP
375 // GR16, GR32 subclasses which contain registers that have R8 sub-registers.
376 // These should only be used for 32-bit mode.
377 def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]>;
378 def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]>;
380 // Scalar SSE2 floating point registers.
381 def FR32 : RegisterClass<"X86", [f32], 32,
382 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
383 XMM8, XMM9, XMM10, XMM11,
384 XMM12, XMM13, XMM14, XMM15]> {
385 let MethodProtos = [{
386 iterator allocation_order_end(const MachineFunction &MF) const;
388 let MethodBodies = [{
390 FR32Class::allocation_order_end(const MachineFunction &MF) const {
391 const TargetMachine &TM = MF.getTarget();
392 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
393 if (!Subtarget.is64Bit())
394 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
401 def FR64 : RegisterClass<"X86", [f64], 64,
402 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
403 XMM8, XMM9, XMM10, XMM11,
404 XMM12, XMM13, XMM14, XMM15]> {
405 let MethodProtos = [{
406 iterator allocation_order_end(const MachineFunction &MF) const;
408 let MethodBodies = [{
410 FR64Class::allocation_order_end(const MachineFunction &MF) const {
411 const TargetMachine &TM = MF.getTarget();
412 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
413 if (!Subtarget.is64Bit())
414 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
422 // FIXME: This sets up the floating point register files as though they are f64
423 // values, though they really are f80 values. This will cause us to spill
424 // values as 64-bit quantities instead of 80-bit quantities, which is much much
425 // faster on common hardware. In reality, this should be controlled by a
426 // command line option or something.
428 def RFP : RegisterClass<"X86", [f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
430 // Floating point stack registers (these are not allocatable by the
431 // register allocator - the floating point stackifier is responsible
432 // for transforming FPn allocations to STn registers)
433 def RST : RegisterClass<"X86", [f64], 32,
434 [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
435 let MethodProtos = [{
436 iterator allocation_order_end(const MachineFunction &MF) const;
438 let MethodBodies = [{
440 RSTClass::allocation_order_end(const MachineFunction &MF) const {
446 // Generic vector registers: VR64 and VR128.
447 def VR64 : RegisterClass<"X86", [v8i8, v4i16, v2i32, v1i64], 64,
448 [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
449 def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128,
450 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
451 XMM8, XMM9, XMM10, XMM11,
452 XMM12, XMM13, XMM14, XMM15]> {
453 let MethodProtos = [{
454 iterator allocation_order_end(const MachineFunction &MF) const;
456 let MethodBodies = [{
458 VR128Class::allocation_order_end(const MachineFunction &MF) const {
459 const TargetMachine &TM = MF.getTarget();
460 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
461 if (!Subtarget.is64Bit())
462 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.