1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 Register file, defining the registers themselves,
11 // aliases between the registers, and the register classes built out of the
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Register definitions...
19 let Namespace = "X86" in {
21 // In the register alias definitions below, we define which registers alias
22 // which others. We only specify which registers the small registers alias,
23 // because the register file generator is smart enough to figure out that
24 // AL aliases AX if we tell it that AX aliased AL (for example).
26 // Dwarf numbering is different for 32-bit and 64-bit, and there are
27 // variations by target as well. Currently the first entry is for X86-64,
28 // second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux
29 // and debug information on X86-32/Darwin)
33 def AL : Register<"al">, DwarfRegNum<[0, 0, 0]>;
34 def DL : Register<"dl">, DwarfRegNum<[1, 2, 2]>;
35 def CL : Register<"cl">, DwarfRegNum<[2, 1, 1]>;
36 def BL : Register<"bl">, DwarfRegNum<[3, 3, 3]>;
39 def SIL : Register<"sil">, DwarfRegNum<[4, 6, 6]>;
40 def DIL : Register<"dil">, DwarfRegNum<[5, 7, 7]>;
41 def BPL : Register<"bpl">, DwarfRegNum<[6, 4, 5]>;
42 def SPL : Register<"spl">, DwarfRegNum<[7, 5, 4]>;
43 def R8B : Register<"r8b">, DwarfRegNum<[8, -2, -2]>;
44 def R9B : Register<"r9b">, DwarfRegNum<[9, -2, -2]>;
45 def R10B : Register<"r10b">, DwarfRegNum<[10, -2, -2]>;
46 def R11B : Register<"r11b">, DwarfRegNum<[11, -2, -2]>;
47 def R12B : Register<"r12b">, DwarfRegNum<[12, -2, -2]>;
48 def R13B : Register<"r13b">, DwarfRegNum<[13, -2, -2]>;
49 def R14B : Register<"r14b">, DwarfRegNum<[14, -2, -2]>;
50 def R15B : Register<"r15b">, DwarfRegNum<[15, -2, -2]>;
52 // High registers. On x86-64, these cannot be used in any instruction
54 def AH : Register<"ah">, DwarfRegNum<[0, 0, 0]>;
55 def DH : Register<"dh">, DwarfRegNum<[1, 2, 2]>;
56 def CH : Register<"ch">, DwarfRegNum<[2, 1, 1]>;
57 def BH : Register<"bh">, DwarfRegNum<[3, 3, 3]>;
60 def AX : RegisterWithSubRegs<"ax", [AL,AH]>, DwarfRegNum<[0, 0, 0]>;
61 def DX : RegisterWithSubRegs<"dx", [DL,DH]>, DwarfRegNum<[1, 2, 2]>;
62 def CX : RegisterWithSubRegs<"cx", [CL,CH]>, DwarfRegNum<[2, 1, 1]>;
63 def BX : RegisterWithSubRegs<"bx", [BL,BH]>, DwarfRegNum<[3, 3, 3]>;
64 def SI : RegisterWithSubRegs<"si", [SIL]>, DwarfRegNum<[4, 6, 6]>;
65 def DI : RegisterWithSubRegs<"di", [DIL]>, DwarfRegNum<[5, 7, 7]>;
66 def BP : RegisterWithSubRegs<"bp", [BPL]>, DwarfRegNum<[6, 4, 5]>;
67 def SP : RegisterWithSubRegs<"sp", [SPL]>, DwarfRegNum<[7, 5, 4]>;
68 def IP : Register<"ip">, DwarfRegNum<[16]>;
71 def R8W : RegisterWithSubRegs<"r8w", [R8B]>, DwarfRegNum<[8, -2, -2]>;
72 def R9W : RegisterWithSubRegs<"r9w", [R9B]>, DwarfRegNum<[9, -2, -2]>;
73 def R10W : RegisterWithSubRegs<"r10w", [R10B]>, DwarfRegNum<[10, -2, -2]>;
74 def R11W : RegisterWithSubRegs<"r11w", [R11B]>, DwarfRegNum<[11, -2, -2]>;
75 def R12W : RegisterWithSubRegs<"r12w", [R12B]>, DwarfRegNum<[12, -2, -2]>;
76 def R13W : RegisterWithSubRegs<"r13w", [R13B]>, DwarfRegNum<[13, -2, -2]>;
77 def R14W : RegisterWithSubRegs<"r14w", [R14B]>, DwarfRegNum<[14, -2, -2]>;
78 def R15W : RegisterWithSubRegs<"r15w", [R15B]>, DwarfRegNum<[15, -2, -2]>;
81 def EAX : RegisterWithSubRegs<"eax", [AX]>, DwarfRegNum<[0, 0, 0]>;
82 def EDX : RegisterWithSubRegs<"edx", [DX]>, DwarfRegNum<[1, 2, 2]>;
83 def ECX : RegisterWithSubRegs<"ecx", [CX]>, DwarfRegNum<[2, 1, 1]>;
84 def EBX : RegisterWithSubRegs<"ebx", [BX]>, DwarfRegNum<[3, 3, 3]>;
85 def ESI : RegisterWithSubRegs<"esi", [SI]>, DwarfRegNum<[4, 6, 6]>;
86 def EDI : RegisterWithSubRegs<"edi", [DI]>, DwarfRegNum<[5, 7, 7]>;
87 def EBP : RegisterWithSubRegs<"ebp", [BP]>, DwarfRegNum<[6, 4, 5]>;
88 def ESP : RegisterWithSubRegs<"esp", [SP]>, DwarfRegNum<[7, 5, 4]>;
89 def EIP : RegisterWithSubRegs<"eip", [IP]>, DwarfRegNum<[16, 8, 8]>;
92 def R8D : RegisterWithSubRegs<"r8d", [R8W]>, DwarfRegNum<[8, -2, -2]>;
93 def R9D : RegisterWithSubRegs<"r9d", [R9W]>, DwarfRegNum<[9, -2, -2]>;
94 def R10D : RegisterWithSubRegs<"r10d", [R10W]>, DwarfRegNum<[10, -2, -2]>;
95 def R11D : RegisterWithSubRegs<"r11d", [R11W]>, DwarfRegNum<[11, -2, -2]>;
96 def R12D : RegisterWithSubRegs<"r12d", [R12W]>, DwarfRegNum<[12, -2, -2]>;
97 def R13D : RegisterWithSubRegs<"r13d", [R13W]>, DwarfRegNum<[13, -2, -2]>;
98 def R14D : RegisterWithSubRegs<"r14d", [R14W]>, DwarfRegNum<[14, -2, -2]>;
99 def R15D : RegisterWithSubRegs<"r15d", [R15W]>, DwarfRegNum<[15, -2, -2]>;
101 // 64-bit registers, X86-64 only
102 def RAX : RegisterWithSubRegs<"rax", [EAX]>, DwarfRegNum<[0, -2, -2]>;
103 def RDX : RegisterWithSubRegs<"rdx", [EDX]>, DwarfRegNum<[1, -2, -2]>;
104 def RCX : RegisterWithSubRegs<"rcx", [ECX]>, DwarfRegNum<[2, -2, -2]>;
105 def RBX : RegisterWithSubRegs<"rbx", [EBX]>, DwarfRegNum<[3, -2, -2]>;
106 def RSI : RegisterWithSubRegs<"rsi", [ESI]>, DwarfRegNum<[4, -2, -2]>;
107 def RDI : RegisterWithSubRegs<"rdi", [EDI]>, DwarfRegNum<[5, -2, -2]>;
108 def RBP : RegisterWithSubRegs<"rbp", [EBP]>, DwarfRegNum<[6, -2, -2]>;
109 def RSP : RegisterWithSubRegs<"rsp", [ESP]>, DwarfRegNum<[7, -2, -2]>;
111 def R8 : RegisterWithSubRegs<"r8", [R8D]>, DwarfRegNum<[8, -2, -2]>;
112 def R9 : RegisterWithSubRegs<"r9", [R9D]>, DwarfRegNum<[9, -2, -2]>;
113 def R10 : RegisterWithSubRegs<"r10", [R10D]>, DwarfRegNum<[10, -2, -2]>;
114 def R11 : RegisterWithSubRegs<"r11", [R11D]>, DwarfRegNum<[11, -2, -2]>;
115 def R12 : RegisterWithSubRegs<"r12", [R12D]>, DwarfRegNum<[12, -2, -2]>;
116 def R13 : RegisterWithSubRegs<"r13", [R13D]>, DwarfRegNum<[13, -2, -2]>;
117 def R14 : RegisterWithSubRegs<"r14", [R14D]>, DwarfRegNum<[14, -2, -2]>;
118 def R15 : RegisterWithSubRegs<"r15", [R15D]>, DwarfRegNum<[15, -2, -2]>;
119 def RIP : RegisterWithSubRegs<"rip", [EIP]>, DwarfRegNum<[16, -2, -2]>;
121 // MMX Registers. These are actually aliased to ST0 .. ST7
122 def MM0 : Register<"mm0">, DwarfRegNum<[41, 29, 29]>;
123 def MM1 : Register<"mm1">, DwarfRegNum<[42, 30, 30]>;
124 def MM2 : Register<"mm2">, DwarfRegNum<[43, 31, 31]>;
125 def MM3 : Register<"mm3">, DwarfRegNum<[44, 32, 32]>;
126 def MM4 : Register<"mm4">, DwarfRegNum<[45, 33, 33]>;
127 def MM5 : Register<"mm5">, DwarfRegNum<[46, 34, 34]>;
128 def MM6 : Register<"mm6">, DwarfRegNum<[47, 35, 35]>;
129 def MM7 : Register<"mm7">, DwarfRegNum<[48, 36, 36]>;
131 // Pseudo Floating Point registers
132 def FP0 : Register<"fp0">;
133 def FP1 : Register<"fp1">;
134 def FP2 : Register<"fp2">;
135 def FP3 : Register<"fp3">;
136 def FP4 : Register<"fp4">;
137 def FP5 : Register<"fp5">;
138 def FP6 : Register<"fp6">;
140 // XMM Registers, used by the various SSE instruction set extensions
141 def XMM0: Register<"xmm0">, DwarfRegNum<[17, 21, 21]>;
142 def XMM1: Register<"xmm1">, DwarfRegNum<[18, 22, 22]>;
143 def XMM2: Register<"xmm2">, DwarfRegNum<[19, 23, 23]>;
144 def XMM3: Register<"xmm3">, DwarfRegNum<[20, 24, 24]>;
145 def XMM4: Register<"xmm4">, DwarfRegNum<[21, 25, 25]>;
146 def XMM5: Register<"xmm5">, DwarfRegNum<[22, 26, 26]>;
147 def XMM6: Register<"xmm6">, DwarfRegNum<[23, 27, 27]>;
148 def XMM7: Register<"xmm7">, DwarfRegNum<[24, 28, 28]>;
151 def XMM8: Register<"xmm8">, DwarfRegNum<[25, -2, -2]>;
152 def XMM9: Register<"xmm9">, DwarfRegNum<[26, -2, -2]>;
153 def XMM10: Register<"xmm10">, DwarfRegNum<[27, -2, -2]>;
154 def XMM11: Register<"xmm11">, DwarfRegNum<[28, -2, -2]>;
155 def XMM12: Register<"xmm12">, DwarfRegNum<[29, -2, -2]>;
156 def XMM13: Register<"xmm13">, DwarfRegNum<[30, -2, -2]>;
157 def XMM14: Register<"xmm14">, DwarfRegNum<[31, -2, -2]>;
158 def XMM15: Register<"xmm15">, DwarfRegNum<[32, -2, -2]>;
160 // YMM Registers, used by AVX instructions
161 def YMM0: Register<"ymm0">, DwarfRegNum<[17, 21, 21]>;
162 def YMM1: Register<"ymm1">, DwarfRegNum<[18, 22, 22]>;
163 def YMM2: Register<"ymm2">, DwarfRegNum<[19, 23, 23]>;
164 def YMM3: Register<"ymm3">, DwarfRegNum<[20, 24, 24]>;
165 def YMM4: Register<"ymm4">, DwarfRegNum<[21, 25, 25]>;
166 def YMM5: Register<"ymm5">, DwarfRegNum<[22, 26, 26]>;
167 def YMM6: Register<"ymm6">, DwarfRegNum<[23, 27, 27]>;
168 def YMM7: Register<"ymm7">, DwarfRegNum<[24, 28, 28]>;
169 def YMM8: Register<"ymm8">, DwarfRegNum<[25, -2, -2]>;
170 def YMM9: Register<"ymm9">, DwarfRegNum<[26, -2, -2]>;
171 def YMM10: Register<"ymm10">, DwarfRegNum<[27, -2, -2]>;
172 def YMM11: Register<"ymm11">, DwarfRegNum<[28, -2, -2]>;
173 def YMM12: Register<"ymm12">, DwarfRegNum<[29, -2, -2]>;
174 def YMM13: Register<"ymm13">, DwarfRegNum<[30, -2, -2]>;
175 def YMM14: Register<"ymm14">, DwarfRegNum<[31, -2, -2]>;
176 def YMM15: Register<"ymm15">, DwarfRegNum<[32, -2, -2]>;
178 // Floating point stack registers
179 def ST0 : Register<"st(0)">, DwarfRegNum<[33, 12, 11]>;
180 def ST1 : Register<"st(1)">, DwarfRegNum<[34, 13, 12]>;
181 def ST2 : Register<"st(2)">, DwarfRegNum<[35, 14, 13]>;
182 def ST3 : Register<"st(3)">, DwarfRegNum<[36, 15, 14]>;
183 def ST4 : Register<"st(4)">, DwarfRegNum<[37, 16, 15]>;
184 def ST5 : Register<"st(5)">, DwarfRegNum<[38, 17, 16]>;
185 def ST6 : Register<"st(6)">, DwarfRegNum<[39, 18, 17]>;
186 def ST7 : Register<"st(7)">, DwarfRegNum<[40, 19, 18]>;
188 // Status flags register
189 def EFLAGS : Register<"flags">;
192 def CS : Register<"cs">;
193 def DS : Register<"ds">;
194 def SS : Register<"ss">;
195 def ES : Register<"es">;
196 def FS : Register<"fs">;
197 def GS : Register<"gs">;
200 def DR0 : Register<"dr0">;
201 def DR1 : Register<"dr1">;
202 def DR2 : Register<"dr2">;
203 def DR3 : Register<"dr3">;
204 def DR4 : Register<"dr4">;
205 def DR5 : Register<"dr5">;
206 def DR6 : Register<"dr6">;
207 def DR7 : Register<"dr7">;
209 // Condition registers
210 def ECR0 : Register<"ecr0">;
211 def ECR1 : Register<"ecr1">;
212 def ECR2 : Register<"ecr2">;
213 def ECR3 : Register<"ecr3">;
214 def ECR4 : Register<"ecr4">;
215 def ECR5 : Register<"ecr5">;
216 def ECR6 : Register<"ecr6">;
217 def ECR7 : Register<"ecr7">;
219 def RCR0 : Register<"rcr0">;
220 def RCR1 : Register<"rcr1">;
221 def RCR2 : Register<"rcr2">;
222 def RCR3 : Register<"rcr3">;
223 def RCR4 : Register<"rcr4">;
224 def RCR5 : Register<"rcr5">;
225 def RCR6 : Register<"rcr6">;
226 def RCR7 : Register<"rcr7">;
227 def RCR8 : Register<"rcr8">;
231 //===----------------------------------------------------------------------===//
232 // Subregister Set Definitions... now that we have all of the pieces, define the
233 // sub registers for each register.
236 def x86_subreg_8bit : PatLeaf<(i32 1)>;
237 def x86_subreg_8bit_hi : PatLeaf<(i32 2)>;
238 def x86_subreg_16bit : PatLeaf<(i32 3)>;
239 def x86_subreg_32bit : PatLeaf<(i32 4)>;
241 def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
242 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
243 [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
244 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
246 def : SubRegSet<2, [AX, CX, DX, BX],
249 def : SubRegSet<1, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
250 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
251 [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
252 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
254 def : SubRegSet<2, [EAX, ECX, EDX, EBX],
257 def : SubRegSet<3, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
258 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
259 [AX, CX, DX, BX, SP, BP, SI, DI,
260 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
262 def : SubRegSet<1, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
263 R8, R9, R10, R11, R12, R13, R14, R15],
264 [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
265 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
267 def : SubRegSet<2, [RAX, RCX, RDX, RBX],
270 def : SubRegSet<3, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
271 R8, R9, R10, R11, R12, R13, R14, R15],
272 [AX, CX, DX, BX, SP, BP, SI, DI,
273 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
275 def : SubRegSet<4, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
276 R8, R9, R10, R11, R12, R13, R14, R15],
277 [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
278 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]>;
280 def : SubRegSet<1, [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
281 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15],
282 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
283 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
285 //===----------------------------------------------------------------------===//
286 // Register Class Definitions... now that we have all of the pieces, define the
287 // top-level register classes. The order specified in the register list is
288 // implicitly defined to be the register allocation order.
291 // List call-clobbered registers before callee-save registers. RBX, RBP, (and
292 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
293 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
295 // Allocate R12 and R13 last, as these require an extra byte when
296 // encoded in x86_64 instructions.
297 // FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in
298 // 64-bit mode. The main complication is that they cannot be encoded in an
299 // instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc.
300 // require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d"
301 // cannot be encoded.
302 def GR8 : RegisterClass<"X86", [i8], 8,
303 [AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
304 R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B]> {
305 let MethodProtos = [{
306 iterator allocation_order_begin(const MachineFunction &MF) const;
307 iterator allocation_order_end(const MachineFunction &MF) const;
309 let MethodBodies = [{
310 static const unsigned X86_GR8_AO_64[] = {
311 X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
312 X86::R8B, X86::R9B, X86::R10B, X86::R11B,
313 X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL
317 GR8Class::allocation_order_begin(const MachineFunction &MF) const {
318 const TargetMachine &TM = MF.getTarget();
319 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
320 if (Subtarget.is64Bit())
321 return X86_GR8_AO_64;
327 GR8Class::allocation_order_end(const MachineFunction &MF) const {
328 const TargetMachine &TM = MF.getTarget();
329 const TargetRegisterInfo *RI = TM.getRegisterInfo();
330 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
331 // Does the function dedicate RBP / EBP to being a frame ptr?
332 if (!Subtarget.is64Bit())
333 // In 32-mode, none of the 8-bit registers aliases EBP or ESP.
335 else if (RI->hasFP(MF))
336 // If so, don't allocate SPL or BPL.
337 return array_endof(X86_GR8_AO_64) - 1;
339 // If not, just don't allocate SPL.
340 return array_endof(X86_GR8_AO_64);
345 def GR16 : RegisterClass<"X86", [i16], 16,
346 [AX, CX, DX, SI, DI, BX, BP, SP,
347 R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W]> {
348 let SubRegClassList = [GR8, GR8];
349 let MethodProtos = [{
350 iterator allocation_order_begin(const MachineFunction &MF) const;
351 iterator allocation_order_end(const MachineFunction &MF) const;
353 let MethodBodies = [{
354 static const unsigned X86_GR16_AO_64[] = {
355 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
356 X86::R8W, X86::R9W, X86::R10W, X86::R11W,
357 X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::BP
361 GR16Class::allocation_order_begin(const MachineFunction &MF) const {
362 const TargetMachine &TM = MF.getTarget();
363 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
364 if (Subtarget.is64Bit())
365 return X86_GR16_AO_64;
371 GR16Class::allocation_order_end(const MachineFunction &MF) const {
372 const TargetMachine &TM = MF.getTarget();
373 const TargetRegisterInfo *RI = TM.getRegisterInfo();
374 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
375 if (Subtarget.is64Bit()) {
376 // Does the function dedicate RBP to being a frame ptr?
378 // If so, don't allocate SP or BP.
379 return array_endof(X86_GR16_AO_64) - 1;
381 // If not, just don't allocate SP.
382 return array_endof(X86_GR16_AO_64);
384 // Does the function dedicate EBP to being a frame ptr?
386 // If so, don't allocate SP or BP.
389 // If not, just don't allocate SP.
396 def GR32 : RegisterClass<"X86", [i32], 32,
397 [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
398 R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> {
399 let SubRegClassList = [GR8, GR8, GR16];
400 let MethodProtos = [{
401 iterator allocation_order_begin(const MachineFunction &MF) const;
402 iterator allocation_order_end(const MachineFunction &MF) const;
404 let MethodBodies = [{
405 static const unsigned X86_GR32_AO_64[] = {
406 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
407 X86::R8D, X86::R9D, X86::R10D, X86::R11D,
408 X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP
412 GR32Class::allocation_order_begin(const MachineFunction &MF) const {
413 const TargetMachine &TM = MF.getTarget();
414 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
415 if (Subtarget.is64Bit())
416 return X86_GR32_AO_64;
422 GR32Class::allocation_order_end(const MachineFunction &MF) const {
423 const TargetMachine &TM = MF.getTarget();
424 const TargetRegisterInfo *RI = TM.getRegisterInfo();
425 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
426 if (Subtarget.is64Bit()) {
427 // Does the function dedicate RBP to being a frame ptr?
429 // If so, don't allocate ESP or EBP.
430 return array_endof(X86_GR32_AO_64) - 1;
432 // If not, just don't allocate ESP.
433 return array_endof(X86_GR32_AO_64);
435 // Does the function dedicate EBP to being a frame ptr?
437 // If so, don't allocate ESP or EBP.
440 // If not, just don't allocate ESP.
447 // GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
448 // RIP isn't really a register and it can't be used anywhere except in an
449 // address, but it doesn't cause trouble.
450 def GR64 : RegisterClass<"X86", [i64], 64,
451 [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
452 RBX, R14, R15, R12, R13, RBP, RSP, RIP]> {
453 let SubRegClassList = [GR8, GR8, GR16, GR32];
454 let MethodProtos = [{
455 iterator allocation_order_end(const MachineFunction &MF) const;
457 let MethodBodies = [{
459 GR64Class::allocation_order_end(const MachineFunction &MF) const {
460 const TargetMachine &TM = MF.getTarget();
461 const TargetRegisterInfo *RI = TM.getRegisterInfo();
462 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
463 if (!Subtarget.is64Bit())
464 return begin(); // None of these are allocatable in 32-bit.
465 if (RI->hasFP(MF)) // Does the function dedicate RBP to being a frame ptr?
466 return end()-3; // If so, don't allocate RIP, RSP or RBP
468 return end()-2; // If not, just don't allocate RIP or RSP
473 // Segment registers for use by MOV instructions (and others) that have a
474 // segment register as one operand. Always contain a 16-bit segment
476 def SEGMENT_REG : RegisterClass<"X86", [i16], 16, [CS, DS, SS, ES, FS, GS]> {
480 def DEBUG_REG : RegisterClass<"X86", [i32], 32,
481 [DR0, DR1, DR2, DR3, DR4, DR5, DR6, DR7]> {
484 // Control registers.
485 def CONTROL_REG_32 : RegisterClass<"X86", [i32], 32,
486 [ECR0, ECR1, ECR2, ECR3, ECR4, ECR5, ECR6,
490 def CONTROL_REG_64 : RegisterClass<"X86", [i64], 64,
491 [RCR0, RCR1, RCR2, RCR3, RCR4, RCR5, RCR6,
495 // GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of
496 // GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d"
497 // registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers
498 // that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD,
499 // and GR64_ABCD are classes for registers that support 8-bit h-register
501 def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL]> {
503 def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, [AH, CH, DH, BH]> {
505 def GR16_ABCD : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
506 let SubRegClassList = [GR8_ABCD_L, GR8_ABCD_H];
508 def GR32_ABCD : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
509 let SubRegClassList = [GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD];
511 def GR64_ABCD : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RBX]> {
512 let SubRegClassList = [GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD];
515 // GR8_NOREX - GR8 registers which do not require a REX prefix.
516 def GR8_NOREX : RegisterClass<"X86", [i8], 8,
517 [AL, CL, DL, AH, CH, DH, BL, BH]> {
518 let MethodProtos = [{
519 iterator allocation_order_begin(const MachineFunction &MF) const;
520 iterator allocation_order_end(const MachineFunction &MF) const;
522 let MethodBodies = [{
523 // In 64-bit mode, it's not safe to blindly allocate H registers.
524 static const unsigned X86_GR8_NOREX_AO_64[] = {
525 X86::AL, X86::CL, X86::DL, X86::BL
528 GR8_NOREXClass::iterator
529 GR8_NOREXClass::allocation_order_begin(const MachineFunction &MF) const {
530 const TargetMachine &TM = MF.getTarget();
531 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
532 if (Subtarget.is64Bit())
533 return X86_GR8_NOREX_AO_64;
538 GR8_NOREXClass::iterator
539 GR8_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
540 const TargetMachine &TM = MF.getTarget();
541 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
542 if (Subtarget.is64Bit())
543 return array_endof(X86_GR8_NOREX_AO_64);
549 // GR16_NOREX - GR16 registers which do not require a REX prefix.
550 def GR16_NOREX : RegisterClass<"X86", [i16], 16,
551 [AX, CX, DX, SI, DI, BX, BP, SP]> {
552 let SubRegClassList = [GR8_NOREX, GR8_NOREX];
553 let MethodProtos = [{
554 iterator allocation_order_end(const MachineFunction &MF) const;
556 let MethodBodies = [{
557 GR16_NOREXClass::iterator
558 GR16_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
559 const TargetMachine &TM = MF.getTarget();
560 const TargetRegisterInfo *RI = TM.getRegisterInfo();
561 // Does the function dedicate RBP / EBP to being a frame ptr?
563 // If so, don't allocate SP or BP.
566 // If not, just don't allocate SP.
571 // GR32_NOREX - GR32 registers which do not require a REX prefix.
572 def GR32_NOREX : RegisterClass<"X86", [i32], 32,
573 [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
574 let SubRegClassList = [GR8_NOREX, GR8_NOREX, GR16_NOREX];
575 let MethodProtos = [{
576 iterator allocation_order_end(const MachineFunction &MF) const;
578 let MethodBodies = [{
579 GR32_NOREXClass::iterator
580 GR32_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
581 const TargetMachine &TM = MF.getTarget();
582 const TargetRegisterInfo *RI = TM.getRegisterInfo();
583 // Does the function dedicate RBP / EBP to being a frame ptr?
585 // If so, don't allocate ESP or EBP.
588 // If not, just don't allocate ESP.
593 // GR64_NOREX - GR64 registers which do not require a REX prefix.
594 def GR64_NOREX : RegisterClass<"X86", [i64], 64,
595 [RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP]> {
596 let SubRegClassList = [GR8_NOREX, GR8_NOREX, GR16_NOREX, GR32_NOREX];
597 let MethodProtos = [{
598 iterator allocation_order_end(const MachineFunction &MF) const;
600 let MethodBodies = [{
601 GR64_NOREXClass::iterator
602 GR64_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
603 const TargetMachine &TM = MF.getTarget();
604 const TargetRegisterInfo *RI = TM.getRegisterInfo();
605 // Does the function dedicate RBP to being a frame ptr?
607 // If so, don't allocate RIP, RSP or RBP.
610 // If not, just don't allocate RIP or RSP.
616 // GR32_NOSP - GR32 registers except ESP.
617 def GR32_NOSP : RegisterClass<"X86", [i32], 32,
618 [EAX, ECX, EDX, ESI, EDI, EBX, EBP,
619 R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> {
620 let SubRegClassList = [GR8, GR8, GR16];
621 let MethodProtos = [{
622 iterator allocation_order_begin(const MachineFunction &MF) const;
623 iterator allocation_order_end(const MachineFunction &MF) const;
625 let MethodBodies = [{
626 static const unsigned X86_GR32_NOSP_AO_64[] = {
627 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
628 X86::R8D, X86::R9D, X86::R10D, X86::R11D,
629 X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP
632 GR32_NOSPClass::iterator
633 GR32_NOSPClass::allocation_order_begin(const MachineFunction &MF) const {
634 const TargetMachine &TM = MF.getTarget();
635 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
636 if (Subtarget.is64Bit())
637 return X86_GR32_NOSP_AO_64;
642 GR32_NOSPClass::iterator
643 GR32_NOSPClass::allocation_order_end(const MachineFunction &MF) const {
644 const TargetMachine &TM = MF.getTarget();
645 const TargetRegisterInfo *RI = TM.getRegisterInfo();
646 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
647 if (Subtarget.is64Bit()) {
648 // Does the function dedicate RBP to being a frame ptr?
650 // If so, don't allocate EBP.
651 return array_endof(X86_GR32_NOSP_AO_64) - 1;
653 // If not, any reg in this class is ok.
654 return array_endof(X86_GR32_NOSP_AO_64);
656 // Does the function dedicate EBP to being a frame ptr?
658 // If so, don't allocate EBP.
661 // If not, any reg in this class is ok.
668 // GR64_NOSP - GR64 registers except RSP (and RIP).
669 def GR64_NOSP : RegisterClass<"X86", [i64], 64,
670 [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
671 RBX, R14, R15, R12, R13, RBP]> {
672 let SubRegClassList = [GR8, GR8, GR16, GR32_NOSP];
673 let MethodProtos = [{
674 iterator allocation_order_end(const MachineFunction &MF) const;
676 let MethodBodies = [{
677 GR64_NOSPClass::iterator
678 GR64_NOSPClass::allocation_order_end(const MachineFunction &MF) const {
679 const TargetMachine &TM = MF.getTarget();
680 const TargetRegisterInfo *RI = TM.getRegisterInfo();
681 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
682 if (!Subtarget.is64Bit())
683 return begin(); // None of these are allocatable in 32-bit.
684 if (RI->hasFP(MF)) // Does the function dedicate RBP to being a frame ptr?
685 return end()-1; // If so, don't allocate RBP
687 return end(); // If not, any reg in this class is ok.
692 // GR64_NOREX_NOSP - GR64_NOREX registers except RSP.
693 def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64,
694 [RAX, RCX, RDX, RSI, RDI, RBX, RBP]> {
695 let SubRegClassList = [GR8_NOREX, GR8_NOREX, GR16_NOREX, GR32_NOREX];
696 let MethodProtos = [{
697 iterator allocation_order_end(const MachineFunction &MF) const;
699 let MethodBodies = [{
700 GR64_NOREX_NOSPClass::iterator
701 GR64_NOREX_NOSPClass::allocation_order_end(const MachineFunction &MF) const
703 const TargetMachine &TM = MF.getTarget();
704 const TargetRegisterInfo *RI = TM.getRegisterInfo();
705 // Does the function dedicate RBP to being a frame ptr?
707 // If so, don't allocate RBP.
710 // If not, any reg in this class is ok.
716 // A class to support the 'A' assembler constraint: EAX then EDX.
717 def GR32_AD : RegisterClass<"X86", [i32], 32, [EAX, EDX]> {
718 let SubRegClassList = [GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD];
721 // Scalar SSE2 floating point registers.
722 def FR32 : RegisterClass<"X86", [f32], 32,
723 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
724 XMM8, XMM9, XMM10, XMM11,
725 XMM12, XMM13, XMM14, XMM15]> {
726 let MethodProtos = [{
727 iterator allocation_order_end(const MachineFunction &MF) const;
729 let MethodBodies = [{
731 FR32Class::allocation_order_end(const MachineFunction &MF) const {
732 const TargetMachine &TM = MF.getTarget();
733 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
734 if (!Subtarget.is64Bit())
735 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
742 def FR64 : RegisterClass<"X86", [f64], 64,
743 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
744 XMM8, XMM9, XMM10, XMM11,
745 XMM12, XMM13, XMM14, XMM15]> {
746 let MethodProtos = [{
747 iterator allocation_order_end(const MachineFunction &MF) const;
749 let MethodBodies = [{
751 FR64Class::allocation_order_end(const MachineFunction &MF) const {
752 const TargetMachine &TM = MF.getTarget();
753 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
754 if (!Subtarget.is64Bit())
755 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
763 // FIXME: This sets up the floating point register files as though they are f64
764 // values, though they really are f80 values. This will cause us to spill
765 // values as 64-bit quantities instead of 80-bit quantities, which is much much
766 // faster on common hardware. In reality, this should be controlled by a
767 // command line option or something.
769 def RFP32 : RegisterClass<"X86",[f32], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
770 def RFP64 : RegisterClass<"X86",[f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
771 def RFP80 : RegisterClass<"X86",[f80], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
773 // Floating point stack registers (these are not allocatable by the
774 // register allocator - the floating point stackifier is responsible
775 // for transforming FPn allocations to STn registers)
776 def RST : RegisterClass<"X86", [f80, f64, f32], 32,
777 [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
778 let MethodProtos = [{
779 iterator allocation_order_end(const MachineFunction &MF) const;
781 let MethodBodies = [{
783 RSTClass::allocation_order_end(const MachineFunction &MF) const {
789 // Generic vector registers: VR64 and VR128.
790 def VR64 : RegisterClass<"X86", [v8i8, v4i16, v2i32, v1i64, v2f32], 64,
791 [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
792 def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128,
793 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
794 XMM8, XMM9, XMM10, XMM11,
795 XMM12, XMM13, XMM14, XMM15]> {
796 let MethodProtos = [{
797 iterator allocation_order_end(const MachineFunction &MF) const;
799 let MethodBodies = [{
801 VR128Class::allocation_order_end(const MachineFunction &MF) const {
802 const TargetMachine &TM = MF.getTarget();
803 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
804 if (!Subtarget.is64Bit())
805 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
811 def VR256 : RegisterClass<"X86", [ v8i32, v4i64, v8f32, v4f64],256,
812 [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
813 YMM8, YMM9, YMM10, YMM11,
814 YMM12, YMM13, YMM14, YMM15]>;
816 // Status flags registers.
817 def CCR : RegisterClass<"X86", [i32], 32, [EFLAGS]> {
818 let CopyCost = -1; // Don't allow copying of status registers.