1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 Register file, defining the registers themselves,
11 // aliases between the registers, and the register classes built out of the
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Register definitions...
19 let Namespace = "X86" in {
21 // In the register alias definitions below, we define which registers alias
22 // which others. We only specify which registers the small registers alias,
23 // because the register file generator is smart enough to figure out that
24 // AL aliases AX if we tell it that AX aliased AL (for example).
26 // Dwarf numbering is different for 32-bit and 64-bit, and there are
27 // variations by target as well. Currently the first entry is for X86-64,
28 // second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux
29 // and debug information on X86-32/Darwin)
33 def AL : Register<"al">, DwarfRegNum<[0, 0, 0]>;
34 def DL : Register<"dl">, DwarfRegNum<[1, 2, 2]>;
35 def CL : Register<"cl">, DwarfRegNum<[2, 1, 1]>;
36 def BL : Register<"bl">, DwarfRegNum<[3, 3, 3]>;
39 def SIL : Register<"sil">, DwarfRegNum<[4, 6, 6]>;
40 def DIL : Register<"dil">, DwarfRegNum<[5, 7, 7]>;
41 def BPL : Register<"bpl">, DwarfRegNum<[6, 4, 5]>;
42 def SPL : Register<"spl">, DwarfRegNum<[7, 5, 4]>;
43 def R8B : Register<"r8b">, DwarfRegNum<[8, -2, -2]>;
44 def R9B : Register<"r9b">, DwarfRegNum<[9, -2, -2]>;
45 def R10B : Register<"r10b">, DwarfRegNum<[10, -2, -2]>;
46 def R11B : Register<"r11b">, DwarfRegNum<[11, -2, -2]>;
47 def R12B : Register<"r12b">, DwarfRegNum<[12, -2, -2]>;
48 def R13B : Register<"r13b">, DwarfRegNum<[13, -2, -2]>;
49 def R14B : Register<"r14b">, DwarfRegNum<[14, -2, -2]>;
50 def R15B : Register<"r15b">, DwarfRegNum<[15, -2, -2]>;
52 // High registers. On x86-64, these cannot be used in any instruction
54 def AH : Register<"ah">, DwarfRegNum<[0, 0, 0]>;
55 def DH : Register<"dh">, DwarfRegNum<[1, 2, 2]>;
56 def CH : Register<"ch">, DwarfRegNum<[2, 1, 1]>;
57 def BH : Register<"bh">, DwarfRegNum<[3, 3, 3]>;
60 def AX : RegisterWithSubRegs<"ax", [AL,AH]>, DwarfRegNum<[0, 0, 0]>;
61 def DX : RegisterWithSubRegs<"dx", [DL,DH]>, DwarfRegNum<[1, 2, 2]>;
62 def CX : RegisterWithSubRegs<"cx", [CL,CH]>, DwarfRegNum<[2, 1, 1]>;
63 def BX : RegisterWithSubRegs<"bx", [BL,BH]>, DwarfRegNum<[3, 3, 3]>;
64 def SI : RegisterWithSubRegs<"si", [SIL]>, DwarfRegNum<[4, 6, 6]>;
65 def DI : RegisterWithSubRegs<"di", [DIL]>, DwarfRegNum<[5, 7, 7]>;
66 def BP : RegisterWithSubRegs<"bp", [BPL]>, DwarfRegNum<[6, 4, 5]>;
67 def SP : RegisterWithSubRegs<"sp", [SPL]>, DwarfRegNum<[7, 5, 4]>;
68 def IP : Register<"ip">, DwarfRegNum<[16]>;
71 def R8W : RegisterWithSubRegs<"r8w", [R8B]>, DwarfRegNum<[8, -2, -2]>;
72 def R9W : RegisterWithSubRegs<"r9w", [R9B]>, DwarfRegNum<[9, -2, -2]>;
73 def R10W : RegisterWithSubRegs<"r10w", [R10B]>, DwarfRegNum<[10, -2, -2]>;
74 def R11W : RegisterWithSubRegs<"r11w", [R11B]>, DwarfRegNum<[11, -2, -2]>;
75 def R12W : RegisterWithSubRegs<"r12w", [R12B]>, DwarfRegNum<[12, -2, -2]>;
76 def R13W : RegisterWithSubRegs<"r13w", [R13B]>, DwarfRegNum<[13, -2, -2]>;
77 def R14W : RegisterWithSubRegs<"r14w", [R14B]>, DwarfRegNum<[14, -2, -2]>;
78 def R15W : RegisterWithSubRegs<"r15w", [R15B]>, DwarfRegNum<[15, -2, -2]>;
81 def EAX : RegisterWithSubRegs<"eax", [AX]>, DwarfRegNum<[0, 0, 0]>;
82 def EDX : RegisterWithSubRegs<"edx", [DX]>, DwarfRegNum<[1, 2, 2]>;
83 def ECX : RegisterWithSubRegs<"ecx", [CX]>, DwarfRegNum<[2, 1, 1]>;
84 def EBX : RegisterWithSubRegs<"ebx", [BX]>, DwarfRegNum<[3, 3, 3]>;
85 def ESI : RegisterWithSubRegs<"esi", [SI]>, DwarfRegNum<[4, 6, 6]>;
86 def EDI : RegisterWithSubRegs<"edi", [DI]>, DwarfRegNum<[5, 7, 7]>;
87 def EBP : RegisterWithSubRegs<"ebp", [BP]>, DwarfRegNum<[6, 4, 5]>;
88 def ESP : RegisterWithSubRegs<"esp", [SP]>, DwarfRegNum<[7, 5, 4]>;
89 def EIP : RegisterWithSubRegs<"eip", [IP]>, DwarfRegNum<[16, 8, 8]>;
92 def R8D : RegisterWithSubRegs<"r8d", [R8W]>, DwarfRegNum<[8, -2, -2]>;
93 def R9D : RegisterWithSubRegs<"r9d", [R9W]>, DwarfRegNum<[9, -2, -2]>;
94 def R10D : RegisterWithSubRegs<"r10d", [R10W]>, DwarfRegNum<[10, -2, -2]>;
95 def R11D : RegisterWithSubRegs<"r11d", [R11W]>, DwarfRegNum<[11, -2, -2]>;
96 def R12D : RegisterWithSubRegs<"r12d", [R12W]>, DwarfRegNum<[12, -2, -2]>;
97 def R13D : RegisterWithSubRegs<"r13d", [R13W]>, DwarfRegNum<[13, -2, -2]>;
98 def R14D : RegisterWithSubRegs<"r14d", [R14W]>, DwarfRegNum<[14, -2, -2]>;
99 def R15D : RegisterWithSubRegs<"r15d", [R15W]>, DwarfRegNum<[15, -2, -2]>;
101 // 64-bit registers, X86-64 only
102 def RAX : RegisterWithSubRegs<"rax", [EAX]>, DwarfRegNum<[0, -2, -2]>;
103 def RDX : RegisterWithSubRegs<"rdx", [EDX]>, DwarfRegNum<[1, -2, -2]>;
104 def RCX : RegisterWithSubRegs<"rcx", [ECX]>, DwarfRegNum<[2, -2, -2]>;
105 def RBX : RegisterWithSubRegs<"rbx", [EBX]>, DwarfRegNum<[3, -2, -2]>;
106 def RSI : RegisterWithSubRegs<"rsi", [ESI]>, DwarfRegNum<[4, -2, -2]>;
107 def RDI : RegisterWithSubRegs<"rdi", [EDI]>, DwarfRegNum<[5, -2, -2]>;
108 def RBP : RegisterWithSubRegs<"rbp", [EBP]>, DwarfRegNum<[6, -2, -2]>;
109 def RSP : RegisterWithSubRegs<"rsp", [ESP]>, DwarfRegNum<[7, -2, -2]>;
111 def R8 : RegisterWithSubRegs<"r8", [R8D]>, DwarfRegNum<[8, -2, -2]>;
112 def R9 : RegisterWithSubRegs<"r9", [R9D]>, DwarfRegNum<[9, -2, -2]>;
113 def R10 : RegisterWithSubRegs<"r10", [R10D]>, DwarfRegNum<[10, -2, -2]>;
114 def R11 : RegisterWithSubRegs<"r11", [R11D]>, DwarfRegNum<[11, -2, -2]>;
115 def R12 : RegisterWithSubRegs<"r12", [R12D]>, DwarfRegNum<[12, -2, -2]>;
116 def R13 : RegisterWithSubRegs<"r13", [R13D]>, DwarfRegNum<[13, -2, -2]>;
117 def R14 : RegisterWithSubRegs<"r14", [R14D]>, DwarfRegNum<[14, -2, -2]>;
118 def R15 : RegisterWithSubRegs<"r15", [R15D]>, DwarfRegNum<[15, -2, -2]>;
119 def RIP : RegisterWithSubRegs<"rip", [EIP]>, DwarfRegNum<[16, -2, -2]>;
121 // MMX Registers. These are actually aliased to ST0 .. ST7
122 def MM0 : Register<"mm0">, DwarfRegNum<[41, 29, 29]>;
123 def MM1 : Register<"mm1">, DwarfRegNum<[42, 30, 30]>;
124 def MM2 : Register<"mm2">, DwarfRegNum<[43, 31, 31]>;
125 def MM3 : Register<"mm3">, DwarfRegNum<[44, 32, 32]>;
126 def MM4 : Register<"mm4">, DwarfRegNum<[45, 33, 33]>;
127 def MM5 : Register<"mm5">, DwarfRegNum<[46, 34, 34]>;
128 def MM6 : Register<"mm6">, DwarfRegNum<[47, 35, 35]>;
129 def MM7 : Register<"mm7">, DwarfRegNum<[48, 36, 36]>;
131 // Pseudo Floating Point registers
132 def FP0 : Register<"fp0">;
133 def FP1 : Register<"fp1">;
134 def FP2 : Register<"fp2">;
135 def FP3 : Register<"fp3">;
136 def FP4 : Register<"fp4">;
137 def FP5 : Register<"fp5">;
138 def FP6 : Register<"fp6">;
140 // XMM Registers, used by the various SSE instruction set extensions
141 def XMM0: Register<"xmm0">, DwarfRegNum<[17, 21, 21]>;
142 def XMM1: Register<"xmm1">, DwarfRegNum<[18, 22, 22]>;
143 def XMM2: Register<"xmm2">, DwarfRegNum<[19, 23, 23]>;
144 def XMM3: Register<"xmm3">, DwarfRegNum<[20, 24, 24]>;
145 def XMM4: Register<"xmm4">, DwarfRegNum<[21, 25, 25]>;
146 def XMM5: Register<"xmm5">, DwarfRegNum<[22, 26, 26]>;
147 def XMM6: Register<"xmm6">, DwarfRegNum<[23, 27, 27]>;
148 def XMM7: Register<"xmm7">, DwarfRegNum<[24, 28, 28]>;
151 def XMM8: Register<"xmm8">, DwarfRegNum<[25, -2, -2]>;
152 def XMM9: Register<"xmm9">, DwarfRegNum<[26, -2, -2]>;
153 def XMM10: Register<"xmm10">, DwarfRegNum<[27, -2, -2]>;
154 def XMM11: Register<"xmm11">, DwarfRegNum<[28, -2, -2]>;
155 def XMM12: Register<"xmm12">, DwarfRegNum<[29, -2, -2]>;
156 def XMM13: Register<"xmm13">, DwarfRegNum<[30, -2, -2]>;
157 def XMM14: Register<"xmm14">, DwarfRegNum<[31, -2, -2]>;
158 def XMM15: Register<"xmm15">, DwarfRegNum<[32, -2, -2]>;
160 // YMM Registers, used by AVX instructions
161 def YMM0: RegisterWithSubRegs<"ymm0", [XMM0]>, DwarfRegNum<[17, 21, 21]>;
162 def YMM1: RegisterWithSubRegs<"ymm1", [XMM1]>, DwarfRegNum<[18, 22, 22]>;
163 def YMM2: RegisterWithSubRegs<"ymm2", [XMM2]>, DwarfRegNum<[19, 23, 23]>;
164 def YMM3: RegisterWithSubRegs<"ymm3", [XMM3]>, DwarfRegNum<[20, 24, 24]>;
165 def YMM4: RegisterWithSubRegs<"ymm4", [XMM4]>, DwarfRegNum<[21, 25, 25]>;
166 def YMM5: RegisterWithSubRegs<"ymm5", [XMM5]>, DwarfRegNum<[22, 26, 26]>;
167 def YMM6: RegisterWithSubRegs<"ymm6", [XMM6]>, DwarfRegNum<[23, 27, 27]>;
168 def YMM7: RegisterWithSubRegs<"ymm7", [XMM7]>, DwarfRegNum<[24, 28, 28]>;
169 def YMM8: RegisterWithSubRegs<"ymm8", [XMM8]>, DwarfRegNum<[25, -2, -2]>;
170 def YMM9: RegisterWithSubRegs<"ymm9", [XMM9]>, DwarfRegNum<[26, -2, -2]>;
171 def YMM10: RegisterWithSubRegs<"ymm10", [XMM10]>, DwarfRegNum<[27, -2, -2]>;
172 def YMM11: RegisterWithSubRegs<"ymm11", [XMM11]>, DwarfRegNum<[28, -2, -2]>;
173 def YMM12: RegisterWithSubRegs<"ymm12", [XMM12]>, DwarfRegNum<[29, -2, -2]>;
174 def YMM13: RegisterWithSubRegs<"ymm13", [XMM13]>, DwarfRegNum<[30, -2, -2]>;
175 def YMM14: RegisterWithSubRegs<"ymm14", [XMM14]>, DwarfRegNum<[31, -2, -2]>;
176 def YMM15: RegisterWithSubRegs<"ymm15", [XMM15]>, DwarfRegNum<[32, -2, -2]>;
178 // Floating point stack registers
179 def ST0 : Register<"st(0)">, DwarfRegNum<[33, 12, 11]>;
180 def ST1 : Register<"st(1)">, DwarfRegNum<[34, 13, 12]>;
181 def ST2 : Register<"st(2)">, DwarfRegNum<[35, 14, 13]>;
182 def ST3 : Register<"st(3)">, DwarfRegNum<[36, 15, 14]>;
183 def ST4 : Register<"st(4)">, DwarfRegNum<[37, 16, 15]>;
184 def ST5 : Register<"st(5)">, DwarfRegNum<[38, 17, 16]>;
185 def ST6 : Register<"st(6)">, DwarfRegNum<[39, 18, 17]>;
186 def ST7 : Register<"st(7)">, DwarfRegNum<[40, 19, 18]>;
188 // Status flags register
189 def EFLAGS : Register<"flags">;
192 def CS : Register<"cs">;
193 def DS : Register<"ds">;
194 def SS : Register<"ss">;
195 def ES : Register<"es">;
196 def FS : Register<"fs">;
197 def GS : Register<"gs">;
200 def DR0 : Register<"dr0">;
201 def DR1 : Register<"dr1">;
202 def DR2 : Register<"dr2">;
203 def DR3 : Register<"dr3">;
204 def DR4 : Register<"dr4">;
205 def DR5 : Register<"dr5">;
206 def DR6 : Register<"dr6">;
207 def DR7 : Register<"dr7">;
209 // Condition registers
210 def ECR0 : Register<"ecr0">;
211 def ECR1 : Register<"ecr1">;
212 def ECR2 : Register<"ecr2">;
213 def ECR3 : Register<"ecr3">;
214 def ECR4 : Register<"ecr4">;
215 def ECR5 : Register<"ecr5">;
216 def ECR6 : Register<"ecr6">;
217 def ECR7 : Register<"ecr7">;
219 def RCR0 : Register<"rcr0">;
220 def RCR1 : Register<"rcr1">;
221 def RCR2 : Register<"rcr2">;
222 def RCR3 : Register<"rcr3">;
223 def RCR4 : Register<"rcr4">;
224 def RCR5 : Register<"rcr5">;
225 def RCR6 : Register<"rcr6">;
226 def RCR7 : Register<"rcr7">;
227 def RCR8 : Register<"rcr8">;
231 //===----------------------------------------------------------------------===//
232 // Subregister Set Definitions... now that we have all of the pieces, define the
233 // sub registers for each register.
236 def x86_subreg_8bit : PatLeaf<(i32 1)>;
237 def x86_subreg_8bit_hi : PatLeaf<(i32 2)>;
238 def x86_subreg_16bit : PatLeaf<(i32 3)>;
239 def x86_subreg_32bit : PatLeaf<(i32 4)>;
241 def x86_subreg_ss : PatLeaf<(i32 1)>;
242 def x86_subreg_sd : PatLeaf<(i32 2)>;
243 def x86_subreg_xmm : PatLeaf<(i32 3)>;
245 def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
246 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
247 [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
248 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
250 def : SubRegSet<2, [AX, CX, DX, BX],
253 def : SubRegSet<1, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
254 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
255 [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
256 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
258 def : SubRegSet<2, [EAX, ECX, EDX, EBX],
261 def : SubRegSet<3, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
262 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
263 [AX, CX, DX, BX, SP, BP, SI, DI,
264 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
266 def : SubRegSet<1, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
267 R8, R9, R10, R11, R12, R13, R14, R15],
268 [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
269 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
271 def : SubRegSet<2, [RAX, RCX, RDX, RBX],
274 def : SubRegSet<3, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
275 R8, R9, R10, R11, R12, R13, R14, R15],
276 [AX, CX, DX, BX, SP, BP, SI, DI,
277 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
279 def : SubRegSet<4, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
280 R8, R9, R10, R11, R12, R13, R14, R15],
281 [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
282 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]>;
284 def : SubRegSet<1, [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
285 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15],
286 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
287 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
289 def : SubRegSet<2, [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
290 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15],
291 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
292 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
294 def : SubRegSet<3, [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
295 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15],
296 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
297 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
299 def : SubRegSet<1, [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
300 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15],
301 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
302 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
304 def : SubRegSet<2, [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
305 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15],
306 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
307 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
309 //===----------------------------------------------------------------------===//
310 // Register Class Definitions... now that we have all of the pieces, define the
311 // top-level register classes. The order specified in the register list is
312 // implicitly defined to be the register allocation order.
315 // List call-clobbered registers before callee-save registers. RBX, RBP, (and
316 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
317 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
319 // Allocate R12 and R13 last, as these require an extra byte when
320 // encoded in x86_64 instructions.
321 // FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in
322 // 64-bit mode. The main complication is that they cannot be encoded in an
323 // instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc.
324 // require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d"
325 // cannot be encoded.
326 def GR8 : RegisterClass<"X86", [i8], 8,
327 [AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
328 R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B]> {
329 let MethodProtos = [{
330 iterator allocation_order_begin(const MachineFunction &MF) const;
331 iterator allocation_order_end(const MachineFunction &MF) const;
333 let MethodBodies = [{
334 static const unsigned X86_GR8_AO_64[] = {
335 X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
336 X86::R8B, X86::R9B, X86::R10B, X86::R11B,
337 X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL
341 GR8Class::allocation_order_begin(const MachineFunction &MF) const {
342 const TargetMachine &TM = MF.getTarget();
343 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
344 if (Subtarget.is64Bit())
345 return X86_GR8_AO_64;
351 GR8Class::allocation_order_end(const MachineFunction &MF) const {
352 const TargetMachine &TM = MF.getTarget();
353 const TargetRegisterInfo *RI = TM.getRegisterInfo();
354 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
355 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
356 // Does the function dedicate RBP / EBP to being a frame ptr?
357 if (!Subtarget.is64Bit())
358 // In 32-mode, none of the 8-bit registers aliases EBP or ESP.
360 else if (RI->hasFP(MF) || MFI->getReserveFP())
361 // If so, don't allocate SPL or BPL.
362 return array_endof(X86_GR8_AO_64) - 1;
364 // If not, just don't allocate SPL.
365 return array_endof(X86_GR8_AO_64);
370 def GR16 : RegisterClass<"X86", [i16], 16,
371 [AX, CX, DX, SI, DI, BX, BP, SP,
372 R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W]> {
373 let SubRegClassList = [GR8, GR8];
374 let MethodProtos = [{
375 iterator allocation_order_begin(const MachineFunction &MF) const;
376 iterator allocation_order_end(const MachineFunction &MF) const;
378 let MethodBodies = [{
379 static const unsigned X86_GR16_AO_64[] = {
380 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
381 X86::R8W, X86::R9W, X86::R10W, X86::R11W,
382 X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::BP
386 GR16Class::allocation_order_begin(const MachineFunction &MF) const {
387 const TargetMachine &TM = MF.getTarget();
388 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
389 if (Subtarget.is64Bit())
390 return X86_GR16_AO_64;
396 GR16Class::allocation_order_end(const MachineFunction &MF) const {
397 const TargetMachine &TM = MF.getTarget();
398 const TargetRegisterInfo *RI = TM.getRegisterInfo();
399 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
400 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
401 if (Subtarget.is64Bit()) {
402 // Does the function dedicate RBP to being a frame ptr?
403 if (RI->hasFP(MF) || MFI->getReserveFP())
404 // If so, don't allocate SP or BP.
405 return array_endof(X86_GR16_AO_64) - 1;
407 // If not, just don't allocate SP.
408 return array_endof(X86_GR16_AO_64);
410 // Does the function dedicate EBP to being a frame ptr?
411 if (RI->hasFP(MF) || MFI->getReserveFP())
412 // If so, don't allocate SP or BP.
415 // If not, just don't allocate SP.
422 def GR32 : RegisterClass<"X86", [i32], 32,
423 [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
424 R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> {
425 let SubRegClassList = [GR8, GR8, GR16];
426 let MethodProtos = [{
427 iterator allocation_order_begin(const MachineFunction &MF) const;
428 iterator allocation_order_end(const MachineFunction &MF) const;
430 let MethodBodies = [{
431 static const unsigned X86_GR32_AO_64[] = {
432 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
433 X86::R8D, X86::R9D, X86::R10D, X86::R11D,
434 X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP
438 GR32Class::allocation_order_begin(const MachineFunction &MF) const {
439 const TargetMachine &TM = MF.getTarget();
440 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
441 if (Subtarget.is64Bit())
442 return X86_GR32_AO_64;
448 GR32Class::allocation_order_end(const MachineFunction &MF) const {
449 const TargetMachine &TM = MF.getTarget();
450 const TargetRegisterInfo *RI = TM.getRegisterInfo();
451 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
452 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
453 if (Subtarget.is64Bit()) {
454 // Does the function dedicate RBP to being a frame ptr?
455 if (RI->hasFP(MF) || MFI->getReserveFP())
456 // If so, don't allocate ESP or EBP.
457 return array_endof(X86_GR32_AO_64) - 1;
459 // If not, just don't allocate ESP.
460 return array_endof(X86_GR32_AO_64);
462 // Does the function dedicate EBP to being a frame ptr?
463 if (RI->hasFP(MF) || MFI->getReserveFP())
464 // If so, don't allocate ESP or EBP.
467 // If not, just don't allocate ESP.
474 // GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
475 // RIP isn't really a register and it can't be used anywhere except in an
476 // address, but it doesn't cause trouble.
477 def GR64 : RegisterClass<"X86", [i64], 64,
478 [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
479 RBX, R14, R15, R12, R13, RBP, RSP, RIP]> {
480 let SubRegClassList = [GR8, GR8, GR16, GR32];
481 let MethodProtos = [{
482 iterator allocation_order_end(const MachineFunction &MF) const;
484 let MethodBodies = [{
486 GR64Class::allocation_order_end(const MachineFunction &MF) const {
487 const TargetMachine &TM = MF.getTarget();
488 const TargetRegisterInfo *RI = TM.getRegisterInfo();
489 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
490 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
491 if (!Subtarget.is64Bit())
492 return begin(); // None of these are allocatable in 32-bit.
493 // Does the function dedicate RBP to being a frame ptr?
494 if (RI->hasFP(MF) || MFI->getReserveFP())
495 return end()-3; // If so, don't allocate RIP, RSP or RBP
497 return end()-2; // If not, just don't allocate RIP or RSP
502 // Segment registers for use by MOV instructions (and others) that have a
503 // segment register as one operand. Always contain a 16-bit segment
505 def SEGMENT_REG : RegisterClass<"X86", [i16], 16, [CS, DS, SS, ES, FS, GS]> {
509 def DEBUG_REG : RegisterClass<"X86", [i32], 32,
510 [DR0, DR1, DR2, DR3, DR4, DR5, DR6, DR7]> {
513 // Control registers.
514 def CONTROL_REG_32 : RegisterClass<"X86", [i32], 32,
515 [ECR0, ECR1, ECR2, ECR3, ECR4, ECR5, ECR6,
519 def CONTROL_REG_64 : RegisterClass<"X86", [i64], 64,
520 [RCR0, RCR1, RCR2, RCR3, RCR4, RCR5, RCR6,
524 // GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of
525 // GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d"
526 // registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers
527 // that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD,
528 // and GR64_ABCD are classes for registers that support 8-bit h-register
530 def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL]> {
532 def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, [AH, CH, DH, BH]> {
534 def GR16_ABCD : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
535 let SubRegClassList = [GR8_ABCD_L, GR8_ABCD_H];
537 def GR32_ABCD : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
538 let SubRegClassList = [GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD];
540 def GR64_ABCD : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RBX]> {
541 let SubRegClassList = [GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD];
543 def GR32_TC : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX]> {
544 let SubRegClassList = [GR8, GR8, GR16];
546 def GR64_TC : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RSI, RDI,
548 let SubRegClassList = [GR8, GR8, GR16, GR32_TC];
551 // GR8_NOREX - GR8 registers which do not require a REX prefix.
552 def GR8_NOREX : RegisterClass<"X86", [i8], 8,
553 [AL, CL, DL, AH, CH, DH, BL, BH]> {
554 let MethodProtos = [{
555 iterator allocation_order_begin(const MachineFunction &MF) const;
556 iterator allocation_order_end(const MachineFunction &MF) const;
558 let MethodBodies = [{
559 // In 64-bit mode, it's not safe to blindly allocate H registers.
560 static const unsigned X86_GR8_NOREX_AO_64[] = {
561 X86::AL, X86::CL, X86::DL, X86::BL
564 GR8_NOREXClass::iterator
565 GR8_NOREXClass::allocation_order_begin(const MachineFunction &MF) const {
566 const TargetMachine &TM = MF.getTarget();
567 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
568 if (Subtarget.is64Bit())
569 return X86_GR8_NOREX_AO_64;
574 GR8_NOREXClass::iterator
575 GR8_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
576 const TargetMachine &TM = MF.getTarget();
577 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
578 if (Subtarget.is64Bit())
579 return array_endof(X86_GR8_NOREX_AO_64);
585 // GR16_NOREX - GR16 registers which do not require a REX prefix.
586 def GR16_NOREX : RegisterClass<"X86", [i16], 16,
587 [AX, CX, DX, SI, DI, BX, BP, SP]> {
588 let SubRegClassList = [GR8_NOREX, GR8_NOREX];
589 let MethodProtos = [{
590 iterator allocation_order_end(const MachineFunction &MF) const;
592 let MethodBodies = [{
593 GR16_NOREXClass::iterator
594 GR16_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
595 const TargetMachine &TM = MF.getTarget();
596 const TargetRegisterInfo *RI = TM.getRegisterInfo();
597 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
598 // Does the function dedicate RBP / EBP to being a frame ptr?
599 if (RI->hasFP(MF) || MFI->getReserveFP())
600 // If so, don't allocate SP or BP.
603 // If not, just don't allocate SP.
608 // GR32_NOREX - GR32 registers which do not require a REX prefix.
609 def GR32_NOREX : RegisterClass<"X86", [i32], 32,
610 [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
611 let SubRegClassList = [GR8_NOREX, GR8_NOREX, GR16_NOREX];
612 let MethodProtos = [{
613 iterator allocation_order_end(const MachineFunction &MF) const;
615 let MethodBodies = [{
616 GR32_NOREXClass::iterator
617 GR32_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
618 const TargetMachine &TM = MF.getTarget();
619 const TargetRegisterInfo *RI = TM.getRegisterInfo();
620 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
621 // Does the function dedicate RBP / EBP to being a frame ptr?
622 if (RI->hasFP(MF) || MFI->getReserveFP())
623 // If so, don't allocate ESP or EBP.
626 // If not, just don't allocate ESP.
631 // GR64_NOREX - GR64 registers which do not require a REX prefix.
632 def GR64_NOREX : RegisterClass<"X86", [i64], 64,
633 [RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP]> {
634 let SubRegClassList = [GR8_NOREX, GR8_NOREX, GR16_NOREX, GR32_NOREX];
635 let MethodProtos = [{
636 iterator allocation_order_end(const MachineFunction &MF) const;
638 let MethodBodies = [{
639 GR64_NOREXClass::iterator
640 GR64_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
641 const TargetMachine &TM = MF.getTarget();
642 const TargetRegisterInfo *RI = TM.getRegisterInfo();
643 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
644 // Does the function dedicate RBP to being a frame ptr?
645 if (RI->hasFP(MF) || MFI->getReserveFP())
646 // If so, don't allocate RIP, RSP or RBP.
649 // If not, just don't allocate RIP or RSP.
655 // GR32_NOSP - GR32 registers except ESP.
656 def GR32_NOSP : RegisterClass<"X86", [i32], 32,
657 [EAX, ECX, EDX, ESI, EDI, EBX, EBP,
658 R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> {
659 let SubRegClassList = [GR8, GR8, GR16];
660 let MethodProtos = [{
661 iterator allocation_order_begin(const MachineFunction &MF) const;
662 iterator allocation_order_end(const MachineFunction &MF) const;
664 let MethodBodies = [{
665 static const unsigned X86_GR32_NOSP_AO_64[] = {
666 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
667 X86::R8D, X86::R9D, X86::R10D, X86::R11D,
668 X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP
671 GR32_NOSPClass::iterator
672 GR32_NOSPClass::allocation_order_begin(const MachineFunction &MF) const {
673 const TargetMachine &TM = MF.getTarget();
674 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
675 if (Subtarget.is64Bit())
676 return X86_GR32_NOSP_AO_64;
681 GR32_NOSPClass::iterator
682 GR32_NOSPClass::allocation_order_end(const MachineFunction &MF) const {
683 const TargetMachine &TM = MF.getTarget();
684 const TargetRegisterInfo *RI = TM.getRegisterInfo();
685 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
686 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
687 if (Subtarget.is64Bit()) {
688 // Does the function dedicate RBP to being a frame ptr?
689 if (RI->hasFP(MF) || MFI->getReserveFP())
690 // If so, don't allocate EBP.
691 return array_endof(X86_GR32_NOSP_AO_64) - 1;
693 // If not, any reg in this class is ok.
694 return array_endof(X86_GR32_NOSP_AO_64);
696 // Does the function dedicate EBP to being a frame ptr?
697 if (RI->hasFP(MF) || MFI->getReserveFP())
698 // If so, don't allocate EBP.
701 // If not, any reg in this class is ok.
708 // GR64_NOSP - GR64 registers except RSP (and RIP).
709 def GR64_NOSP : RegisterClass<"X86", [i64], 64,
710 [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
711 RBX, R14, R15, R12, R13, RBP]> {
712 let SubRegClassList = [GR8, GR8, GR16, GR32_NOSP];
713 let MethodProtos = [{
714 iterator allocation_order_end(const MachineFunction &MF) const;
716 let MethodBodies = [{
717 GR64_NOSPClass::iterator
718 GR64_NOSPClass::allocation_order_end(const MachineFunction &MF) const {
719 const TargetMachine &TM = MF.getTarget();
720 const TargetRegisterInfo *RI = TM.getRegisterInfo();
721 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
722 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
723 if (!Subtarget.is64Bit())
724 return begin(); // None of these are allocatable in 32-bit.
725 // Does the function dedicate RBP to being a frame ptr?
726 if (RI->hasFP(MF) || MFI->getReserveFP())
727 return end()-1; // If so, don't allocate RBP
729 return end(); // If not, any reg in this class is ok.
734 // GR64_NOREX_NOSP - GR64_NOREX registers except RSP.
735 def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64,
736 [RAX, RCX, RDX, RSI, RDI, RBX, RBP]> {
737 let SubRegClassList = [GR8_NOREX, GR8_NOREX, GR16_NOREX, GR32_NOREX];
738 let MethodProtos = [{
739 iterator allocation_order_end(const MachineFunction &MF) const;
741 let MethodBodies = [{
742 GR64_NOREX_NOSPClass::iterator
743 GR64_NOREX_NOSPClass::allocation_order_end(const MachineFunction &MF) const
745 const TargetMachine &TM = MF.getTarget();
746 const TargetRegisterInfo *RI = TM.getRegisterInfo();
747 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
748 // Does the function dedicate RBP to being a frame ptr?
749 if (RI->hasFP(MF) || MFI->getReserveFP())
750 // If so, don't allocate RBP.
753 // If not, any reg in this class is ok.
759 // A class to support the 'A' assembler constraint: EAX then EDX.
760 def GR32_AD : RegisterClass<"X86", [i32], 32, [EAX, EDX]> {
761 let SubRegClassList = [GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD];
764 // Scalar SSE2 floating point registers.
765 def FR32 : RegisterClass<"X86", [f32], 32,
766 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
767 XMM8, XMM9, XMM10, XMM11,
768 XMM12, XMM13, XMM14, XMM15]> {
769 let MethodProtos = [{
770 iterator allocation_order_end(const MachineFunction &MF) const;
772 let MethodBodies = [{
774 FR32Class::allocation_order_end(const MachineFunction &MF) const {
775 const TargetMachine &TM = MF.getTarget();
776 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
777 if (!Subtarget.is64Bit())
778 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
785 def FR64 : RegisterClass<"X86", [f64], 64,
786 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
787 XMM8, XMM9, XMM10, XMM11,
788 XMM12, XMM13, XMM14, XMM15]> {
789 let MethodProtos = [{
790 iterator allocation_order_end(const MachineFunction &MF) const;
792 let MethodBodies = [{
794 FR64Class::allocation_order_end(const MachineFunction &MF) const {
795 const TargetMachine &TM = MF.getTarget();
796 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
797 if (!Subtarget.is64Bit())
798 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
806 // FIXME: This sets up the floating point register files as though they are f64
807 // values, though they really are f80 values. This will cause us to spill
808 // values as 64-bit quantities instead of 80-bit quantities, which is much much
809 // faster on common hardware. In reality, this should be controlled by a
810 // command line option or something.
812 def RFP32 : RegisterClass<"X86",[f32], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
813 def RFP64 : RegisterClass<"X86",[f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
814 def RFP80 : RegisterClass<"X86",[f80], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
816 // Floating point stack registers (these are not allocatable by the
817 // register allocator - the floating point stackifier is responsible
818 // for transforming FPn allocations to STn registers)
819 def RST : RegisterClass<"X86", [f80, f64, f32], 32,
820 [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
821 let MethodProtos = [{
822 iterator allocation_order_end(const MachineFunction &MF) const;
824 let MethodBodies = [{
826 RSTClass::allocation_order_end(const MachineFunction &MF) const {
832 // Generic vector registers: VR64 and VR128.
833 def VR64 : RegisterClass<"X86", [v8i8, v4i16, v2i32, v1i64, v2f32], 64,
834 [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
835 def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128,
836 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
837 XMM8, XMM9, XMM10, XMM11,
838 XMM12, XMM13, XMM14, XMM15]> {
839 let SubRegClassList = [FR32, FR64];
840 let MethodProtos = [{
841 iterator allocation_order_end(const MachineFunction &MF) const;
843 let MethodBodies = [{
845 VR128Class::allocation_order_end(const MachineFunction &MF) const {
846 const TargetMachine &TM = MF.getTarget();
847 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
848 if (!Subtarget.is64Bit())
849 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
855 def VR256 : RegisterClass<"X86", [ v8i32, v4i64, v8f32, v4f64],256,
856 [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
857 YMM8, YMM9, YMM10, YMM11,
858 YMM12, YMM13, YMM14, YMM15]> {
859 let SubRegClassList = [FR32, FR64, VR128];
862 // Status flags registers.
863 def CCR : RegisterClass<"X86", [i32], 32, [EFLAGS]> {
864 let CopyCost = -1; // Don't allow copying of status registers.