1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 Register file, defining the registers themselves,
11 // aliases between the registers, and the register classes built out of the
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Register definitions...
19 let Namespace = "X86" in {
21 // Subregister indices.
22 def sub_8bit : SubRegIndex;
23 def sub_8bit_hi : SubRegIndex;
24 def sub_16bit : SubRegIndex;
25 def sub_32bit : SubRegIndex;
27 def sub_ss : SubRegIndex;
28 def sub_sd : SubRegIndex;
29 def sub_xmm : SubRegIndex;
32 // In the register alias definitions below, we define which registers alias
33 // which others. We only specify which registers the small registers alias,
34 // because the register file generator is smart enough to figure out that
35 // AL aliases AX if we tell it that AX aliased AL (for example).
37 // Dwarf numbering is different for 32-bit and 64-bit, and there are
38 // variations by target as well. Currently the first entry is for X86-64,
39 // second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux
40 // and debug information on X86-32/Darwin)
44 def AL : Register<"al">, DwarfRegNum<[0, 0, 0]>;
45 def DL : Register<"dl">, DwarfRegNum<[1, 2, 2]>;
46 def CL : Register<"cl">, DwarfRegNum<[2, 1, 1]>;
47 def BL : Register<"bl">, DwarfRegNum<[3, 3, 3]>;
49 // X86-64 only, requires REX.
50 let CostPerUse = 1 in {
51 def SIL : Register<"sil">, DwarfRegNum<[4, 6, 6]>;
52 def DIL : Register<"dil">, DwarfRegNum<[5, 7, 7]>;
53 def BPL : Register<"bpl">, DwarfRegNum<[6, 4, 5]>;
54 def SPL : Register<"spl">, DwarfRegNum<[7, 5, 4]>;
55 def R8B : Register<"r8b">, DwarfRegNum<[8, -2, -2]>;
56 def R9B : Register<"r9b">, DwarfRegNum<[9, -2, -2]>;
57 def R10B : Register<"r10b">, DwarfRegNum<[10, -2, -2]>;
58 def R11B : Register<"r11b">, DwarfRegNum<[11, -2, -2]>;
59 def R12B : Register<"r12b">, DwarfRegNum<[12, -2, -2]>;
60 def R13B : Register<"r13b">, DwarfRegNum<[13, -2, -2]>;
61 def R14B : Register<"r14b">, DwarfRegNum<[14, -2, -2]>;
62 def R15B : Register<"r15b">, DwarfRegNum<[15, -2, -2]>;
65 // High registers. On x86-64, these cannot be used in any instruction
67 def AH : Register<"ah">, DwarfRegNum<[0, 0, 0]>;
68 def DH : Register<"dh">, DwarfRegNum<[1, 2, 2]>;
69 def CH : Register<"ch">, DwarfRegNum<[2, 1, 1]>;
70 def BH : Register<"bh">, DwarfRegNum<[3, 3, 3]>;
73 let SubRegIndices = [sub_8bit, sub_8bit_hi] in {
74 def AX : RegisterWithSubRegs<"ax", [AL,AH]>, DwarfRegNum<[0, 0, 0]>;
75 def DX : RegisterWithSubRegs<"dx", [DL,DH]>, DwarfRegNum<[1, 2, 2]>;
76 def CX : RegisterWithSubRegs<"cx", [CL,CH]>, DwarfRegNum<[2, 1, 1]>;
77 def BX : RegisterWithSubRegs<"bx", [BL,BH]>, DwarfRegNum<[3, 3, 3]>;
79 let SubRegIndices = [sub_8bit] in {
80 def SI : RegisterWithSubRegs<"si", [SIL]>, DwarfRegNum<[4, 6, 6]>;
81 def DI : RegisterWithSubRegs<"di", [DIL]>, DwarfRegNum<[5, 7, 7]>;
82 def BP : RegisterWithSubRegs<"bp", [BPL]>, DwarfRegNum<[6, 4, 5]>;
83 def SP : RegisterWithSubRegs<"sp", [SPL]>, DwarfRegNum<[7, 5, 4]>;
85 def IP : Register<"ip">, DwarfRegNum<[16]>;
87 // X86-64 only, requires REX.
88 let SubRegIndices = [sub_8bit], CostPerUse = 1 in {
89 def R8W : RegisterWithSubRegs<"r8w", [R8B]>, DwarfRegNum<[8, -2, -2]>;
90 def R9W : RegisterWithSubRegs<"r9w", [R9B]>, DwarfRegNum<[9, -2, -2]>;
91 def R10W : RegisterWithSubRegs<"r10w", [R10B]>, DwarfRegNum<[10, -2, -2]>;
92 def R11W : RegisterWithSubRegs<"r11w", [R11B]>, DwarfRegNum<[11, -2, -2]>;
93 def R12W : RegisterWithSubRegs<"r12w", [R12B]>, DwarfRegNum<[12, -2, -2]>;
94 def R13W : RegisterWithSubRegs<"r13w", [R13B]>, DwarfRegNum<[13, -2, -2]>;
95 def R14W : RegisterWithSubRegs<"r14w", [R14B]>, DwarfRegNum<[14, -2, -2]>;
96 def R15W : RegisterWithSubRegs<"r15w", [R15B]>, DwarfRegNum<[15, -2, -2]>;
99 let SubRegIndices = [sub_16bit] in {
100 def EAX : RegisterWithSubRegs<"eax", [AX]>, DwarfRegNum<[0, 0, 0]>;
101 def EDX : RegisterWithSubRegs<"edx", [DX]>, DwarfRegNum<[1, 2, 2]>;
102 def ECX : RegisterWithSubRegs<"ecx", [CX]>, DwarfRegNum<[2, 1, 1]>;
103 def EBX : RegisterWithSubRegs<"ebx", [BX]>, DwarfRegNum<[3, 3, 3]>;
104 def ESI : RegisterWithSubRegs<"esi", [SI]>, DwarfRegNum<[4, 6, 6]>;
105 def EDI : RegisterWithSubRegs<"edi", [DI]>, DwarfRegNum<[5, 7, 7]>;
106 def EBP : RegisterWithSubRegs<"ebp", [BP]>, DwarfRegNum<[6, 4, 5]>;
107 def ESP : RegisterWithSubRegs<"esp", [SP]>, DwarfRegNum<[7, 5, 4]>;
108 def EIP : RegisterWithSubRegs<"eip", [IP]>, DwarfRegNum<[16, 8, 8]>;
110 // X86-64 only, requires REX
111 let CostPerUse = 1 in {
112 def R8D : RegisterWithSubRegs<"r8d", [R8W]>, DwarfRegNum<[8, -2, -2]>;
113 def R9D : RegisterWithSubRegs<"r9d", [R9W]>, DwarfRegNum<[9, -2, -2]>;
114 def R10D : RegisterWithSubRegs<"r10d", [R10W]>, DwarfRegNum<[10, -2, -2]>;
115 def R11D : RegisterWithSubRegs<"r11d", [R11W]>, DwarfRegNum<[11, -2, -2]>;
116 def R12D : RegisterWithSubRegs<"r12d", [R12W]>, DwarfRegNum<[12, -2, -2]>;
117 def R13D : RegisterWithSubRegs<"r13d", [R13W]>, DwarfRegNum<[13, -2, -2]>;
118 def R14D : RegisterWithSubRegs<"r14d", [R14W]>, DwarfRegNum<[14, -2, -2]>;
119 def R15D : RegisterWithSubRegs<"r15d", [R15W]>, DwarfRegNum<[15, -2, -2]>;
122 // 64-bit registers, X86-64 only
123 let SubRegIndices = [sub_32bit] in {
124 def RAX : RegisterWithSubRegs<"rax", [EAX]>, DwarfRegNum<[0, -2, -2]>;
125 def RDX : RegisterWithSubRegs<"rdx", [EDX]>, DwarfRegNum<[1, -2, -2]>;
126 def RCX : RegisterWithSubRegs<"rcx", [ECX]>, DwarfRegNum<[2, -2, -2]>;
127 def RBX : RegisterWithSubRegs<"rbx", [EBX]>, DwarfRegNum<[3, -2, -2]>;
128 def RSI : RegisterWithSubRegs<"rsi", [ESI]>, DwarfRegNum<[4, -2, -2]>;
129 def RDI : RegisterWithSubRegs<"rdi", [EDI]>, DwarfRegNum<[5, -2, -2]>;
130 def RBP : RegisterWithSubRegs<"rbp", [EBP]>, DwarfRegNum<[6, -2, -2]>;
131 def RSP : RegisterWithSubRegs<"rsp", [ESP]>, DwarfRegNum<[7, -2, -2]>;
133 // These also require REX.
134 let CostPerUse = 1 in {
135 def R8 : RegisterWithSubRegs<"r8", [R8D]>, DwarfRegNum<[8, -2, -2]>;
136 def R9 : RegisterWithSubRegs<"r9", [R9D]>, DwarfRegNum<[9, -2, -2]>;
137 def R10 : RegisterWithSubRegs<"r10", [R10D]>, DwarfRegNum<[10, -2, -2]>;
138 def R11 : RegisterWithSubRegs<"r11", [R11D]>, DwarfRegNum<[11, -2, -2]>;
139 def R12 : RegisterWithSubRegs<"r12", [R12D]>, DwarfRegNum<[12, -2, -2]>;
140 def R13 : RegisterWithSubRegs<"r13", [R13D]>, DwarfRegNum<[13, -2, -2]>;
141 def R14 : RegisterWithSubRegs<"r14", [R14D]>, DwarfRegNum<[14, -2, -2]>;
142 def R15 : RegisterWithSubRegs<"r15", [R15D]>, DwarfRegNum<[15, -2, -2]>;
143 def RIP : RegisterWithSubRegs<"rip", [EIP]>, DwarfRegNum<[16, -2, -2]>;
146 // MMX Registers. These are actually aliased to ST0 .. ST7
147 def MM0 : Register<"mm0">, DwarfRegNum<[41, 29, 29]>;
148 def MM1 : Register<"mm1">, DwarfRegNum<[42, 30, 30]>;
149 def MM2 : Register<"mm2">, DwarfRegNum<[43, 31, 31]>;
150 def MM3 : Register<"mm3">, DwarfRegNum<[44, 32, 32]>;
151 def MM4 : Register<"mm4">, DwarfRegNum<[45, 33, 33]>;
152 def MM5 : Register<"mm5">, DwarfRegNum<[46, 34, 34]>;
153 def MM6 : Register<"mm6">, DwarfRegNum<[47, 35, 35]>;
154 def MM7 : Register<"mm7">, DwarfRegNum<[48, 36, 36]>;
156 // Pseudo Floating Point registers
157 def FP0 : Register<"fp0">;
158 def FP1 : Register<"fp1">;
159 def FP2 : Register<"fp2">;
160 def FP3 : Register<"fp3">;
161 def FP4 : Register<"fp4">;
162 def FP5 : Register<"fp5">;
163 def FP6 : Register<"fp6">;
165 // XMM Registers, used by the various SSE instruction set extensions.
166 // The sub_ss and sub_sd subregs are the same registers with another regclass.
167 let CompositeIndices = [(sub_ss), (sub_sd)] in {
168 def XMM0: Register<"xmm0">, DwarfRegNum<[17, 21, 21]>;
169 def XMM1: Register<"xmm1">, DwarfRegNum<[18, 22, 22]>;
170 def XMM2: Register<"xmm2">, DwarfRegNum<[19, 23, 23]>;
171 def XMM3: Register<"xmm3">, DwarfRegNum<[20, 24, 24]>;
172 def XMM4: Register<"xmm4">, DwarfRegNum<[21, 25, 25]>;
173 def XMM5: Register<"xmm5">, DwarfRegNum<[22, 26, 26]>;
174 def XMM6: Register<"xmm6">, DwarfRegNum<[23, 27, 27]>;
175 def XMM7: Register<"xmm7">, DwarfRegNum<[24, 28, 28]>;
178 let CostPerUse = 1 in {
179 def XMM8: Register<"xmm8">, DwarfRegNum<[25, -2, -2]>;
180 def XMM9: Register<"xmm9">, DwarfRegNum<[26, -2, -2]>;
181 def XMM10: Register<"xmm10">, DwarfRegNum<[27, -2, -2]>;
182 def XMM11: Register<"xmm11">, DwarfRegNum<[28, -2, -2]>;
183 def XMM12: Register<"xmm12">, DwarfRegNum<[29, -2, -2]>;
184 def XMM13: Register<"xmm13">, DwarfRegNum<[30, -2, -2]>;
185 def XMM14: Register<"xmm14">, DwarfRegNum<[31, -2, -2]>;
186 def XMM15: Register<"xmm15">, DwarfRegNum<[32, -2, -2]>;
189 // YMM Registers, used by AVX instructions
190 let SubRegIndices = [sub_xmm] in {
191 def YMM0: RegisterWithSubRegs<"ymm0", [XMM0]>, DwarfRegNum<[17, 21, 21]>;
192 def YMM1: RegisterWithSubRegs<"ymm1", [XMM1]>, DwarfRegNum<[18, 22, 22]>;
193 def YMM2: RegisterWithSubRegs<"ymm2", [XMM2]>, DwarfRegNum<[19, 23, 23]>;
194 def YMM3: RegisterWithSubRegs<"ymm3", [XMM3]>, DwarfRegNum<[20, 24, 24]>;
195 def YMM4: RegisterWithSubRegs<"ymm4", [XMM4]>, DwarfRegNum<[21, 25, 25]>;
196 def YMM5: RegisterWithSubRegs<"ymm5", [XMM5]>, DwarfRegNum<[22, 26, 26]>;
197 def YMM6: RegisterWithSubRegs<"ymm6", [XMM6]>, DwarfRegNum<[23, 27, 27]>;
198 def YMM7: RegisterWithSubRegs<"ymm7", [XMM7]>, DwarfRegNum<[24, 28, 28]>;
199 def YMM8: RegisterWithSubRegs<"ymm8", [XMM8]>, DwarfRegNum<[25, -2, -2]>;
200 def YMM9: RegisterWithSubRegs<"ymm9", [XMM9]>, DwarfRegNum<[26, -2, -2]>;
201 def YMM10: RegisterWithSubRegs<"ymm10", [XMM10]>, DwarfRegNum<[27, -2, -2]>;
202 def YMM11: RegisterWithSubRegs<"ymm11", [XMM11]>, DwarfRegNum<[28, -2, -2]>;
203 def YMM12: RegisterWithSubRegs<"ymm12", [XMM12]>, DwarfRegNum<[29, -2, -2]>;
204 def YMM13: RegisterWithSubRegs<"ymm13", [XMM13]>, DwarfRegNum<[30, -2, -2]>;
205 def YMM14: RegisterWithSubRegs<"ymm14", [XMM14]>, DwarfRegNum<[31, -2, -2]>;
206 def YMM15: RegisterWithSubRegs<"ymm15", [XMM15]>, DwarfRegNum<[32, -2, -2]>;
209 // Floating point stack registers
210 def ST0 : Register<"st(0)">, DwarfRegNum<[33, 12, 11]>;
211 def ST1 : Register<"st(1)">, DwarfRegNum<[34, 13, 12]>;
212 def ST2 : Register<"st(2)">, DwarfRegNum<[35, 14, 13]>;
213 def ST3 : Register<"st(3)">, DwarfRegNum<[36, 15, 14]>;
214 def ST4 : Register<"st(4)">, DwarfRegNum<[37, 16, 15]>;
215 def ST5 : Register<"st(5)">, DwarfRegNum<[38, 17, 16]>;
216 def ST6 : Register<"st(6)">, DwarfRegNum<[39, 18, 17]>;
217 def ST7 : Register<"st(7)">, DwarfRegNum<[40, 19, 18]>;
219 // Status flags register
220 def EFLAGS : Register<"flags">;
223 def CS : Register<"cs">;
224 def DS : Register<"ds">;
225 def SS : Register<"ss">;
226 def ES : Register<"es">;
227 def FS : Register<"fs">;
228 def GS : Register<"gs">;
231 def DR0 : Register<"dr0">;
232 def DR1 : Register<"dr1">;
233 def DR2 : Register<"dr2">;
234 def DR3 : Register<"dr3">;
235 def DR4 : Register<"dr4">;
236 def DR5 : Register<"dr5">;
237 def DR6 : Register<"dr6">;
238 def DR7 : Register<"dr7">;
241 def CR0 : Register<"cr0">;
242 def CR1 : Register<"cr1">;
243 def CR2 : Register<"cr2">;
244 def CR3 : Register<"cr3">;
245 def CR4 : Register<"cr4">;
246 def CR5 : Register<"cr5">;
247 def CR6 : Register<"cr6">;
248 def CR7 : Register<"cr7">;
249 def CR8 : Register<"cr8">;
250 def CR9 : Register<"cr9">;
251 def CR10 : Register<"cr10">;
252 def CR11 : Register<"cr11">;
253 def CR12 : Register<"cr12">;
254 def CR13 : Register<"cr13">;
255 def CR14 : Register<"cr14">;
256 def CR15 : Register<"cr15">;
258 // Pseudo index registers
259 def EIZ : Register<"eiz">;
260 def RIZ : Register<"riz">;
264 //===----------------------------------------------------------------------===//
265 // Register Class Definitions... now that we have all of the pieces, define the
266 // top-level register classes. The order specified in the register list is
267 // implicitly defined to be the register allocation order.
270 // List call-clobbered registers before callee-save registers. RBX, RBP, (and
271 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
272 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
274 // Allocate R12 and R13 last, as these require an extra byte when
275 // encoded in x86_64 instructions.
276 // FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in
277 // 64-bit mode. The main complication is that they cannot be encoded in an
278 // instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc.
279 // require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d"
280 // cannot be encoded.
281 def GR8 : RegisterClass<"X86", [i8], 8,
282 [AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
283 R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B]> {
284 let MethodProtos = [{
285 iterator allocation_order_begin(const MachineFunction &MF) const;
286 iterator allocation_order_end(const MachineFunction &MF) const;
288 let MethodBodies = [{
289 static const unsigned X86_GR8_AO_64[] = {
290 X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
291 X86::R8B, X86::R9B, X86::R10B, X86::R11B,
292 X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL
296 GR8Class::allocation_order_begin(const MachineFunction &MF) const {
297 const TargetMachine &TM = MF.getTarget();
298 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
299 if (Subtarget.is64Bit())
300 return X86_GR8_AO_64;
306 GR8Class::allocation_order_end(const MachineFunction &MF) const {
307 const TargetMachine &TM = MF.getTarget();
308 const TargetFrameLowering *TFI = TM.getFrameLowering();
309 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
310 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
311 // Does the function dedicate RBP / EBP to being a frame ptr?
312 if (!Subtarget.is64Bit())
313 // In 32-mode, none of the 8-bit registers aliases EBP or ESP.
315 else if (TFI->hasFP(MF) || MFI->getReserveFP())
316 // If so, don't allocate SPL or BPL.
317 return array_endof(X86_GR8_AO_64) - 1;
319 // If not, just don't allocate SPL.
320 return array_endof(X86_GR8_AO_64);
325 def GR16 : RegisterClass<"X86", [i16], 16,
326 [AX, CX, DX, SI, DI, BX, BP, SP,
327 R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W]> {
328 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi)];
329 let MethodProtos = [{
330 iterator allocation_order_begin(const MachineFunction &MF) const;
331 iterator allocation_order_end(const MachineFunction &MF) const;
333 let MethodBodies = [{
334 static const unsigned X86_GR16_AO_64[] = {
335 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
336 X86::R8W, X86::R9W, X86::R10W, X86::R11W,
337 X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::BP
341 GR16Class::allocation_order_begin(const MachineFunction &MF) const {
342 const TargetMachine &TM = MF.getTarget();
343 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
344 if (Subtarget.is64Bit())
345 return X86_GR16_AO_64;
351 GR16Class::allocation_order_end(const MachineFunction &MF) const {
352 const TargetMachine &TM = MF.getTarget();
353 const TargetFrameLowering *TFI = TM.getFrameLowering();
354 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
355 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
356 if (Subtarget.is64Bit()) {
357 // Does the function dedicate RBP to being a frame ptr?
358 if (TFI->hasFP(MF) || MFI->getReserveFP())
359 // If so, don't allocate SP or BP.
360 return array_endof(X86_GR16_AO_64) - 1;
362 // If not, just don't allocate SP.
363 return array_endof(X86_GR16_AO_64);
365 // Does the function dedicate EBP to being a frame ptr?
366 if (TFI->hasFP(MF) || MFI->getReserveFP())
367 // If so, don't allocate SP or BP.
370 // If not, just don't allocate SP.
377 def GR32 : RegisterClass<"X86", [i32], 32,
378 [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
379 R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> {
380 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)];
381 let MethodProtos = [{
382 iterator allocation_order_begin(const MachineFunction &MF) const;
383 iterator allocation_order_end(const MachineFunction &MF) const;
385 let MethodBodies = [{
386 static const unsigned X86_GR32_AO_64[] = {
387 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
388 X86::R8D, X86::R9D, X86::R10D, X86::R11D,
389 X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP
393 GR32Class::allocation_order_begin(const MachineFunction &MF) const {
394 const TargetMachine &TM = MF.getTarget();
395 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
396 if (Subtarget.is64Bit())
397 return X86_GR32_AO_64;
403 GR32Class::allocation_order_end(const MachineFunction &MF) const {
404 const TargetMachine &TM = MF.getTarget();
405 const TargetFrameLowering *TFI = TM.getFrameLowering();
406 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
407 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
408 if (Subtarget.is64Bit()) {
409 // Does the function dedicate RBP to being a frame ptr?
410 if (TFI->hasFP(MF) || MFI->getReserveFP())
411 // If so, don't allocate ESP or EBP.
412 return array_endof(X86_GR32_AO_64) - 1;
414 // If not, just don't allocate ESP.
415 return array_endof(X86_GR32_AO_64);
417 // Does the function dedicate EBP to being a frame ptr?
418 if (TFI->hasFP(MF) || MFI->getReserveFP())
419 // If so, don't allocate ESP or EBP.
422 // If not, just don't allocate ESP.
429 // GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
430 // RIP isn't really a register and it can't be used anywhere except in an
431 // address, but it doesn't cause trouble.
432 def GR64 : RegisterClass<"X86", [i64], 64,
433 [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
434 RBX, R14, R15, R12, R13, RBP, RSP, RIP]> {
435 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi),
438 let MethodProtos = [{
439 iterator allocation_order_end(const MachineFunction &MF) const;
441 let MethodBodies = [{
443 GR64Class::allocation_order_end(const MachineFunction &MF) const {
444 const TargetMachine &TM = MF.getTarget();
445 const TargetFrameLowering *TFI = TM.getFrameLowering();
446 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
447 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
448 if (!Subtarget.is64Bit())
449 return begin(); // None of these are allocatable in 32-bit.
450 // Does the function dedicate RBP to being a frame ptr?
451 if (TFI->hasFP(MF) || MFI->getReserveFP())
452 return end()-3; // If so, don't allocate RIP, RSP or RBP
454 return end()-2; // If not, just don't allocate RIP or RSP
459 // Segment registers for use by MOV instructions (and others) that have a
460 // segment register as one operand. Always contain a 16-bit segment
462 def SEGMENT_REG : RegisterClass<"X86", [i16], 16, [CS, DS, SS, ES, FS, GS]>;
465 def DEBUG_REG : RegisterClass<"X86", [i32], 32,
466 [DR0, DR1, DR2, DR3, DR4, DR5, DR6, DR7]>;
468 // Control registers.
469 def CONTROL_REG : RegisterClass<"X86", [i64], 64,
470 [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7, CR8,
471 CR9, CR10, CR11, CR12, CR13, CR14, CR15]>;
473 // GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of
474 // GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d"
475 // registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers
476 // that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD,
477 // and GR64_ABCD are classes for registers that support 8-bit h-register
479 def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL]>;
480 def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, [AH, CH, DH, BH]>;
481 def GR16_ABCD : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
482 let SubRegClasses = [(GR8_ABCD_L sub_8bit), (GR8_ABCD_H sub_8bit_hi)];
484 def GR32_ABCD : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
485 let SubRegClasses = [(GR8_ABCD_L sub_8bit),
486 (GR8_ABCD_H sub_8bit_hi),
487 (GR16_ABCD sub_16bit)];
489 def GR64_ABCD : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RBX]> {
490 let SubRegClasses = [(GR8_ABCD_L sub_8bit),
491 (GR8_ABCD_H sub_8bit_hi),
492 (GR16_ABCD sub_16bit),
493 (GR32_ABCD sub_32bit)];
495 def GR32_TC : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX]> {
496 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)];
498 def GR64_TC : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RSI, RDI,
500 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi),
502 (GR32_TC sub_32bit)];
505 def GR64_TCW64 : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX,
508 // GR8_NOREX - GR8 registers which do not require a REX prefix.
509 def GR8_NOREX : RegisterClass<"X86", [i8], 8,
510 [AL, CL, DL, AH, CH, DH, BL, BH]> {
511 let MethodProtos = [{
512 iterator allocation_order_begin(const MachineFunction &MF) const;
513 iterator allocation_order_end(const MachineFunction &MF) const;
515 let MethodBodies = [{
516 // In 64-bit mode, it's not safe to blindly allocate H registers.
517 static const unsigned X86_GR8_NOREX_AO_64[] = {
518 X86::AL, X86::CL, X86::DL, X86::BL
521 GR8_NOREXClass::iterator
522 GR8_NOREXClass::allocation_order_begin(const MachineFunction &MF) const {
523 const TargetMachine &TM = MF.getTarget();
524 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
525 if (Subtarget.is64Bit())
526 return X86_GR8_NOREX_AO_64;
531 GR8_NOREXClass::iterator
532 GR8_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
533 const TargetMachine &TM = MF.getTarget();
534 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
535 if (Subtarget.is64Bit())
536 return array_endof(X86_GR8_NOREX_AO_64);
542 // GR16_NOREX - GR16 registers which do not require a REX prefix.
543 def GR16_NOREX : RegisterClass<"X86", [i16], 16,
544 [AX, CX, DX, SI, DI, BX, BP, SP]> {
545 let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi)];
546 let MethodProtos = [{
547 iterator allocation_order_end(const MachineFunction &MF) const;
549 let MethodBodies = [{
550 GR16_NOREXClass::iterator
551 GR16_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
552 const TargetMachine &TM = MF.getTarget();
553 const TargetFrameLowering *TFI = TM.getFrameLowering();
554 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
555 // Does the function dedicate RBP / EBP to being a frame ptr?
556 if (TFI->hasFP(MF) || MFI->getReserveFP())
557 // If so, don't allocate SP or BP.
560 // If not, just don't allocate SP.
565 // GR32_NOREX - GR32 registers which do not require a REX prefix.
566 def GR32_NOREX : RegisterClass<"X86", [i32], 32,
567 [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
568 let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi),
569 (GR16_NOREX sub_16bit)];
570 let MethodProtos = [{
571 iterator allocation_order_end(const MachineFunction &MF) const;
573 let MethodBodies = [{
574 GR32_NOREXClass::iterator
575 GR32_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
576 const TargetMachine &TM = MF.getTarget();
577 const TargetFrameLowering *TFI = TM.getFrameLowering();
578 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
579 // Does the function dedicate RBP / EBP to being a frame ptr?
580 if (TFI->hasFP(MF) || MFI->getReserveFP())
581 // If so, don't allocate ESP or EBP.
584 // If not, just don't allocate ESP.
589 // GR64_NOREX - GR64 registers which do not require a REX prefix.
590 def GR64_NOREX : RegisterClass<"X86", [i64], 64,
591 [RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP]> {
592 let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi),
593 (GR16_NOREX sub_16bit),
594 (GR32_NOREX sub_32bit)];
595 let MethodProtos = [{
596 iterator allocation_order_end(const MachineFunction &MF) const;
598 let MethodBodies = [{
599 GR64_NOREXClass::iterator
600 GR64_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
601 const TargetMachine &TM = MF.getTarget();
602 const TargetFrameLowering *TFI = TM.getFrameLowering();
603 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
604 // Does the function dedicate RBP to being a frame ptr?
605 if (TFI->hasFP(MF) || MFI->getReserveFP())
606 // If so, don't allocate RIP, RSP or RBP.
609 // If not, just don't allocate RIP or RSP.
615 // GR32_NOSP - GR32 registers except ESP.
616 def GR32_NOSP : RegisterClass<"X86", [i32], 32,
617 [EAX, ECX, EDX, ESI, EDI, EBX, EBP,
618 R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> {
619 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)];
620 let MethodProtos = [{
621 iterator allocation_order_begin(const MachineFunction &MF) const;
622 iterator allocation_order_end(const MachineFunction &MF) const;
624 let MethodBodies = [{
625 static const unsigned X86_GR32_NOSP_AO_64[] = {
626 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
627 X86::R8D, X86::R9D, X86::R10D, X86::R11D,
628 X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP
631 GR32_NOSPClass::iterator
632 GR32_NOSPClass::allocation_order_begin(const MachineFunction &MF) const {
633 const TargetMachine &TM = MF.getTarget();
634 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
635 if (Subtarget.is64Bit())
636 return X86_GR32_NOSP_AO_64;
641 GR32_NOSPClass::iterator
642 GR32_NOSPClass::allocation_order_end(const MachineFunction &MF) const {
643 const TargetMachine &TM = MF.getTarget();
644 const TargetFrameLowering *TFI = TM.getFrameLowering();
645 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
646 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
647 if (Subtarget.is64Bit()) {
648 // Does the function dedicate RBP to being a frame ptr?
649 if (TFI->hasFP(MF) || MFI->getReserveFP())
650 // If so, don't allocate EBP.
651 return array_endof(X86_GR32_NOSP_AO_64) - 1;
653 // If not, any reg in this class is ok.
654 return array_endof(X86_GR32_NOSP_AO_64);
656 // Does the function dedicate EBP to being a frame ptr?
657 if (TFI->hasFP(MF) || MFI->getReserveFP())
658 // If so, don't allocate EBP.
661 // If not, any reg in this class is ok.
668 // GR64_NOSP - GR64 registers except RSP (and RIP).
669 def GR64_NOSP : RegisterClass<"X86", [i64], 64,
670 [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
671 RBX, R14, R15, R12, R13, RBP]> {
672 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi),
674 (GR32_NOSP sub_32bit)];
675 let MethodProtos = [{
676 iterator allocation_order_end(const MachineFunction &MF) const;
678 let MethodBodies = [{
679 GR64_NOSPClass::iterator
680 GR64_NOSPClass::allocation_order_end(const MachineFunction &MF) const {
681 const TargetMachine &TM = MF.getTarget();
682 const TargetFrameLowering *TFI = TM.getFrameLowering();
683 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
684 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
685 if (!Subtarget.is64Bit())
686 return begin(); // None of these are allocatable in 32-bit.
687 // Does the function dedicate RBP to being a frame ptr?
688 if (TFI->hasFP(MF) || MFI->getReserveFP())
689 return end()-1; // If so, don't allocate RBP
691 return end(); // If not, any reg in this class is ok.
696 // GR64_NOREX_NOSP - GR64_NOREX registers except RSP.
697 def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64,
698 [RAX, RCX, RDX, RSI, RDI, RBX, RBP]> {
699 let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi),
700 (GR16_NOREX sub_16bit),
701 (GR32_NOREX sub_32bit)];
702 let MethodProtos = [{
703 iterator allocation_order_end(const MachineFunction &MF) const;
705 let MethodBodies = [{
706 GR64_NOREX_NOSPClass::iterator
707 GR64_NOREX_NOSPClass::allocation_order_end(const MachineFunction &MF) const
709 const TargetMachine &TM = MF.getTarget();
710 const TargetFrameLowering *TFI = TM.getFrameLowering();
711 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
712 // Does the function dedicate RBP to being a frame ptr?
713 if (TFI->hasFP(MF) || MFI->getReserveFP())
714 // If so, don't allocate RBP.
717 // If not, any reg in this class is ok.
723 // A class to support the 'A' assembler constraint: EAX then EDX.
724 def GR32_AD : RegisterClass<"X86", [i32], 32, [EAX, EDX]> {
725 let SubRegClasses = [(GR8_ABCD_L sub_8bit),
726 (GR8_ABCD_H sub_8bit_hi),
727 (GR16_ABCD sub_16bit)];
730 // Scalar SSE2 floating point registers.
731 def FR32 : RegisterClass<"X86", [f32], 32,
732 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
733 XMM8, XMM9, XMM10, XMM11,
734 XMM12, XMM13, XMM14, XMM15]> {
735 let MethodProtos = [{
736 iterator allocation_order_end(const MachineFunction &MF) const;
738 let MethodBodies = [{
740 FR32Class::allocation_order_end(const MachineFunction &MF) const {
741 const TargetMachine &TM = MF.getTarget();
742 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
743 if (!Subtarget.is64Bit())
744 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
751 def FR64 : RegisterClass<"X86", [f64], 64,
752 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
753 XMM8, XMM9, XMM10, XMM11,
754 XMM12, XMM13, XMM14, XMM15]> {
755 let MethodProtos = [{
756 iterator allocation_order_end(const MachineFunction &MF) const;
758 let MethodBodies = [{
760 FR64Class::allocation_order_end(const MachineFunction &MF) const {
761 const TargetMachine &TM = MF.getTarget();
762 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
763 if (!Subtarget.is64Bit())
764 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
772 // FIXME: This sets up the floating point register files as though they are f64
773 // values, though they really are f80 values. This will cause us to spill
774 // values as 64-bit quantities instead of 80-bit quantities, which is much much
775 // faster on common hardware. In reality, this should be controlled by a
776 // command line option or something.
778 def RFP32 : RegisterClass<"X86",[f32], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
779 def RFP64 : RegisterClass<"X86",[f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
780 def RFP80 : RegisterClass<"X86",[f80], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
782 // Floating point stack registers (these are not allocatable by the
783 // register allocator - the floating point stackifier is responsible
784 // for transforming FPn allocations to STn registers)
785 def RST : RegisterClass<"X86", [f80, f64, f32], 32,
786 [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
787 let MethodProtos = [{
788 iterator allocation_order_end(const MachineFunction &MF) const;
790 let MethodBodies = [{
792 RSTClass::allocation_order_end(const MachineFunction &MF) const {
798 // Generic vector registers: VR64 and VR128.
799 def VR64: RegisterClass<"X86", [x86mmx], 64,
800 [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
801 def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128,
802 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
803 XMM8, XMM9, XMM10, XMM11,
804 XMM12, XMM13, XMM14, XMM15]> {
805 let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd)];
807 let MethodProtos = [{
808 iterator allocation_order_end(const MachineFunction &MF) const;
810 let MethodBodies = [{
812 VR128Class::allocation_order_end(const MachineFunction &MF) const {
813 const TargetMachine &TM = MF.getTarget();
814 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
815 if (!Subtarget.is64Bit())
816 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
823 def VR256 : RegisterClass<"X86", [v32i8, v8i32, v4i64, v8f32, v4f64], 256,
824 [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
825 YMM8, YMM9, YMM10, YMM11,
826 YMM12, YMM13, YMM14, YMM15]> {
827 let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd), (VR128 sub_xmm)];
829 let MethodProtos = [{
830 iterator allocation_order_end(const MachineFunction &MF) const;
832 let MethodBodies = [{
834 VR256Class::allocation_order_end(const MachineFunction &MF) const {
835 const TargetMachine &TM = MF.getTarget();
836 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
837 if (!Subtarget.is64Bit())
838 return end()-8; // Only YMM0 to YMM7 are available in 32-bit mode.
845 // Status flags registers.
846 def CCR : RegisterClass<"X86", [i32], 32, [EFLAGS]> {
847 let CopyCost = -1; // Don't allow copying of status registers.
849 // EFLAGS is not allocatable.
850 let MethodProtos = [{
851 iterator allocation_order_end(const MachineFunction &MF) const;
853 let MethodBodies = [{
855 CCRClass::allocation_order_end(const MachineFunction &MF) const {
856 return allocation_order_begin(MF);