1 //===- X86RegisterInfo.td - Describe the X86 Register File ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 Register file, defining the registers themselves,
11 // aliases between the registers, and the register classes built out of the
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Register definitions...
19 let Namespace = "X86" in {
21 // In the register alias definitions below, we define which registers alias
22 // which others. We only specify which registers the small registers alias,
23 // because the register file generator is smart enough to figure out that
24 // AL aliases AX if we tell it that AX aliased AL (for example).
27 def EAX : Register<"EAX">; def ECX : Register<"ECX">;
28 def EDX : Register<"EDX">; def EBX : Register<"EBX">;
29 def ESP : Register<"ESP">; def EBP : Register<"EBP">;
30 def ESI : Register<"ESI">; def EDI : Register<"EDI">;
33 def AX : RegisterGroup<"AX", [EAX]>; def CX : RegisterGroup<"CX", [ECX]>;
34 def DX : RegisterGroup<"DX", [EDX]>; def BX : RegisterGroup<"BX", [EBX]>;
35 def SP : RegisterGroup<"SP", [ESP]>; def BP : RegisterGroup<"BP", [EBP]>;
36 def SI : RegisterGroup<"SI", [ESI]>; def DI : RegisterGroup<"DI", [EDI]>;
39 def AL : RegisterGroup<"AL", [AX,EAX]>; def CL : RegisterGroup<"CL",[CX,ECX]>;
40 def DL : RegisterGroup<"DL", [DX,EDX]>; def BL : RegisterGroup<"BL",[BX,EBX]>;
41 def AH : RegisterGroup<"AH", [AX,EAX]>; def CH : RegisterGroup<"CH",[CX,ECX]>;
42 def DH : RegisterGroup<"DH", [DX,EDX]>; def BH : RegisterGroup<"BH",[BX,EBX]>;
44 // Pseudo Floating Point registers
45 def FP0 : Register<"FP0">; def FP1 : Register<"FP1">;
46 def FP2 : Register<"FP2">; def FP3 : Register<"FP3">;
47 def FP4 : Register<"FP4">; def FP5 : Register<"FP5">;
48 def FP6 : Register<"FP6">;
50 // Floating point stack registers
51 def ST0 : Register<"ST(0)">; def ST1 : Register<"ST(1)">;
52 def ST2 : Register<"ST(2)">; def ST3 : Register<"ST(3)">;
53 def ST4 : Register<"ST(4)">; def ST5 : Register<"ST(5)">;
54 def ST6 : Register<"ST(6)">; def ST7 : Register<"ST(7)">;
56 // Flags, Segment registers, etc...
59 //===----------------------------------------------------------------------===//
60 // Register Class Definitions... now that we have all of the pieces, define the
61 // top-level register classes. The order specified in the register list is
62 // implicitly defined to be the register allocation order.
64 def R8 : RegisterClass<i8, 8, [AL, AH, CL, CH, DL, DH, BL, BH]>;
65 def R16 : RegisterClass<i16, 16, [AX, CX, DX, SI, DI, BX, BP, SP]> {
67 iterator allocation_order_end(MachineFunction &MF) const {
68 if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
69 return end()-2; // If so, don't allocate SP or BP
71 return end()-1; // If not, just don't allocate SP
76 def R32 : RegisterClass<i32, 32, [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
78 iterator allocation_order_end(MachineFunction &MF) const {
79 if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
80 return end()-2; // If so, don't allocate ESP or EBP
82 return end()-1; // If not, just don't allocate ESP
87 def RFP : RegisterClass<f80, 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
89 // Floating point stack registers (these are not allocatable by the
90 // register allocator - the floating point stackifier is responsible
91 // for transforming FPn allocations to STn registers)
92 def RST : RegisterClass<f80, 32, [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
94 iterator allocation_order_end(MachineFunction &MF) const {