1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 Register file, defining the registers themselves,
11 // aliases between the registers, and the register classes built out of the
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Register definitions...
19 let Namespace = "X86" in {
21 // In the register alias definitions below, we define which registers alias
22 // which others. We only specify which registers the small registers alias,
23 // because the register file generator is smart enough to figure out that
24 // AL aliases AX if we tell it that AX aliased AL (for example).
26 // Dwarf numbering is different for 32-bit and 64-bit, and there are
27 // variations by target as well. Currently the first entry is for X86-64,
28 // second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux
29 // and debug information on X86-32/Darwin)
33 def AL : Register<"AL">, DwarfRegNum<[0, 0, 0]>;
34 def DL : Register<"DL">, DwarfRegNum<[1, 2, 2]>;
35 def CL : Register<"CL">, DwarfRegNum<[2, 1, 1]>;
36 def BL : Register<"BL">, DwarfRegNum<[3, 3, 3]>;
39 def SIL : Register<"SIL">, DwarfRegNum<[4, 6, 6]>;
40 def DIL : Register<"DIL">, DwarfRegNum<[5, 7, 7]>;
41 def BPL : Register<"BPL">, DwarfRegNum<[6, 4, 5]>;
42 def SPL : Register<"SPL">, DwarfRegNum<[7, 5, 4]>;
43 def R8B : Register<"R8B">, DwarfRegNum<[8, -2, -2]>;
44 def R9B : Register<"R9B">, DwarfRegNum<[9, -2, -2]>;
45 def R10B : Register<"R10B">, DwarfRegNum<[10, -2, -2]>;
46 def R11B : Register<"R11B">, DwarfRegNum<[11, -2, -2]>;
47 def R12B : Register<"R12B">, DwarfRegNum<[12, -2, -2]>;
48 def R13B : Register<"R13B">, DwarfRegNum<[13, -2, -2]>;
49 def R14B : Register<"R14B">, DwarfRegNum<[14, -2, -2]>;
50 def R15B : Register<"R15B">, DwarfRegNum<[15, -2, -2]>;
52 // High registers X86-32 only
53 def AH : Register<"AH">, DwarfRegNum<[0, 0, 0]>;
54 def DH : Register<"DH">, DwarfRegNum<[1, 2, 2]>;
55 def CH : Register<"CH">, DwarfRegNum<[2, 1, 1]>;
56 def BH : Register<"BH">, DwarfRegNum<[3, 3, 3]>;
59 def AX : RegisterWithSubRegs<"AX", [AH,AL]>, DwarfRegNum<[0, 0, 0]>;
60 def DX : RegisterWithSubRegs<"DX", [DH,DL]>, DwarfRegNum<[1, 2, 2]>;
61 def CX : RegisterWithSubRegs<"CX", [CH,CL]>, DwarfRegNum<[2, 1, 1]>;
62 def BX : RegisterWithSubRegs<"BX", [BH,BL]>, DwarfRegNum<[3, 3, 3]>;
63 def SI : RegisterWithSubRegs<"SI", [SIL]>, DwarfRegNum<[4, 6, 6]>;
64 def DI : RegisterWithSubRegs<"DI", [DIL]>, DwarfRegNum<[5, 7, 7]>;
65 def BP : RegisterWithSubRegs<"BP", [BPL]>, DwarfRegNum<[6, 4, 5]>;
66 def SP : RegisterWithSubRegs<"SP", [SPL]>, DwarfRegNum<[7, 5, 4]>;
67 def IP : Register<"IP">, DwarfRegNum<[16]>;
70 def R8W : RegisterWithSubRegs<"R8W", [R8B]>, DwarfRegNum<[8, -2, -2]>;
71 def R9W : RegisterWithSubRegs<"R9W", [R9B]>, DwarfRegNum<[9, -2, -2]>;
72 def R10W : RegisterWithSubRegs<"R10W", [R10B]>, DwarfRegNum<[10, -2, -2]>;
73 def R11W : RegisterWithSubRegs<"R11W", [R11B]>, DwarfRegNum<[11, -2, -2]>;
74 def R12W : RegisterWithSubRegs<"R12W", [R12B]>, DwarfRegNum<[12, -2, -2]>;
75 def R13W : RegisterWithSubRegs<"R13W", [R13B]>, DwarfRegNum<[13, -2, -2]>;
76 def R14W : RegisterWithSubRegs<"R14W", [R14B]>, DwarfRegNum<[14, -2, -2]>;
77 def R15W : RegisterWithSubRegs<"R15W", [R15B]>, DwarfRegNum<[15, -2, -2]>;
80 def EAX : RegisterWithSubRegs<"EAX", [AX]>, DwarfRegNum<[0, 0, 0]>;
81 def EDX : RegisterWithSubRegs<"EDX", [DX]>, DwarfRegNum<[1, 2, 2]>;
82 def ECX : RegisterWithSubRegs<"ECX", [CX]>, DwarfRegNum<[2, 1, 1]>;
83 def EBX : RegisterWithSubRegs<"EBX", [BX]>, DwarfRegNum<[3, 3, 3]>;
84 def ESI : RegisterWithSubRegs<"ESI", [SI]>, DwarfRegNum<[4, 6, 6]>;
85 def EDI : RegisterWithSubRegs<"EDI", [DI]>, DwarfRegNum<[5, 7, 7]>;
86 def EBP : RegisterWithSubRegs<"EBP", [BP]>, DwarfRegNum<[6, 4, 5]>;
87 def ESP : RegisterWithSubRegs<"ESP", [SP]>, DwarfRegNum<[7, 5, 4]>;
88 def EIP : RegisterWithSubRegs<"EIP", [IP]>, DwarfRegNum<[16, 8, 8]>;
91 def R8D : RegisterWithSubRegs<"R8D", [R8W]>, DwarfRegNum<[8, -2, -2]>;
92 def R9D : RegisterWithSubRegs<"R9D", [R9W]>, DwarfRegNum<[9, -2, -2]>;
93 def R10D : RegisterWithSubRegs<"R10D", [R10W]>, DwarfRegNum<[10, -2, -2]>;
94 def R11D : RegisterWithSubRegs<"R11D", [R11W]>, DwarfRegNum<[11, -2, -2]>;
95 def R12D : RegisterWithSubRegs<"R12D", [R12W]>, DwarfRegNum<[12, -2, -2]>;
96 def R13D : RegisterWithSubRegs<"R13D", [R13W]>, DwarfRegNum<[13, -2, -2]>;
97 def R14D : RegisterWithSubRegs<"R14D", [R14W]>, DwarfRegNum<[14, -2, -2]>;
98 def R15D : RegisterWithSubRegs<"R15D", [R15W]>, DwarfRegNum<[15, -2, -2]>;
100 // 64-bit registers, X86-64 only
101 def RAX : RegisterWithSubRegs<"RAX", [EAX]>, DwarfRegNum<[0, -2, -2]>;
102 def RDX : RegisterWithSubRegs<"RDX", [EDX]>, DwarfRegNum<[1, -2, -2]>;
103 def RCX : RegisterWithSubRegs<"RCX", [ECX]>, DwarfRegNum<[2, -2, -2]>;
104 def RBX : RegisterWithSubRegs<"RBX", [EBX]>, DwarfRegNum<[3, -2, -2]>;
105 def RSI : RegisterWithSubRegs<"RSI", [ESI]>, DwarfRegNum<[4, -2, -2]>;
106 def RDI : RegisterWithSubRegs<"RDI", [EDI]>, DwarfRegNum<[5, -2, -2]>;
107 def RBP : RegisterWithSubRegs<"RBP", [EBP]>, DwarfRegNum<[6, -2, -2]>;
108 def RSP : RegisterWithSubRegs<"RSP", [ESP]>, DwarfRegNum<[7, -2, -2]>;
110 def R8 : RegisterWithSubRegs<"R8", [R8D]>, DwarfRegNum<[8, -2, -2]>;
111 def R9 : RegisterWithSubRegs<"R9", [R9D]>, DwarfRegNum<[9, -2, -2]>;
112 def R10 : RegisterWithSubRegs<"R10", [R10D]>, DwarfRegNum<[10, -2, -2]>;
113 def R11 : RegisterWithSubRegs<"R11", [R11D]>, DwarfRegNum<[11, -2, -2]>;
114 def R12 : RegisterWithSubRegs<"R12", [R12D]>, DwarfRegNum<[12, -2, -2]>;
115 def R13 : RegisterWithSubRegs<"R13", [R13D]>, DwarfRegNum<[13, -2, -2]>;
116 def R14 : RegisterWithSubRegs<"R14", [R14D]>, DwarfRegNum<[14, -2, -2]>;
117 def R15 : RegisterWithSubRegs<"R15", [R15D]>, DwarfRegNum<[15, -2, -2]>;
118 def RIP : RegisterWithSubRegs<"RIP", [EIP]>, DwarfRegNum<[16, -2, -2]>;
120 // MMX Registers. These are actually aliased to ST0 .. ST7
121 def MM0 : Register<"MM0">, DwarfRegNum<[41, 29, 29]>;
122 def MM1 : Register<"MM1">, DwarfRegNum<[42, 30, 30]>;
123 def MM2 : Register<"MM2">, DwarfRegNum<[43, 31, 31]>;
124 def MM3 : Register<"MM3">, DwarfRegNum<[44, 32, 32]>;
125 def MM4 : Register<"MM4">, DwarfRegNum<[45, 33, 33]>;
126 def MM5 : Register<"MM5">, DwarfRegNum<[46, 34, 34]>;
127 def MM6 : Register<"MM6">, DwarfRegNum<[47, 35, 35]>;
128 def MM7 : Register<"MM7">, DwarfRegNum<[48, 36, 36]>;
130 // Pseudo Floating Point registers
131 def FP0 : Register<"FP0">;
132 def FP1 : Register<"FP1">;
133 def FP2 : Register<"FP2">;
134 def FP3 : Register<"FP3">;
135 def FP4 : Register<"FP4">;
136 def FP5 : Register<"FP5">;
137 def FP6 : Register<"FP6">;
139 // XMM Registers, used by the various SSE instruction set extensions
140 def XMM0: Register<"XMM0">, DwarfRegNum<[17, 21, 21]>;
141 def XMM1: Register<"XMM1">, DwarfRegNum<[18, 22, 22]>;
142 def XMM2: Register<"XMM2">, DwarfRegNum<[19, 23, 23]>;
143 def XMM3: Register<"XMM3">, DwarfRegNum<[20, 24, 24]>;
144 def XMM4: Register<"XMM4">, DwarfRegNum<[21, 25, 25]>;
145 def XMM5: Register<"XMM5">, DwarfRegNum<[22, 26, 26]>;
146 def XMM6: Register<"XMM6">, DwarfRegNum<[23, 27, 27]>;
147 def XMM7: Register<"XMM7">, DwarfRegNum<[24, 28, 28]>;
150 def XMM8: Register<"XMM8">, DwarfRegNum<[25, -2, -2]>;
151 def XMM9: Register<"XMM9">, DwarfRegNum<[26, -2, -2]>;
152 def XMM10: Register<"XMM10">, DwarfRegNum<[27, -2, -2]>;
153 def XMM11: Register<"XMM11">, DwarfRegNum<[28, -2, -2]>;
154 def XMM12: Register<"XMM12">, DwarfRegNum<[29, -2, -2]>;
155 def XMM13: Register<"XMM13">, DwarfRegNum<[30, -2, -2]>;
156 def XMM14: Register<"XMM14">, DwarfRegNum<[31, -2, -2]>;
157 def XMM15: Register<"XMM15">, DwarfRegNum<[32, -2, -2]>;
159 // Floating point stack registers
160 def ST0 : Register<"ST(0)">, DwarfRegNum<[33, 12, 11]>;
161 def ST1 : Register<"ST(1)">, DwarfRegNum<[34, 13, 12]>;
162 def ST2 : Register<"ST(2)">, DwarfRegNum<[35, 14, 13]>;
163 def ST3 : Register<"ST(3)">, DwarfRegNum<[36, 15, 14]>;
164 def ST4 : Register<"ST(4)">, DwarfRegNum<[37, 16, 15]>;
165 def ST5 : Register<"ST(5)">, DwarfRegNum<[38, 17, 16]>;
166 def ST6 : Register<"ST(6)">, DwarfRegNum<[39, 18, 17]>;
167 def ST7 : Register<"ST(7)">, DwarfRegNum<[40, 19, 18]>;
169 // Status flags register
170 def EFLAGS : Register<"EFLAGS">;
174 //===----------------------------------------------------------------------===//
175 // Subregister Set Definitions... now that we have all of the pieces, define the
176 // sub registers for each register.
179 def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
180 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
181 [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
182 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
184 // It's unclear if this subreg set is safe, given that not all registers
185 // in the class have an 'H' subreg.
186 // def : SubRegSet<2, [AX, CX, DX, BX],
187 // [AH, CH, DH, BH]>;
189 def : SubRegSet<1, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
190 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
191 [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
192 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
194 def : SubRegSet<2, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
195 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
196 [AX, CX, DX, BX, SP, BP, SI, DI,
197 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
200 def : SubRegSet<1, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
201 R8, R9, R10, R11, R12, R13, R14, R15],
202 [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
203 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
205 def : SubRegSet<2, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
206 R8, R9, R10, R11, R12, R13, R14, R15],
207 [AX, CX, DX, BX, SP, BP, SI, DI,
208 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
210 def : SubRegSet<3, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
211 R8, R9, R10, R11, R12, R13, R14, R15],
212 [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
213 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]>;
215 //===----------------------------------------------------------------------===//
216 // Register Class Definitions... now that we have all of the pieces, define the
217 // top-level register classes. The order specified in the register list is
218 // implicitly defined to be the register allocation order.
221 // List call-clobbered registers before callee-save registers. RBX, RBP, (and
222 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
223 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
225 // FIXME: Allow AH, CH, DH, BH in 64-mode for non-REX instructions,
226 def GR8 : RegisterClass<"X86", [i8], 8,
227 [AL, CL, DL, BL, AH, CH, DH, BH, SIL, DIL, BPL, SPL,
228 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]> {
229 let MethodProtos = [{
230 iterator allocation_order_begin(const MachineFunction &MF) const;
231 iterator allocation_order_end(const MachineFunction &MF) const;
233 let MethodBodies = [{
234 // Does the function dedicate RBP / EBP to being a frame ptr?
235 // If so, don't allocate SPL or BPL.
236 static const unsigned X86_GR8_AO_64_fp[] =
237 {X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
238 X86::R8B, X86::R9B, X86::R10B, X86::R11B,
239 X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B};
240 // If not, just don't allocate SPL.
241 static const unsigned X86_GR8_AO_64[] =
242 {X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
243 X86::R8B, X86::R9B, X86::R10B, X86::R11B,
244 X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL};
245 // In 32-mode, none of the 8-bit registers aliases EBP or ESP.
246 static const unsigned X86_GR8_AO_32[] =
247 {X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH};
250 GR8Class::allocation_order_begin(const MachineFunction &MF) const {
251 const TargetMachine &TM = MF.getTarget();
252 const TargetRegisterInfo *RI = TM.getRegisterInfo();
253 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
254 if (!Subtarget.is64Bit())
255 return X86_GR8_AO_32;
256 else if (RI->hasFP(MF))
257 return X86_GR8_AO_64_fp;
259 return X86_GR8_AO_64;
263 GR8Class::allocation_order_end(const MachineFunction &MF) const {
264 const TargetMachine &TM = MF.getTarget();
265 const TargetRegisterInfo *RI = TM.getRegisterInfo();
266 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
267 if (!Subtarget.is64Bit())
268 return X86_GR8_AO_32 + (sizeof(X86_GR8_AO_32) / sizeof(unsigned));
269 else if (RI->hasFP(MF))
270 return X86_GR8_AO_64_fp + (sizeof(X86_GR8_AO_64_fp) / sizeof(unsigned));
272 return X86_GR8_AO_64 + (sizeof(X86_GR8_AO_64) / sizeof(unsigned));
278 def GR16 : RegisterClass<"X86", [i16], 16,
279 [AX, CX, DX, SI, DI, BX, BP, SP,
280 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]> {
281 let SubRegClassList = [GR8];
282 let MethodProtos = [{
283 iterator allocation_order_begin(const MachineFunction &MF) const;
284 iterator allocation_order_end(const MachineFunction &MF) const;
286 let MethodBodies = [{
287 // Does the function dedicate RBP / EBP to being a frame ptr?
288 // If so, don't allocate SP or BP.
289 static const unsigned X86_GR16_AO_64_fp[] =
290 {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
291 X86::R8W, X86::R9W, X86::R10W, X86::R11W,
292 X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W};
293 static const unsigned X86_GR16_AO_32_fp[] =
294 {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX};
295 // If not, just don't allocate SPL.
296 static const unsigned X86_GR16_AO_64[] =
297 {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
298 X86::R8W, X86::R9W, X86::R10W, X86::R11W,
299 X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::BP};
300 static const unsigned X86_GR16_AO_32[] =
301 {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP};
304 GR16Class::allocation_order_begin(const MachineFunction &MF) const {
305 const TargetMachine &TM = MF.getTarget();
306 const TargetRegisterInfo *RI = TM.getRegisterInfo();
307 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
308 if (Subtarget.is64Bit()) {
310 return X86_GR16_AO_64_fp;
312 return X86_GR16_AO_64;
315 return X86_GR16_AO_32_fp;
317 return X86_GR16_AO_32;
322 GR16Class::allocation_order_end(const MachineFunction &MF) const {
323 const TargetMachine &TM = MF.getTarget();
324 const TargetRegisterInfo *RI = TM.getRegisterInfo();
325 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
326 if (Subtarget.is64Bit()) {
328 return X86_GR16_AO_64_fp+(sizeof(X86_GR16_AO_64_fp)/sizeof(unsigned));
330 return X86_GR16_AO_64 + (sizeof(X86_GR16_AO_64) / sizeof(unsigned));
333 return X86_GR16_AO_32_fp+(sizeof(X86_GR16_AO_32_fp)/sizeof(unsigned));
335 return X86_GR16_AO_32 + (sizeof(X86_GR16_AO_32) / sizeof(unsigned));
342 def GR32 : RegisterClass<"X86", [i32], 32,
343 [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
344 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]> {
345 let SubRegClassList = [GR8, GR16];
346 let MethodProtos = [{
347 iterator allocation_order_begin(const MachineFunction &MF) const;
348 iterator allocation_order_end(const MachineFunction &MF) const;
350 let MethodBodies = [{
351 // Does the function dedicate RBP / EBP to being a frame ptr?
352 // If so, don't allocate ESP or EBP.
353 static const unsigned X86_GR32_AO_64_fp[] =
354 {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
355 X86::R8D, X86::R9D, X86::R10D, X86::R11D,
356 X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D};
357 static const unsigned X86_GR32_AO_32_fp[] =
358 {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX};
359 // If not, just don't allocate SPL.
360 static const unsigned X86_GR32_AO_64[] =
361 {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
362 X86::R8D, X86::R9D, X86::R10D, X86::R11D,
363 X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP};
364 static const unsigned X86_GR32_AO_32[] =
365 {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP};
368 GR32Class::allocation_order_begin(const MachineFunction &MF) const {
369 const TargetMachine &TM = MF.getTarget();
370 const TargetRegisterInfo *RI = TM.getRegisterInfo();
371 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
372 if (Subtarget.is64Bit()) {
374 return X86_GR32_AO_64_fp;
376 return X86_GR32_AO_64;
379 return X86_GR32_AO_32_fp;
381 return X86_GR32_AO_32;
386 GR32Class::allocation_order_end(const MachineFunction &MF) const {
387 const TargetMachine &TM = MF.getTarget();
388 const TargetRegisterInfo *RI = TM.getRegisterInfo();
389 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
390 if (Subtarget.is64Bit()) {
392 return X86_GR32_AO_64_fp+(sizeof(X86_GR32_AO_64_fp)/sizeof(unsigned));
394 return X86_GR32_AO_64 + (sizeof(X86_GR32_AO_64) / sizeof(unsigned));
397 return X86_GR32_AO_32_fp+(sizeof(X86_GR32_AO_32_fp)/sizeof(unsigned));
399 return X86_GR32_AO_32 + (sizeof(X86_GR32_AO_32) / sizeof(unsigned));
406 def GR64 : RegisterClass<"X86", [i64], 64,
407 [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
408 RBX, R14, R15, R12, R13, RBP, RSP]> {
409 let SubRegClassList = [GR8, GR16, GR32];
410 let MethodProtos = [{
411 iterator allocation_order_end(const MachineFunction &MF) const;
413 let MethodBodies = [{
415 GR64Class::allocation_order_end(const MachineFunction &MF) const {
416 const TargetMachine &TM = MF.getTarget();
417 const TargetRegisterInfo *RI = TM.getRegisterInfo();
418 if (RI->hasFP(MF)) // Does the function dedicate RBP to being a frame ptr?
419 return end()-2; // If so, don't allocate RSP or RBP
421 return end()-1; // If not, just don't allocate RSP
427 // GR16, GR32 subclasses which contain registers that have GR8 sub-registers.
428 // These should only be used for 32-bit mode.
429 def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
430 let SubRegClassList = [GR8];
432 def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
433 let SubRegClassList = [GR8, GR16];
436 // Scalar SSE2 floating point registers.
437 def FR32 : RegisterClass<"X86", [f32], 32,
438 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
439 XMM8, XMM9, XMM10, XMM11,
440 XMM12, XMM13, XMM14, XMM15]> {
441 let MethodProtos = [{
442 iterator allocation_order_end(const MachineFunction &MF) const;
444 let MethodBodies = [{
446 FR32Class::allocation_order_end(const MachineFunction &MF) const {
447 const TargetMachine &TM = MF.getTarget();
448 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
449 if (!Subtarget.is64Bit())
450 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
457 def FR64 : RegisterClass<"X86", [f64], 64,
458 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
459 XMM8, XMM9, XMM10, XMM11,
460 XMM12, XMM13, XMM14, XMM15]> {
461 let MethodProtos = [{
462 iterator allocation_order_end(const MachineFunction &MF) const;
464 let MethodBodies = [{
466 FR64Class::allocation_order_end(const MachineFunction &MF) const {
467 const TargetMachine &TM = MF.getTarget();
468 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
469 if (!Subtarget.is64Bit())
470 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
478 // FIXME: This sets up the floating point register files as though they are f64
479 // values, though they really are f80 values. This will cause us to spill
480 // values as 64-bit quantities instead of 80-bit quantities, which is much much
481 // faster on common hardware. In reality, this should be controlled by a
482 // command line option or something.
484 def RFP32 : RegisterClass<"X86", [f32], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
485 def RFP64 : RegisterClass<"X86", [f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
486 def RFP80 : RegisterClass<"X86", [f80], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
488 // Floating point stack registers (these are not allocatable by the
489 // register allocator - the floating point stackifier is responsible
490 // for transforming FPn allocations to STn registers)
491 def RST : RegisterClass<"X86", [f64], 32,
492 [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
493 let MethodProtos = [{
494 iterator allocation_order_end(const MachineFunction &MF) const;
496 let MethodBodies = [{
498 RSTClass::allocation_order_end(const MachineFunction &MF) const {
504 // Generic vector registers: VR64 and VR128.
505 def VR64 : RegisterClass<"X86", [v8i8, v4i16, v2i32, v1i64], 64,
506 [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
507 def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128,
508 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
509 XMM8, XMM9, XMM10, XMM11,
510 XMM12, XMM13, XMM14, XMM15]> {
511 let MethodProtos = [{
512 iterator allocation_order_end(const MachineFunction &MF) const;
514 let MethodBodies = [{
516 VR128Class::allocation_order_end(const MachineFunction &MF) const {
517 const TargetMachine &TM = MF.getTarget();
518 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
519 if (!Subtarget.is64Bit())
520 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
527 // Status flags registers.
528 def CCR : RegisterClass<"X86", [i32], 32, [EFLAGS]> {
529 let CopyCost = -1; // Don't allow copying of status registers.