1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 Register file, defining the registers themselves,
11 // aliases between the registers, and the register classes built out of the
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Register definitions...
19 let Namespace = "X86" in {
21 // In the register alias definitions below, we define which registers alias
22 // which others. We only specify which registers the small registers alias,
23 // because the register file generator is smart enough to figure out that
24 // AL aliases AX if we tell it that AX aliased AL (for example).
26 // Dwarf numbering is different for 32-bit and 64-bit, and there are
27 // variations by target as well. Currently the first entry is for X86-64,
28 // second - for X86-32/Darwin and third for X86-32/Linux
30 // FIXME: Comments in gcc indicate that Darwin uses different numbering
31 // for debug info and exception handling info:( The numbering here is
32 // for exception handling.
36 def AL : Register<"AL">, DwarfRegNum<[0, 0, 0]>;
37 def DL : Register<"DL">, DwarfRegNum<[1, 2, 2]>;
38 def CL : Register<"CL">, DwarfRegNum<[2, 1, 1]>;
39 def BL : Register<"BL">, DwarfRegNum<[3, 3, 3]>;
42 def SIL : Register<"SIL">, DwarfRegNum<[4, 6, 6]>;
43 def DIL : Register<"DIL">, DwarfRegNum<[5, 7, 7]>;
44 def BPL : Register<"BPL">, DwarfRegNum<[6, 4, 5]>;
45 def SPL : Register<"SPL">, DwarfRegNum<[7, 5, 4]>;
46 def R8B : Register<"R8B">, DwarfRegNum<[8, -2, -2]>;
47 def R9B : Register<"R9B">, DwarfRegNum<[9, -2, -2]>;
48 def R10B : Register<"R10B">, DwarfRegNum<[10, -2, -2]>;
49 def R11B : Register<"R11B">, DwarfRegNum<[11, -2, -2]>;
50 def R12B : Register<"R12B">, DwarfRegNum<[12, -2, -2]>;
51 def R13B : Register<"R13B">, DwarfRegNum<[13, -2, -2]>;
52 def R14B : Register<"R14B">, DwarfRegNum<[14, -2, -2]>;
53 def R15B : Register<"R15B">, DwarfRegNum<[15, -2, -2]>;
55 // High registers X86-32 only
56 def AH : Register<"AH">, DwarfRegNum<[0, 0, 0]>;
57 def DH : Register<"DH">, DwarfRegNum<[1, 2, 2]>;
58 def CH : Register<"CH">, DwarfRegNum<[2, 1, 1]>;
59 def BH : Register<"BH">, DwarfRegNum<[3, 3, 3]>;
62 def AX : RegisterWithSubRegs<"AX", [AH,AL]>, DwarfRegNum<[0, 0, 0]>;
63 def DX : RegisterWithSubRegs<"DX", [DH,DL]>, DwarfRegNum<[1, 2, 2]>;
64 def CX : RegisterWithSubRegs<"CX", [CH,CL]>, DwarfRegNum<[2, 1, 1]>;
65 def BX : RegisterWithSubRegs<"BX", [BH,BL]>, DwarfRegNum<[3, 3, 3]>;
66 def SI : RegisterWithSubRegs<"SI", [SIL]>, DwarfRegNum<[4, 6, 6]>;
67 def DI : RegisterWithSubRegs<"DI", [DIL]>, DwarfRegNum<[5, 7, 7]>;
68 def BP : RegisterWithSubRegs<"BP", [BPL]>, DwarfRegNum<[6, 4, 5]>;
69 def SP : RegisterWithSubRegs<"SP", [SPL]>, DwarfRegNum<[7, 5, 4]>;
70 def IP : Register<"IP">, DwarfRegNum<[16]>;
73 def R8W : RegisterWithSubRegs<"R8W", [R8B]>, DwarfRegNum<[8, -2, -2]>;
74 def R9W : RegisterWithSubRegs<"R9W", [R9B]>, DwarfRegNum<[9, -2, -2]>;
75 def R10W : RegisterWithSubRegs<"R10W", [R10B]>, DwarfRegNum<[10, -2, -2]>;
76 def R11W : RegisterWithSubRegs<"R11W", [R11B]>, DwarfRegNum<[11, -2, -2]>;
77 def R12W : RegisterWithSubRegs<"R12W", [R12B]>, DwarfRegNum<[12, -2, -2]>;
78 def R13W : RegisterWithSubRegs<"R13W", [R13B]>, DwarfRegNum<[13, -2, -2]>;
79 def R14W : RegisterWithSubRegs<"R14W", [R14B]>, DwarfRegNum<[14, -2, -2]>;
80 def R15W : RegisterWithSubRegs<"R15W", [R15B]>, DwarfRegNum<[15, -2, -2]>;
83 def EAX : RegisterWithSubRegs<"EAX", [AX]>, DwarfRegNum<[0, 0, 0]>;
84 def EDX : RegisterWithSubRegs<"EDX", [DX]>, DwarfRegNum<[1, 2, 2]>;
85 def ECX : RegisterWithSubRegs<"ECX", [CX]>, DwarfRegNum<[2, 1, 1]>;
86 def EBX : RegisterWithSubRegs<"EBX", [BX]>, DwarfRegNum<[3, 3, 3]>;
87 def ESI : RegisterWithSubRegs<"ESI", [SI]>, DwarfRegNum<[4, 6, 6]>;
88 def EDI : RegisterWithSubRegs<"EDI", [DI]>, DwarfRegNum<[5, 7, 7]>;
89 def EBP : RegisterWithSubRegs<"EBP", [BP]>, DwarfRegNum<[6, 4, 5]>;
90 def ESP : RegisterWithSubRegs<"ESP", [SP]>, DwarfRegNum<[7, 5, 4]>;
91 def EIP : RegisterWithSubRegs<"EIP", [IP]>, DwarfRegNum<[16, 8, 8]>;
94 def R8D : RegisterWithSubRegs<"R8D", [R8W]>, DwarfRegNum<[8, -2, -2]>;
95 def R9D : RegisterWithSubRegs<"R9D", [R9W]>, DwarfRegNum<[9, -2, -2]>;
96 def R10D : RegisterWithSubRegs<"R10D", [R10W]>, DwarfRegNum<[10, -2, -2]>;
97 def R11D : RegisterWithSubRegs<"R11D", [R11W]>, DwarfRegNum<[11, -2, -2]>;
98 def R12D : RegisterWithSubRegs<"R12D", [R12W]>, DwarfRegNum<[12, -2, -2]>;
99 def R13D : RegisterWithSubRegs<"R13D", [R13W]>, DwarfRegNum<[13, -2, -2]>;
100 def R14D : RegisterWithSubRegs<"R14D", [R14W]>, DwarfRegNum<[14, -2, -2]>;
101 def R15D : RegisterWithSubRegs<"R15D", [R15W]>, DwarfRegNum<[15, -2, -2]>;
103 // 64-bit registers, X86-64 only
104 def RAX : RegisterWithSubRegs<"RAX", [EAX]>, DwarfRegNum<[0, -2, -2]>;
105 def RDX : RegisterWithSubRegs<"RDX", [EDX]>, DwarfRegNum<[1, -2, -2]>;
106 def RCX : RegisterWithSubRegs<"RCX", [ECX]>, DwarfRegNum<[2, -2, -2]>;
107 def RBX : RegisterWithSubRegs<"RBX", [EBX]>, DwarfRegNum<[3, -2, -2]>;
108 def RSI : RegisterWithSubRegs<"RSI", [ESI]>, DwarfRegNum<[4, -2, -2]>;
109 def RDI : RegisterWithSubRegs<"RDI", [EDI]>, DwarfRegNum<[5, -2, -2]>;
110 def RBP : RegisterWithSubRegs<"RBP", [EBP]>, DwarfRegNum<[6, -2, -2]>;
111 def RSP : RegisterWithSubRegs<"RSP", [ESP]>, DwarfRegNum<[7, -2, -2]>;
113 def R8 : RegisterWithSubRegs<"R8", [R8D]>, DwarfRegNum<[8, -2, -2]>;
114 def R9 : RegisterWithSubRegs<"R9", [R9D]>, DwarfRegNum<[9, -2, -2]>;
115 def R10 : RegisterWithSubRegs<"R10", [R10D]>, DwarfRegNum<[10, -2, -2]>;
116 def R11 : RegisterWithSubRegs<"R11", [R11D]>, DwarfRegNum<[11, -2, -2]>;
117 def R12 : RegisterWithSubRegs<"R12", [R12D]>, DwarfRegNum<[12, -2, -2]>;
118 def R13 : RegisterWithSubRegs<"R13", [R13D]>, DwarfRegNum<[13, -2, -2]>;
119 def R14 : RegisterWithSubRegs<"R14", [R14D]>, DwarfRegNum<[14, -2, -2]>;
120 def R15 : RegisterWithSubRegs<"R15", [R15D]>, DwarfRegNum<[15, -2, -2]>;
121 def RIP : RegisterWithSubRegs<"RIP", [EIP]>, DwarfRegNum<[16, -2, -2]>;
123 // MMX Registers. These are actually aliased to ST0 .. ST7
124 def MM0 : Register<"MM0">, DwarfRegNum<[41, 29, 29]>;
125 def MM1 : Register<"MM1">, DwarfRegNum<[42, 30, 30]>;
126 def MM2 : Register<"MM2">, DwarfRegNum<[43, 31, 31]>;
127 def MM3 : Register<"MM3">, DwarfRegNum<[44, 32, 32]>;
128 def MM4 : Register<"MM4">, DwarfRegNum<[45, 33, 33]>;
129 def MM5 : Register<"MM5">, DwarfRegNum<[46, 34, 34]>;
130 def MM6 : Register<"MM6">, DwarfRegNum<[47, 35, 35]>;
131 def MM7 : Register<"MM7">, DwarfRegNum<[48, 36, 36]>;
133 // Pseudo Floating Point registers
134 def FP0 : Register<"FP0">;
135 def FP1 : Register<"FP1">;
136 def FP2 : Register<"FP2">;
137 def FP3 : Register<"FP3">;
138 def FP4 : Register<"FP4">;
139 def FP5 : Register<"FP5">;
140 def FP6 : Register<"FP6">;
142 // XMM Registers, used by the various SSE instruction set extensions
143 def XMM0: Register<"XMM0">, DwarfRegNum<[17, 21, 21]>;
144 def XMM1: Register<"XMM1">, DwarfRegNum<[18, 22, 22]>;
145 def XMM2: Register<"XMM2">, DwarfRegNum<[19, 23, 23]>;
146 def XMM3: Register<"XMM3">, DwarfRegNum<[20, 24, 24]>;
147 def XMM4: Register<"XMM4">, DwarfRegNum<[21, 25, 25]>;
148 def XMM5: Register<"XMM5">, DwarfRegNum<[22, 26, 26]>;
149 def XMM6: Register<"XMM6">, DwarfRegNum<[23, 27, 27]>;
150 def XMM7: Register<"XMM7">, DwarfRegNum<[24, 28, 28]>;
153 def XMM8: Register<"XMM8">, DwarfRegNum<[25, -2, -2]>;
154 def XMM9: Register<"XMM9">, DwarfRegNum<[26, -2, -2]>;
155 def XMM10: Register<"XMM10">, DwarfRegNum<[27, -2, -2]>;
156 def XMM11: Register<"XMM11">, DwarfRegNum<[28, -2, -2]>;
157 def XMM12: Register<"XMM12">, DwarfRegNum<[29, -2, -2]>;
158 def XMM13: Register<"XMM13">, DwarfRegNum<[30, -2, -2]>;
159 def XMM14: Register<"XMM14">, DwarfRegNum<[31, -2, -2]>;
160 def XMM15: Register<"XMM15">, DwarfRegNum<[32, -2, -2]>;
162 // Floating point stack registers
163 def ST0 : Register<"ST(0)">, DwarfRegNum<[33, 12, 11]>;
164 def ST1 : Register<"ST(1)">, DwarfRegNum<[34, 13, 12]>;
165 def ST2 : Register<"ST(2)">, DwarfRegNum<[35, 14, 13]>;
166 def ST3 : Register<"ST(3)">, DwarfRegNum<[36, 15, 14]>;
167 def ST4 : Register<"ST(4)">, DwarfRegNum<[37, 16, 15]>;
168 def ST5 : Register<"ST(5)">, DwarfRegNum<[38, 17, 16]>;
169 def ST6 : Register<"ST(6)">, DwarfRegNum<[39, 18, 17]>;
170 def ST7 : Register<"ST(7)">, DwarfRegNum<[40, 19, 18]>;
172 // Status flags register
173 def EFLAGS : Register<"EFLAGS">;
177 //===----------------------------------------------------------------------===//
178 // Subregister Set Definitions... now that we have all of the pieces, define the
179 // sub registers for each register.
182 def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
183 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
184 [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
185 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
187 // It's unclear if this subreg set is safe, given that not all registers
188 // in the class have an 'H' subreg.
189 // def : SubRegSet<2, [AX, CX, DX, BX],
190 // [AH, CH, DH, BH]>;
192 def : SubRegSet<1, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
193 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
194 [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
195 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
197 def : SubRegSet<2, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
198 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
199 [AX, CX, DX, BX, SP, BP, SI, DI,
200 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
203 def : SubRegSet<1, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
204 R8, R9, R10, R11, R12, R13, R14, R15],
205 [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
206 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
208 def : SubRegSet<2, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
209 R8, R9, R10, R11, R12, R13, R14, R15],
210 [AX, CX, DX, BX, SP, BP, SI, DI,
211 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
213 def : SubRegSet<3, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
214 R8, R9, R10, R11, R12, R13, R14, R15],
215 [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
216 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]>;
218 //===----------------------------------------------------------------------===//
219 // Register Class Definitions... now that we have all of the pieces, define the
220 // top-level register classes. The order specified in the register list is
221 // implicitly defined to be the register allocation order.
224 // List call-clobbered registers before callee-save registers. RBX, RBP, (and
225 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
226 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
228 // FIXME: Allow AH, CH, DH, BH in 64-mode for non-REX instructions,
229 def GR8 : RegisterClass<"X86", [i8], 8,
230 [AL, CL, DL, BL, AH, CH, DH, BH, SIL, DIL, BPL, SPL,
231 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]> {
232 let MethodProtos = [{
233 iterator allocation_order_begin(const MachineFunction &MF) const;
234 iterator allocation_order_end(const MachineFunction &MF) const;
236 let MethodBodies = [{
237 // Does the function dedicate RBP / EBP to being a frame ptr?
238 // If so, don't allocate SPL or BPL.
239 static const unsigned X86_GR8_AO_64_fp[] =
240 {X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
241 X86::R8B, X86::R9B, X86::R10B, X86::R11B,
242 X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B};
243 // If not, just don't allocate SPL.
244 static const unsigned X86_GR8_AO_64[] =
245 {X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
246 X86::R8B, X86::R9B, X86::R10B, X86::R11B,
247 X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL};
248 // In 32-mode, none of the 8-bit registers aliases EBP or ESP.
249 static const unsigned X86_GR8_AO_32[] =
250 {X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH};
253 GR8Class::allocation_order_begin(const MachineFunction &MF) const {
254 const TargetMachine &TM = MF.getTarget();
255 const MRegisterInfo *RI = TM.getRegisterInfo();
256 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
257 if (!Subtarget.is64Bit())
258 return X86_GR8_AO_32;
259 else if (RI->hasFP(MF))
260 return X86_GR8_AO_64_fp;
262 return X86_GR8_AO_64;
266 GR8Class::allocation_order_end(const MachineFunction &MF) const {
267 const TargetMachine &TM = MF.getTarget();
268 const MRegisterInfo *RI = TM.getRegisterInfo();
269 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
270 if (!Subtarget.is64Bit())
271 return X86_GR8_AO_32 + (sizeof(X86_GR8_AO_32) / sizeof(unsigned));
272 else if (RI->hasFP(MF))
273 return X86_GR8_AO_64_fp + (sizeof(X86_GR8_AO_64_fp) / sizeof(unsigned));
275 return X86_GR8_AO_64 + (sizeof(X86_GR8_AO_64) / sizeof(unsigned));
281 def GR16 : RegisterClass<"X86", [i16], 16,
282 [AX, CX, DX, SI, DI, BX, BP, SP,
283 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]> {
284 let SubRegClassList = [GR8];
285 let MethodProtos = [{
286 iterator allocation_order_begin(const MachineFunction &MF) const;
287 iterator allocation_order_end(const MachineFunction &MF) const;
289 let MethodBodies = [{
290 // Does the function dedicate RBP / EBP to being a frame ptr?
291 // If so, don't allocate SP or BP.
292 static const unsigned X86_GR16_AO_64_fp[] =
293 {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
294 X86::R8W, X86::R9W, X86::R10W, X86::R11W,
295 X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W};
296 static const unsigned X86_GR16_AO_32_fp[] =
297 {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX};
298 // If not, just don't allocate SPL.
299 static const unsigned X86_GR16_AO_64[] =
300 {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
301 X86::R8W, X86::R9W, X86::R10W, X86::R11W,
302 X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::BP};
303 static const unsigned X86_GR16_AO_32[] =
304 {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP};
307 GR16Class::allocation_order_begin(const MachineFunction &MF) const {
308 const TargetMachine &TM = MF.getTarget();
309 const MRegisterInfo *RI = TM.getRegisterInfo();
310 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
311 if (Subtarget.is64Bit()) {
313 return X86_GR16_AO_64_fp;
315 return X86_GR16_AO_64;
318 return X86_GR16_AO_32_fp;
320 return X86_GR16_AO_32;
325 GR16Class::allocation_order_end(const MachineFunction &MF) const {
326 const TargetMachine &TM = MF.getTarget();
327 const MRegisterInfo *RI = TM.getRegisterInfo();
328 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
329 if (Subtarget.is64Bit()) {
331 return X86_GR16_AO_64_fp+(sizeof(X86_GR16_AO_64_fp)/sizeof(unsigned));
333 return X86_GR16_AO_64 + (sizeof(X86_GR16_AO_64) / sizeof(unsigned));
336 return X86_GR16_AO_32_fp+(sizeof(X86_GR16_AO_32_fp)/sizeof(unsigned));
338 return X86_GR16_AO_32 + (sizeof(X86_GR16_AO_32) / sizeof(unsigned));
345 def GR32 : RegisterClass<"X86", [i32], 32,
346 [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
347 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]> {
348 let SubRegClassList = [GR8, GR16];
349 let MethodProtos = [{
350 iterator allocation_order_begin(const MachineFunction &MF) const;
351 iterator allocation_order_end(const MachineFunction &MF) const;
353 let MethodBodies = [{
354 // Does the function dedicate RBP / EBP to being a frame ptr?
355 // If so, don't allocate ESP or EBP.
356 static const unsigned X86_GR32_AO_64_fp[] =
357 {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
358 X86::R8D, X86::R9D, X86::R10D, X86::R11D,
359 X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D};
360 static const unsigned X86_GR32_AO_32_fp[] =
361 {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX};
362 // If not, just don't allocate SPL.
363 static const unsigned X86_GR32_AO_64[] =
364 {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
365 X86::R8D, X86::R9D, X86::R10D, X86::R11D,
366 X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP};
367 static const unsigned X86_GR32_AO_32[] =
368 {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP};
371 GR32Class::allocation_order_begin(const MachineFunction &MF) const {
372 const TargetMachine &TM = MF.getTarget();
373 const MRegisterInfo *RI = TM.getRegisterInfo();
374 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
375 if (Subtarget.is64Bit()) {
377 return X86_GR32_AO_64_fp;
379 return X86_GR32_AO_64;
382 return X86_GR32_AO_32_fp;
384 return X86_GR32_AO_32;
389 GR32Class::allocation_order_end(const MachineFunction &MF) const {
390 const TargetMachine &TM = MF.getTarget();
391 const MRegisterInfo *RI = TM.getRegisterInfo();
392 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
393 if (Subtarget.is64Bit()) {
395 return X86_GR32_AO_64_fp+(sizeof(X86_GR32_AO_64_fp)/sizeof(unsigned));
397 return X86_GR32_AO_64 + (sizeof(X86_GR32_AO_64) / sizeof(unsigned));
400 return X86_GR32_AO_32_fp+(sizeof(X86_GR32_AO_32_fp)/sizeof(unsigned));
402 return X86_GR32_AO_32 + (sizeof(X86_GR32_AO_32) / sizeof(unsigned));
409 def GR64 : RegisterClass<"X86", [i64], 64,
410 [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
411 RBX, R14, R15, R12, R13, RBP, RSP]> {
412 let SubRegClassList = [GR8, GR16, GR32];
413 let MethodProtos = [{
414 iterator allocation_order_end(const MachineFunction &MF) const;
416 let MethodBodies = [{
418 GR64Class::allocation_order_end(const MachineFunction &MF) const {
419 const TargetMachine &TM = MF.getTarget();
420 const MRegisterInfo *RI = TM.getRegisterInfo();
421 if (RI->hasFP(MF)) // Does the function dedicate RBP to being a frame ptr?
422 return end()-2; // If so, don't allocate RSP or RBP
424 return end()-1; // If not, just don't allocate RSP
430 // GR16, GR32 subclasses which contain registers that have GR8 sub-registers.
431 // These should only be used for 32-bit mode.
432 def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
433 let SubRegClassList = [GR8];
435 def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
436 let SubRegClassList = [GR8, GR16];
439 // Scalar SSE2 floating point registers.
440 def FR32 : RegisterClass<"X86", [f32], 32,
441 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
442 XMM8, XMM9, XMM10, XMM11,
443 XMM12, XMM13, XMM14, XMM15]> {
444 let MethodProtos = [{
445 iterator allocation_order_end(const MachineFunction &MF) const;
447 let MethodBodies = [{
449 FR32Class::allocation_order_end(const MachineFunction &MF) const {
450 const TargetMachine &TM = MF.getTarget();
451 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
452 if (!Subtarget.is64Bit())
453 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
460 def FR64 : RegisterClass<"X86", [f64], 64,
461 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
462 XMM8, XMM9, XMM10, XMM11,
463 XMM12, XMM13, XMM14, XMM15]> {
464 let MethodProtos = [{
465 iterator allocation_order_end(const MachineFunction &MF) const;
467 let MethodBodies = [{
469 FR64Class::allocation_order_end(const MachineFunction &MF) const {
470 const TargetMachine &TM = MF.getTarget();
471 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
472 if (!Subtarget.is64Bit())
473 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
481 // FIXME: This sets up the floating point register files as though they are f64
482 // values, though they really are f80 values. This will cause us to spill
483 // values as 64-bit quantities instead of 80-bit quantities, which is much much
484 // faster on common hardware. In reality, this should be controlled by a
485 // command line option or something.
487 def RFP32 : RegisterClass<"X86", [f32], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
488 def RFP64 : RegisterClass<"X86", [f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
489 def RFP80 : RegisterClass<"X86", [f80], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
491 // Floating point stack registers (these are not allocatable by the
492 // register allocator - the floating point stackifier is responsible
493 // for transforming FPn allocations to STn registers)
494 def RST : RegisterClass<"X86", [f64], 32,
495 [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
496 let MethodProtos = [{
497 iterator allocation_order_end(const MachineFunction &MF) const;
499 let MethodBodies = [{
501 RSTClass::allocation_order_end(const MachineFunction &MF) const {
507 // Generic vector registers: VR64 and VR128.
508 def VR64 : RegisterClass<"X86", [v8i8, v4i16, v2i32, v1i64], 64,
509 [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
510 def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128,
511 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
512 XMM8, XMM9, XMM10, XMM11,
513 XMM12, XMM13, XMM14, XMM15]> {
514 let MethodProtos = [{
515 iterator allocation_order_end(const MachineFunction &MF) const;
517 let MethodBodies = [{
519 VR128Class::allocation_order_end(const MachineFunction &MF) const {
520 const TargetMachine &TM = MF.getTarget();
521 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
522 if (!Subtarget.is64Bit())
523 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
530 // Status flags registers.
531 def CCR : RegisterClass<"X86", [i32], 32, [EFLAGS]> {
532 let CopyCost = -1; // Don't allow copying of status registers.