1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 Register file, defining the registers themselves,
11 // aliases between the registers, and the register classes built out of the
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Register definitions...
19 let Namespace = "X86" in {
21 // In the register alias definitions below, we define which registers alias
22 // which others. We only specify which registers the small registers alias,
23 // because the register file generator is smart enough to figure out that
24 // AL aliases AX if we tell it that AX aliased AL (for example).
26 // Dwarf numbering is different for 32-bit and 64-bit, and there are
27 // variations by target as well. Currently the first entry is for X86-64,
28 // second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux
29 // and debug information on X86-32/Darwin)
33 def AL : Register<"al">, DwarfRegNum<[0, 0, 0]>;
34 def DL : Register<"dl">, DwarfRegNum<[1, 2, 2]>;
35 def CL : Register<"cl">, DwarfRegNum<[2, 1, 1]>;
36 def BL : Register<"bl">, DwarfRegNum<[3, 3, 3]>;
39 def SIL : Register<"sil">, DwarfRegNum<[4, 6, 6]>;
40 def DIL : Register<"dil">, DwarfRegNum<[5, 7, 7]>;
41 def BPL : Register<"bpl">, DwarfRegNum<[6, 4, 5]>;
42 def SPL : Register<"spl">, DwarfRegNum<[7, 5, 4]>;
43 def R8B : Register<"r8b">, DwarfRegNum<[8, -2, -2]>;
44 def R9B : Register<"r9b">, DwarfRegNum<[9, -2, -2]>;
45 def R10B : Register<"r10b">, DwarfRegNum<[10, -2, -2]>;
46 def R11B : Register<"r11b">, DwarfRegNum<[11, -2, -2]>;
47 def R12B : Register<"r12b">, DwarfRegNum<[12, -2, -2]>;
48 def R13B : Register<"r13b">, DwarfRegNum<[13, -2, -2]>;
49 def R14B : Register<"r14b">, DwarfRegNum<[14, -2, -2]>;
50 def R15B : Register<"r15b">, DwarfRegNum<[15, -2, -2]>;
52 // High registers X86-32 only
53 def AH : Register<"ah">, DwarfRegNum<[0, 0, 0]>;
54 def DH : Register<"dh">, DwarfRegNum<[1, 2, 2]>;
55 def CH : Register<"ch">, DwarfRegNum<[2, 1, 1]>;
56 def BH : Register<"bh">, DwarfRegNum<[3, 3, 3]>;
59 def AX : RegisterWithSubRegs<"ax", [AL,AH]>, DwarfRegNum<[0, 0, 0]>;
60 def DX : RegisterWithSubRegs<"dx", [DL,DH]>, DwarfRegNum<[1, 2, 2]>;
61 def CX : RegisterWithSubRegs<"cx", [CL,CH]>, DwarfRegNum<[2, 1, 1]>;
62 def BX : RegisterWithSubRegs<"bx", [BL,BH]>, DwarfRegNum<[3, 3, 3]>;
63 def SI : RegisterWithSubRegs<"si", [SIL]>, DwarfRegNum<[4, 6, 6]>;
64 def DI : RegisterWithSubRegs<"di", [DIL]>, DwarfRegNum<[5, 7, 7]>;
65 def BP : RegisterWithSubRegs<"bp", [BPL]>, DwarfRegNum<[6, 4, 5]>;
66 def SP : RegisterWithSubRegs<"sp", [SPL]>, DwarfRegNum<[7, 5, 4]>;
67 def IP : Register<"ip">, DwarfRegNum<[16]>;
70 def R8W : RegisterWithSubRegs<"r8w", [R8B]>, DwarfRegNum<[8, -2, -2]>;
71 def R9W : RegisterWithSubRegs<"r9w", [R9B]>, DwarfRegNum<[9, -2, -2]>;
72 def R10W : RegisterWithSubRegs<"r10w", [R10B]>, DwarfRegNum<[10, -2, -2]>;
73 def R11W : RegisterWithSubRegs<"r11w", [R11B]>, DwarfRegNum<[11, -2, -2]>;
74 def R12W : RegisterWithSubRegs<"r12w", [R12B]>, DwarfRegNum<[12, -2, -2]>;
75 def R13W : RegisterWithSubRegs<"r13w", [R13B]>, DwarfRegNum<[13, -2, -2]>;
76 def R14W : RegisterWithSubRegs<"r14w", [R14B]>, DwarfRegNum<[14, -2, -2]>;
77 def R15W : RegisterWithSubRegs<"r15w", [R15B]>, DwarfRegNum<[15, -2, -2]>;
80 def EAX : RegisterWithSubRegs<"eax", [AX]>, DwarfRegNum<[0, 0, 0]>;
81 def EDX : RegisterWithSubRegs<"edx", [DX]>, DwarfRegNum<[1, 2, 2]>;
82 def ECX : RegisterWithSubRegs<"ecx", [CX]>, DwarfRegNum<[2, 1, 1]>;
83 def EBX : RegisterWithSubRegs<"ebx", [BX]>, DwarfRegNum<[3, 3, 3]>;
84 def ESI : RegisterWithSubRegs<"esi", [SI]>, DwarfRegNum<[4, 6, 6]>;
85 def EDI : RegisterWithSubRegs<"edi", [DI]>, DwarfRegNum<[5, 7, 7]>;
86 def EBP : RegisterWithSubRegs<"ebp", [BP]>, DwarfRegNum<[6, 4, 5]>;
87 def ESP : RegisterWithSubRegs<"esp", [SP]>, DwarfRegNum<[7, 5, 4]>;
88 def EIP : RegisterWithSubRegs<"eip", [IP]>, DwarfRegNum<[16, 8, 8]>;
91 def R8D : RegisterWithSubRegs<"r8d", [R8W]>, DwarfRegNum<[8, -2, -2]>;
92 def R9D : RegisterWithSubRegs<"r9d", [R9W]>, DwarfRegNum<[9, -2, -2]>;
93 def R10D : RegisterWithSubRegs<"r10d", [R10W]>, DwarfRegNum<[10, -2, -2]>;
94 def R11D : RegisterWithSubRegs<"r11d", [R11W]>, DwarfRegNum<[11, -2, -2]>;
95 def R12D : RegisterWithSubRegs<"r12d", [R12W]>, DwarfRegNum<[12, -2, -2]>;
96 def R13D : RegisterWithSubRegs<"r13d", [R13W]>, DwarfRegNum<[13, -2, -2]>;
97 def R14D : RegisterWithSubRegs<"r14d", [R14W]>, DwarfRegNum<[14, -2, -2]>;
98 def R15D : RegisterWithSubRegs<"r15d", [R15W]>, DwarfRegNum<[15, -2, -2]>;
100 // 64-bit registers, X86-64 only
101 def RAX : RegisterWithSubRegs<"rax", [EAX]>, DwarfRegNum<[0, -2, -2]>;
102 def RDX : RegisterWithSubRegs<"rdx", [EDX]>, DwarfRegNum<[1, -2, -2]>;
103 def RCX : RegisterWithSubRegs<"rcx", [ECX]>, DwarfRegNum<[2, -2, -2]>;
104 def RBX : RegisterWithSubRegs<"rbx", [EBX]>, DwarfRegNum<[3, -2, -2]>;
105 def RSI : RegisterWithSubRegs<"rsi", [ESI]>, DwarfRegNum<[4, -2, -2]>;
106 def RDI : RegisterWithSubRegs<"rdi", [EDI]>, DwarfRegNum<[5, -2, -2]>;
107 def RBP : RegisterWithSubRegs<"rbp", [EBP]>, DwarfRegNum<[6, -2, -2]>;
108 def RSP : RegisterWithSubRegs<"rsp", [ESP]>, DwarfRegNum<[7, -2, -2]>;
110 def R8 : RegisterWithSubRegs<"r8", [R8D]>, DwarfRegNum<[8, -2, -2]>;
111 def R9 : RegisterWithSubRegs<"r9", [R9D]>, DwarfRegNum<[9, -2, -2]>;
112 def R10 : RegisterWithSubRegs<"r10", [R10D]>, DwarfRegNum<[10, -2, -2]>;
113 def R11 : RegisterWithSubRegs<"r11", [R11D]>, DwarfRegNum<[11, -2, -2]>;
114 def R12 : RegisterWithSubRegs<"r12", [R12D]>, DwarfRegNum<[12, -2, -2]>;
115 def R13 : RegisterWithSubRegs<"r13", [R13D]>, DwarfRegNum<[13, -2, -2]>;
116 def R14 : RegisterWithSubRegs<"r14", [R14D]>, DwarfRegNum<[14, -2, -2]>;
117 def R15 : RegisterWithSubRegs<"r15", [R15D]>, DwarfRegNum<[15, -2, -2]>;
118 def RIP : RegisterWithSubRegs<"rip", [EIP]>, DwarfRegNum<[16, -2, -2]>;
120 // MMX Registers. These are actually aliased to ST0 .. ST7
121 def MM0 : Register<"mm0">, DwarfRegNum<[41, 29, 29]>;
122 def MM1 : Register<"mm1">, DwarfRegNum<[42, 30, 30]>;
123 def MM2 : Register<"mm2">, DwarfRegNum<[43, 31, 31]>;
124 def MM3 : Register<"mm3">, DwarfRegNum<[44, 32, 32]>;
125 def MM4 : Register<"mm4">, DwarfRegNum<[45, 33, 33]>;
126 def MM5 : Register<"mm5">, DwarfRegNum<[46, 34, 34]>;
127 def MM6 : Register<"mm6">, DwarfRegNum<[47, 35, 35]>;
128 def MM7 : Register<"mm7">, DwarfRegNum<[48, 36, 36]>;
130 // Pseudo Floating Point registers
131 def FP0 : Register<"fp0">;
132 def FP1 : Register<"fp1">;
133 def FP2 : Register<"fp2">;
134 def FP3 : Register<"fp3">;
135 def FP4 : Register<"fp4">;
136 def FP5 : Register<"fp5">;
137 def FP6 : Register<"fp6">;
139 // XMM Registers, used by the various SSE instruction set extensions
140 def XMM0: Register<"xmm0">, DwarfRegNum<[17, 21, 21]>;
141 def XMM1: Register<"xmm1">, DwarfRegNum<[18, 22, 22]>;
142 def XMM2: Register<"xmm2">, DwarfRegNum<[19, 23, 23]>;
143 def XMM3: Register<"xmm3">, DwarfRegNum<[20, 24, 24]>;
144 def XMM4: Register<"xmm4">, DwarfRegNum<[21, 25, 25]>;
145 def XMM5: Register<"xmm5">, DwarfRegNum<[22, 26, 26]>;
146 def XMM6: Register<"xmm6">, DwarfRegNum<[23, 27, 27]>;
147 def XMM7: Register<"xmm7">, DwarfRegNum<[24, 28, 28]>;
150 def XMM8: Register<"xmm8">, DwarfRegNum<[25, -2, -2]>;
151 def XMM9: Register<"xmm9">, DwarfRegNum<[26, -2, -2]>;
152 def XMM10: Register<"xmm10">, DwarfRegNum<[27, -2, -2]>;
153 def XMM11: Register<"xmm11">, DwarfRegNum<[28, -2, -2]>;
154 def XMM12: Register<"xmm12">, DwarfRegNum<[29, -2, -2]>;
155 def XMM13: Register<"xmm13">, DwarfRegNum<[30, -2, -2]>;
156 def XMM14: Register<"xmm14">, DwarfRegNum<[31, -2, -2]>;
157 def XMM15: Register<"xmm15">, DwarfRegNum<[32, -2, -2]>;
159 // Floating point stack registers
160 def ST0 : Register<"st(0)">, DwarfRegNum<[33, 12, 11]>;
161 def ST1 : Register<"st(1)">, DwarfRegNum<[34, 13, 12]>;
162 def ST2 : Register<"st(2)">, DwarfRegNum<[35, 14, 13]>;
163 def ST3 : Register<"st(3)">, DwarfRegNum<[36, 15, 14]>;
164 def ST4 : Register<"st(4)">, DwarfRegNum<[37, 16, 15]>;
165 def ST5 : Register<"st(5)">, DwarfRegNum<[38, 17, 16]>;
166 def ST6 : Register<"st(6)">, DwarfRegNum<[39, 18, 17]>;
167 def ST7 : Register<"st(7)">, DwarfRegNum<[40, 19, 18]>;
169 // Status flags register
170 def EFLAGS : Register<"flags">;
173 def CS : Register<"cs">;
174 def DS : Register<"ds">;
175 def SS : Register<"ss">;
176 def ES : Register<"es">;
177 def FS : Register<"fs">;
178 def GS : Register<"gs">;
182 //===----------------------------------------------------------------------===//
183 // Subregister Set Definitions... now that we have all of the pieces, define the
184 // sub registers for each register.
187 def x86_subreg_8bit : PatLeaf<(i32 1)>;
188 def x86_subreg_16bit : PatLeaf<(i32 2)>;
189 def x86_subreg_32bit : PatLeaf<(i32 3)>;
191 def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
192 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
193 [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
194 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
196 // It's unclear if this subreg set is safe, given that not all registers
197 // in the class have an 'H' subreg.
198 // def : SubRegSet<2, [AX, CX, DX, BX],
199 // [AH, CH, DH, BH]>;
201 def : SubRegSet<1, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
202 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
203 [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
204 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
206 def : SubRegSet<2, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
207 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
208 [AX, CX, DX, BX, SP, BP, SI, DI,
209 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
212 def : SubRegSet<1, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
213 R8, R9, R10, R11, R12, R13, R14, R15],
214 [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
215 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
217 def : SubRegSet<2, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
218 R8, R9, R10, R11, R12, R13, R14, R15],
219 [AX, CX, DX, BX, SP, BP, SI, DI,
220 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
222 def : SubRegSet<3, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
223 R8, R9, R10, R11, R12, R13, R14, R15],
224 [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
225 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]>;
227 //===----------------------------------------------------------------------===//
228 // Register Class Definitions... now that we have all of the pieces, define the
229 // top-level register classes. The order specified in the register list is
230 // implicitly defined to be the register allocation order.
233 // List call-clobbered registers before callee-save registers. RBX, RBP, (and
234 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
235 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
237 // Allocate R12 and R13 last, as these require an extra byte when
238 // encoded in x86_64 instructions.
239 // FIXME: Allow AH, CH, DH, BH in 64-mode for non-REX instructions,
240 def GR8 : RegisterClass<"X86", [i8], 8,
241 [AL, CL, DL, BL, AH, CH, DH, BH, SIL, DIL, BPL, SPL,
242 R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B]> {
243 let MethodProtos = [{
244 iterator allocation_order_begin(const MachineFunction &MF) const;
245 iterator allocation_order_end(const MachineFunction &MF) const;
247 let MethodBodies = [{
248 // Does the function dedicate RBP / EBP to being a frame ptr?
249 // If so, don't allocate SPL or BPL.
250 static const unsigned X86_GR8_AO_64_fp[] = {
251 X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
252 X86::R8B, X86::R9B, X86::R10B, X86::R11B,
253 X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B
255 // If not, just don't allocate SPL.
256 static const unsigned X86_GR8_AO_64[] = {
257 X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
258 X86::R8B, X86::R9B, X86::R10B, X86::R11B,
259 X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL
261 // In 32-mode, none of the 8-bit registers aliases EBP or ESP.
262 static const unsigned X86_GR8_AO_32[] = {
263 X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH
267 GR8Class::allocation_order_begin(const MachineFunction &MF) const {
268 const TargetMachine &TM = MF.getTarget();
269 const TargetRegisterInfo *RI = TM.getRegisterInfo();
270 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
271 if (!Subtarget.is64Bit())
272 return X86_GR8_AO_32;
273 else if (RI->hasFP(MF))
274 return X86_GR8_AO_64_fp;
276 return X86_GR8_AO_64;
280 GR8Class::allocation_order_end(const MachineFunction &MF) const {
281 const TargetMachine &TM = MF.getTarget();
282 const TargetRegisterInfo *RI = TM.getRegisterInfo();
283 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
284 if (!Subtarget.is64Bit())
285 return X86_GR8_AO_32 + (sizeof(X86_GR8_AO_32) / sizeof(unsigned));
286 else if (RI->hasFP(MF))
287 return X86_GR8_AO_64_fp + (sizeof(X86_GR8_AO_64_fp) / sizeof(unsigned));
289 return X86_GR8_AO_64 + (sizeof(X86_GR8_AO_64) / sizeof(unsigned));
295 def GR16 : RegisterClass<"X86", [i16], 16,
296 [AX, CX, DX, SI, DI, BX, BP, SP,
297 R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W]> {
298 let SubRegClassList = [GR8];
299 let MethodProtos = [{
300 iterator allocation_order_begin(const MachineFunction &MF) const;
301 iterator allocation_order_end(const MachineFunction &MF) const;
303 let MethodBodies = [{
304 // Does the function dedicate RBP / EBP to being a frame ptr?
305 // If so, don't allocate SP or BP.
306 static const unsigned X86_GR16_AO_64_fp[] = {
307 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
308 X86::R8W, X86::R9W, X86::R10W, X86::R11W,
309 X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W
311 static const unsigned X86_GR16_AO_32_fp[] = {
312 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX
314 // If not, just don't allocate SP.
315 static const unsigned X86_GR16_AO_64[] = {
316 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
317 X86::R8W, X86::R9W, X86::R10W, X86::R11W,
318 X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::BP
320 static const unsigned X86_GR16_AO_32[] = {
321 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP
325 GR16Class::allocation_order_begin(const MachineFunction &MF) const {
326 const TargetMachine &TM = MF.getTarget();
327 const TargetRegisterInfo *RI = TM.getRegisterInfo();
328 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
329 if (Subtarget.is64Bit()) {
331 return X86_GR16_AO_64_fp;
333 return X86_GR16_AO_64;
336 return X86_GR16_AO_32_fp;
338 return X86_GR16_AO_32;
343 GR16Class::allocation_order_end(const MachineFunction &MF) const {
344 const TargetMachine &TM = MF.getTarget();
345 const TargetRegisterInfo *RI = TM.getRegisterInfo();
346 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
347 if (Subtarget.is64Bit()) {
349 return X86_GR16_AO_64_fp+(sizeof(X86_GR16_AO_64_fp)/sizeof(unsigned));
351 return X86_GR16_AO_64 + (sizeof(X86_GR16_AO_64) / sizeof(unsigned));
354 return X86_GR16_AO_32_fp+(sizeof(X86_GR16_AO_32_fp)/sizeof(unsigned));
356 return X86_GR16_AO_32 + (sizeof(X86_GR16_AO_32) / sizeof(unsigned));
363 def GR32 : RegisterClass<"X86", [i32], 32,
364 [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
365 R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> {
366 let SubRegClassList = [GR8, GR16];
367 let MethodProtos = [{
368 iterator allocation_order_begin(const MachineFunction &MF) const;
369 iterator allocation_order_end(const MachineFunction &MF) const;
371 let MethodBodies = [{
372 // Does the function dedicate RBP / EBP to being a frame ptr?
373 // If so, don't allocate ESP or EBP.
374 static const unsigned X86_GR32_AO_64_fp[] = {
375 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
376 X86::R8D, X86::R9D, X86::R10D, X86::R11D,
377 X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D
379 static const unsigned X86_GR32_AO_32_fp[] = {
380 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX
382 // If not, just don't allocate ESP.
383 static const unsigned X86_GR32_AO_64[] = {
384 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
385 X86::R8D, X86::R9D, X86::R10D, X86::R11D,
386 X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP
388 static const unsigned X86_GR32_AO_32[] = {
389 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP
393 GR32Class::allocation_order_begin(const MachineFunction &MF) const {
394 const TargetMachine &TM = MF.getTarget();
395 const TargetRegisterInfo *RI = TM.getRegisterInfo();
396 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
397 if (Subtarget.is64Bit()) {
399 return X86_GR32_AO_64_fp;
401 return X86_GR32_AO_64;
404 return X86_GR32_AO_32_fp;
406 return X86_GR32_AO_32;
411 GR32Class::allocation_order_end(const MachineFunction &MF) const {
412 const TargetMachine &TM = MF.getTarget();
413 const TargetRegisterInfo *RI = TM.getRegisterInfo();
414 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
415 if (Subtarget.is64Bit()) {
417 return X86_GR32_AO_64_fp+(sizeof(X86_GR32_AO_64_fp)/sizeof(unsigned));
419 return X86_GR32_AO_64 + (sizeof(X86_GR32_AO_64) / sizeof(unsigned));
422 return X86_GR32_AO_32_fp+(sizeof(X86_GR32_AO_32_fp)/sizeof(unsigned));
424 return X86_GR32_AO_32 + (sizeof(X86_GR32_AO_32) / sizeof(unsigned));
431 def GR64 : RegisterClass<"X86", [i64], 64,
432 [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
433 RBX, R14, R15, R12, R13, RBP, RSP]> {
434 let SubRegClassList = [GR8, GR16, GR32];
435 let MethodProtos = [{
436 iterator allocation_order_end(const MachineFunction &MF) const;
438 let MethodBodies = [{
440 GR64Class::allocation_order_end(const MachineFunction &MF) const {
441 const TargetMachine &TM = MF.getTarget();
442 const TargetRegisterInfo *RI = TM.getRegisterInfo();
443 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
444 if (!Subtarget.is64Bit())
445 return begin(); // None of these are allocatable in 32-bit.
446 if (RI->hasFP(MF)) // Does the function dedicate RBP to being a frame ptr?
447 return end()-2; // If so, don't allocate RSP or RBP
449 return end()-1; // If not, just don't allocate RSP
455 // GR16, GR32 subclasses which contain registers that have GR8 sub-registers.
456 // These should only be used for 32-bit mode.
457 def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
458 let SubRegClassList = [GR8];
460 def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
461 let SubRegClassList = [GR8, GR16];
464 // A class to support the 'A' assembler constraint: EAX then EDX.
465 def GRAD : RegisterClass<"X86", [i32], 32, [EAX, EDX]>;
467 // Scalar SSE2 floating point registers.
468 def FR32 : RegisterClass<"X86", [f32], 32,
469 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
470 XMM8, XMM9, XMM10, XMM11,
471 XMM12, XMM13, XMM14, XMM15]> {
472 let MethodProtos = [{
473 iterator allocation_order_end(const MachineFunction &MF) const;
475 let MethodBodies = [{
477 FR32Class::allocation_order_end(const MachineFunction &MF) const {
478 const TargetMachine &TM = MF.getTarget();
479 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
480 if (!Subtarget.is64Bit())
481 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
488 def FR64 : RegisterClass<"X86", [f64], 64,
489 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
490 XMM8, XMM9, XMM10, XMM11,
491 XMM12, XMM13, XMM14, XMM15]> {
492 let MethodProtos = [{
493 iterator allocation_order_end(const MachineFunction &MF) const;
495 let MethodBodies = [{
497 FR64Class::allocation_order_end(const MachineFunction &MF) const {
498 const TargetMachine &TM = MF.getTarget();
499 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
500 if (!Subtarget.is64Bit())
501 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
509 // FIXME: This sets up the floating point register files as though they are f64
510 // values, though they really are f80 values. This will cause us to spill
511 // values as 64-bit quantities instead of 80-bit quantities, which is much much
512 // faster on common hardware. In reality, this should be controlled by a
513 // command line option or something.
515 def RFP32 : RegisterClass<"X86",[f32], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
516 def RFP64 : RegisterClass<"X86",[f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
517 def RFP80 : RegisterClass<"X86",[f80], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
519 // Floating point stack registers (these are not allocatable by the
520 // register allocator - the floating point stackifier is responsible
521 // for transforming FPn allocations to STn registers)
522 def RST : RegisterClass<"X86", [f80, f64, f32], 32,
523 [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
524 let MethodProtos = [{
525 iterator allocation_order_end(const MachineFunction &MF) const;
527 let MethodBodies = [{
529 RSTClass::allocation_order_end(const MachineFunction &MF) const {
535 // Generic vector registers: VR64 and VR128.
536 def VR64 : RegisterClass<"X86", [v8i8, v4i16, v2i32, v1i64, v2f32], 64,
537 [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
538 def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128,
539 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
540 XMM8, XMM9, XMM10, XMM11,
541 XMM12, XMM13, XMM14, XMM15]> {
542 let MethodProtos = [{
543 iterator allocation_order_end(const MachineFunction &MF) const;
545 let MethodBodies = [{
547 VR128Class::allocation_order_end(const MachineFunction &MF) const {
548 const TargetMachine &TM = MF.getTarget();
549 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
550 if (!Subtarget.is64Bit())
551 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
558 // Status flags registers.
559 def CCR : RegisterClass<"X86", [i32], 32, [EFLAGS]> {
560 let CopyCost = -1; // Don't allow copying of status registers.