1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 Register file, defining the registers themselves,
11 // aliases between the registers, and the register classes built out of the
14 //===----------------------------------------------------------------------===//
16 class X86Reg<string n, bits<16> Enc, list<Register> subregs = []> : Register<n> {
17 let Namespace = "X86";
19 let SubRegs = subregs;
22 // Subregister indices.
23 let Namespace = "X86" in {
24 def sub_8bit : SubRegIndex<8>;
25 def sub_8bit_hi : SubRegIndex<8, 8>;
26 def sub_16bit : SubRegIndex<16>;
27 def sub_32bit : SubRegIndex<32>;
28 def sub_xmm : SubRegIndex<128>;
29 def sub_ymm : SubRegIndex<256>;
32 //===----------------------------------------------------------------------===//
33 // Register definitions...
36 // In the register alias definitions below, we define which registers alias
37 // which others. We only specify which registers the small registers alias,
38 // because the register file generator is smart enough to figure out that
39 // AL aliases AX if we tell it that AX aliased AL (for example).
41 // Dwarf numbering is different for 32-bit and 64-bit, and there are
42 // variations by target as well. Currently the first entry is for X86-64,
43 // second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux
44 // and debug information on X86-32/Darwin)
48 def AL : X86Reg<"al", 0>;
49 def DL : X86Reg<"dl", 2>;
50 def CL : X86Reg<"cl", 1>;
51 def BL : X86Reg<"bl", 3>;
53 // High registers. On x86-64, these cannot be used in any instruction
55 def AH : X86Reg<"ah", 4>;
56 def DH : X86Reg<"dh", 6>;
57 def CH : X86Reg<"ch", 5>;
58 def BH : X86Reg<"bh", 7>;
60 // X86-64 only, requires REX.
61 let CostPerUse = 1 in {
62 def SIL : X86Reg<"sil", 6>;
63 def DIL : X86Reg<"dil", 7>;
64 def BPL : X86Reg<"bpl", 5>;
65 def SPL : X86Reg<"spl", 4>;
66 def R8B : X86Reg<"r8b", 8>;
67 def R9B : X86Reg<"r9b", 9>;
68 def R10B : X86Reg<"r10b", 10>;
69 def R11B : X86Reg<"r11b", 11>;
70 def R12B : X86Reg<"r12b", 12>;
71 def R13B : X86Reg<"r13b", 13>;
72 def R14B : X86Reg<"r14b", 14>;
73 def R15B : X86Reg<"r15b", 15>;
77 let SubRegIndices = [sub_8bit, sub_8bit_hi], CoveredBySubRegs = 1 in {
78 def AX : X86Reg<"ax", 0, [AL,AH]>;
79 def DX : X86Reg<"dx", 2, [DL,DH]>;
80 def CX : X86Reg<"cx", 1, [CL,CH]>;
81 def BX : X86Reg<"bx", 3, [BL,BH]>;
83 let SubRegIndices = [sub_8bit] in {
84 def SI : X86Reg<"si", 6, [SIL]>;
85 def DI : X86Reg<"di", 7, [DIL]>;
86 def BP : X86Reg<"bp", 5, [BPL]>;
87 def SP : X86Reg<"sp", 4, [SPL]>;
89 def IP : X86Reg<"ip", 0>;
91 // X86-64 only, requires REX.
92 let SubRegIndices = [sub_8bit], CostPerUse = 1 in {
93 def R8W : X86Reg<"r8w", 8, [R8B]>;
94 def R9W : X86Reg<"r9w", 9, [R9B]>;
95 def R10W : X86Reg<"r10w", 10, [R10B]>;
96 def R11W : X86Reg<"r11w", 11, [R11B]>;
97 def R12W : X86Reg<"r12w", 12, [R12B]>;
98 def R13W : X86Reg<"r13w", 13, [R13B]>;
99 def R14W : X86Reg<"r14w", 14, [R14B]>;
100 def R15W : X86Reg<"r15w", 15, [R15B]>;
104 let SubRegIndices = [sub_16bit] in {
105 def EAX : X86Reg<"eax", 0, [AX]>, DwarfRegNum<[-2, 0, 0]>;
106 def EDX : X86Reg<"edx", 2, [DX]>, DwarfRegNum<[-2, 2, 2]>;
107 def ECX : X86Reg<"ecx", 1, [CX]>, DwarfRegNum<[-2, 1, 1]>;
108 def EBX : X86Reg<"ebx", 3, [BX]>, DwarfRegNum<[-2, 3, 3]>;
109 def ESI : X86Reg<"esi", 6, [SI]>, DwarfRegNum<[-2, 6, 6]>;
110 def EDI : X86Reg<"edi", 7, [DI]>, DwarfRegNum<[-2, 7, 7]>;
111 def EBP : X86Reg<"ebp", 5, [BP]>, DwarfRegNum<[-2, 4, 5]>;
112 def ESP : X86Reg<"esp", 4, [SP]>, DwarfRegNum<[-2, 5, 4]>;
113 def EIP : X86Reg<"eip", 0, [IP]>, DwarfRegNum<[-2, 8, 8]>;
115 // X86-64 only, requires REX
116 let CostPerUse = 1 in {
117 def R8D : X86Reg<"r8d", 8, [R8W]>;
118 def R9D : X86Reg<"r9d", 9, [R9W]>;
119 def R10D : X86Reg<"r10d", 10, [R10W]>;
120 def R11D : X86Reg<"r11d", 11, [R11W]>;
121 def R12D : X86Reg<"r12d", 12, [R12W]>;
122 def R13D : X86Reg<"r13d", 13, [R13W]>;
123 def R14D : X86Reg<"r14d", 14, [R14W]>;
124 def R15D : X86Reg<"r15d", 15, [R15W]>;
127 // 64-bit registers, X86-64 only
128 let SubRegIndices = [sub_32bit] in {
129 def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>;
130 def RDX : X86Reg<"rdx", 2, [EDX]>, DwarfRegNum<[1, -2, -2]>;
131 def RCX : X86Reg<"rcx", 1, [ECX]>, DwarfRegNum<[2, -2, -2]>;
132 def RBX : X86Reg<"rbx", 3, [EBX]>, DwarfRegNum<[3, -2, -2]>;
133 def RSI : X86Reg<"rsi", 6, [ESI]>, DwarfRegNum<[4, -2, -2]>;
134 def RDI : X86Reg<"rdi", 7, [EDI]>, DwarfRegNum<[5, -2, -2]>;
135 def RBP : X86Reg<"rbp", 5, [EBP]>, DwarfRegNum<[6, -2, -2]>;
136 def RSP : X86Reg<"rsp", 4, [ESP]>, DwarfRegNum<[7, -2, -2]>;
138 // These also require REX.
139 let CostPerUse = 1 in {
140 def R8 : X86Reg<"r8", 8, [R8D]>, DwarfRegNum<[ 8, -2, -2]>;
141 def R9 : X86Reg<"r9", 9, [R9D]>, DwarfRegNum<[ 9, -2, -2]>;
142 def R10 : X86Reg<"r10", 10, [R10D]>, DwarfRegNum<[10, -2, -2]>;
143 def R11 : X86Reg<"r11", 11, [R11D]>, DwarfRegNum<[11, -2, -2]>;
144 def R12 : X86Reg<"r12", 12, [R12D]>, DwarfRegNum<[12, -2, -2]>;
145 def R13 : X86Reg<"r13", 13, [R13D]>, DwarfRegNum<[13, -2, -2]>;
146 def R14 : X86Reg<"r14", 14, [R14D]>, DwarfRegNum<[14, -2, -2]>;
147 def R15 : X86Reg<"r15", 15, [R15D]>, DwarfRegNum<[15, -2, -2]>;
148 def RIP : X86Reg<"rip", 0, [EIP]>, DwarfRegNum<[16, -2, -2]>;
151 // MMX Registers. These are actually aliased to ST0 .. ST7
152 def MM0 : X86Reg<"mm0", 0>, DwarfRegNum<[41, 29, 29]>;
153 def MM1 : X86Reg<"mm1", 1>, DwarfRegNum<[42, 30, 30]>;
154 def MM2 : X86Reg<"mm2", 2>, DwarfRegNum<[43, 31, 31]>;
155 def MM3 : X86Reg<"mm3", 3>, DwarfRegNum<[44, 32, 32]>;
156 def MM4 : X86Reg<"mm4", 4>, DwarfRegNum<[45, 33, 33]>;
157 def MM5 : X86Reg<"mm5", 5>, DwarfRegNum<[46, 34, 34]>;
158 def MM6 : X86Reg<"mm6", 6>, DwarfRegNum<[47, 35, 35]>;
159 def MM7 : X86Reg<"mm7", 7>, DwarfRegNum<[48, 36, 36]>;
161 // Pseudo Floating Point registers
162 def FP0 : X86Reg<"fp0", 0>;
163 def FP1 : X86Reg<"fp1", 0>;
164 def FP2 : X86Reg<"fp2", 0>;
165 def FP3 : X86Reg<"fp3", 0>;
166 def FP4 : X86Reg<"fp4", 0>;
167 def FP5 : X86Reg<"fp5", 0>;
168 def FP6 : X86Reg<"fp6", 0>;
170 // XMM Registers, used by the various SSE instruction set extensions.
171 def XMM0: X86Reg<"xmm0", 0>, DwarfRegNum<[17, 21, 21]>;
172 def XMM1: X86Reg<"xmm1", 1>, DwarfRegNum<[18, 22, 22]>;
173 def XMM2: X86Reg<"xmm2", 2>, DwarfRegNum<[19, 23, 23]>;
174 def XMM3: X86Reg<"xmm3", 3>, DwarfRegNum<[20, 24, 24]>;
175 def XMM4: X86Reg<"xmm4", 4>, DwarfRegNum<[21, 25, 25]>;
176 def XMM5: X86Reg<"xmm5", 5>, DwarfRegNum<[22, 26, 26]>;
177 def XMM6: X86Reg<"xmm6", 6>, DwarfRegNum<[23, 27, 27]>;
178 def XMM7: X86Reg<"xmm7", 7>, DwarfRegNum<[24, 28, 28]>;
181 let CostPerUse = 1 in {
182 def XMM8: X86Reg<"xmm8", 8>, DwarfRegNum<[25, -2, -2]>;
183 def XMM9: X86Reg<"xmm9", 9>, DwarfRegNum<[26, -2, -2]>;
184 def XMM10: X86Reg<"xmm10", 10>, DwarfRegNum<[27, -2, -2]>;
185 def XMM11: X86Reg<"xmm11", 11>, DwarfRegNum<[28, -2, -2]>;
186 def XMM12: X86Reg<"xmm12", 12>, DwarfRegNum<[29, -2, -2]>;
187 def XMM13: X86Reg<"xmm13", 13>, DwarfRegNum<[30, -2, -2]>;
188 def XMM14: X86Reg<"xmm14", 14>, DwarfRegNum<[31, -2, -2]>;
189 def XMM15: X86Reg<"xmm15", 15>, DwarfRegNum<[32, -2, -2]>;
191 def XMM16: X86Reg<"xmm16", 16>, DwarfRegNum<[60, -2, -2]>;
192 def XMM17: X86Reg<"xmm17", 17>, DwarfRegNum<[61, -2, -2]>;
193 def XMM18: X86Reg<"xmm18", 18>, DwarfRegNum<[62, -2, -2]>;
194 def XMM19: X86Reg<"xmm19", 19>, DwarfRegNum<[63, -2, -2]>;
195 def XMM20: X86Reg<"xmm20", 20>, DwarfRegNum<[64, -2, -2]>;
196 def XMM21: X86Reg<"xmm21", 21>, DwarfRegNum<[65, -2, -2]>;
197 def XMM22: X86Reg<"xmm22", 22>, DwarfRegNum<[66, -2, -2]>;
198 def XMM23: X86Reg<"xmm23", 23>, DwarfRegNum<[67, -2, -2]>;
199 def XMM24: X86Reg<"xmm24", 24>, DwarfRegNum<[68, -2, -2]>;
200 def XMM25: X86Reg<"xmm25", 25>, DwarfRegNum<[69, -2, -2]>;
201 def XMM26: X86Reg<"xmm26", 26>, DwarfRegNum<[70, -2, -2]>;
202 def XMM27: X86Reg<"xmm27", 27>, DwarfRegNum<[71, -2, -2]>;
203 def XMM28: X86Reg<"xmm28", 28>, DwarfRegNum<[72, -2, -2]>;
204 def XMM29: X86Reg<"xmm29", 29>, DwarfRegNum<[73, -2, -2]>;
205 def XMM30: X86Reg<"xmm30", 30>, DwarfRegNum<[74, -2, -2]>;
206 def XMM31: X86Reg<"xmm31", 31>, DwarfRegNum<[75, -2, -2]>;
210 // YMM0-15 registers, used by AVX instructions and
211 // YMM16-31 registers, used by AVX-512 instructions.
212 let SubRegIndices = [sub_xmm] in {
213 foreach Index = 0-31 in {
214 def YMM#Index : X86Reg<"ymm"#Index, Index, [!cast<X86Reg>("XMM"#Index)]>,
215 DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>;
219 // ZMM Registers, used by AVX-512 instructions.
220 let SubRegIndices = [sub_ymm] in {
221 foreach Index = 0-31 in {
222 def ZMM#Index : X86Reg<"zmm"#Index, Index, [!cast<X86Reg>("YMM"#Index)]>,
223 DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>;
227 // Mask Registers, used by AVX-512 instructions.
228 def K0 : X86Reg<"k0", 0>, DwarfRegNum<[118, -2, -2]>;
229 def K1 : X86Reg<"k1", 1>, DwarfRegNum<[119, -2, -2]>;
230 def K2 : X86Reg<"k2", 2>, DwarfRegNum<[120, -2, -2]>;
231 def K3 : X86Reg<"k3", 3>, DwarfRegNum<[121, -2, -2]>;
232 def K4 : X86Reg<"k4", 4>, DwarfRegNum<[122, -2, -2]>;
233 def K5 : X86Reg<"k5", 5>, DwarfRegNum<[123, -2, -2]>;
234 def K6 : X86Reg<"k6", 6>, DwarfRegNum<[124, -2, -2]>;
235 def K7 : X86Reg<"k7", 7>, DwarfRegNum<[125, -2, -2]>;
237 class STRegister<string n, bits<16> Enc, list<Register> A> : X86Reg<n, Enc> {
241 // Floating point stack registers. These don't map one-to-one to the FP
242 // pseudo registers, but we still mark them as aliasing FP registers. That
243 // way both kinds can be live without exceeding the stack depth. ST registers
244 // are only live around inline assembly.
245 def ST0 : STRegister<"st(0)", 0, []>, DwarfRegNum<[33, 12, 11]>;
246 def ST1 : STRegister<"st(1)", 1, [FP6]>, DwarfRegNum<[34, 13, 12]>;
247 def ST2 : STRegister<"st(2)", 2, [FP5]>, DwarfRegNum<[35, 14, 13]>;
248 def ST3 : STRegister<"st(3)", 3, [FP4]>, DwarfRegNum<[36, 15, 14]>;
249 def ST4 : STRegister<"st(4)", 4, [FP3]>, DwarfRegNum<[37, 16, 15]>;
250 def ST5 : STRegister<"st(5)", 5, [FP2]>, DwarfRegNum<[38, 17, 16]>;
251 def ST6 : STRegister<"st(6)", 6, [FP1]>, DwarfRegNum<[39, 18, 17]>;
252 def ST7 : STRegister<"st(7)", 7, [FP0]>, DwarfRegNum<[40, 19, 18]>;
254 // Floating-point status word
255 def FPSW : X86Reg<"fpsw", 0>;
257 // Status flags register
258 def EFLAGS : X86Reg<"flags", 0>;
261 def CS : X86Reg<"cs", 1>;
262 def DS : X86Reg<"ds", 3>;
263 def SS : X86Reg<"ss", 2>;
264 def ES : X86Reg<"es", 0>;
265 def FS : X86Reg<"fs", 4>;
266 def GS : X86Reg<"gs", 5>;
269 def DR0 : X86Reg<"dr0", 0>;
270 def DR1 : X86Reg<"dr1", 1>;
271 def DR2 : X86Reg<"dr2", 2>;
272 def DR3 : X86Reg<"dr3", 3>;
273 def DR4 : X86Reg<"dr4", 4>;
274 def DR5 : X86Reg<"dr5", 5>;
275 def DR6 : X86Reg<"dr6", 6>;
276 def DR7 : X86Reg<"dr7", 7>;
279 def CR0 : X86Reg<"cr0", 0>;
280 def CR1 : X86Reg<"cr1", 1>;
281 def CR2 : X86Reg<"cr2", 2>;
282 def CR3 : X86Reg<"cr3", 3>;
283 def CR4 : X86Reg<"cr4", 4>;
284 def CR5 : X86Reg<"cr5", 5>;
285 def CR6 : X86Reg<"cr6", 6>;
286 def CR7 : X86Reg<"cr7", 7>;
287 def CR8 : X86Reg<"cr8", 8>;
288 def CR9 : X86Reg<"cr9", 9>;
289 def CR10 : X86Reg<"cr10", 10>;
290 def CR11 : X86Reg<"cr11", 11>;
291 def CR12 : X86Reg<"cr12", 12>;
292 def CR13 : X86Reg<"cr13", 13>;
293 def CR14 : X86Reg<"cr14", 14>;
294 def CR15 : X86Reg<"cr15", 15>;
296 // Pseudo index registers
297 def EIZ : X86Reg<"eiz", 4>;
298 def RIZ : X86Reg<"riz", 4>;
301 //===----------------------------------------------------------------------===//
302 // Register Class Definitions... now that we have all of the pieces, define the
303 // top-level register classes. The order specified in the register list is
304 // implicitly defined to be the register allocation order.
307 // List call-clobbered registers before callee-save registers. RBX, RBP, (and
308 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
309 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
311 // Allocate R12 and R13 last, as these require an extra byte when
312 // encoded in x86_64 instructions.
313 // FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in
314 // 64-bit mode. The main complication is that they cannot be encoded in an
315 // instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc.
316 // require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d"
317 // cannot be encoded.
318 def GR8 : RegisterClass<"X86", [i8], 8,
319 (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
320 R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B)> {
321 let AltOrders = [(sub GR8, AH, BH, CH, DH)];
322 let AltOrderSelect = [{
323 return MF.getTarget().getSubtarget<X86Subtarget>().is64Bit();
327 def GR16 : RegisterClass<"X86", [i16], 16,
328 (add AX, CX, DX, SI, DI, BX, BP, SP,
329 R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W)>;
331 def GR32 : RegisterClass<"X86", [i32], 32,
332 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
333 R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D)>;
335 // GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
336 // RIP isn't really a register and it can't be used anywhere except in an
337 // address, but it doesn't cause trouble.
338 def GR64 : RegisterClass<"X86", [i64], 64,
339 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
340 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
342 // Segment registers for use by MOV instructions (and others) that have a
343 // segment register as one operand. Always contain a 16-bit segment
345 def SEGMENT_REG : RegisterClass<"X86", [i16], 16, (add CS, DS, SS, ES, FS, GS)>;
348 def DEBUG_REG : RegisterClass<"X86", [i32], 32, (sequence "DR%u", 0, 7)>;
350 // Control registers.
351 def CONTROL_REG : RegisterClass<"X86", [i64], 64, (sequence "CR%u", 0, 15)>;
353 // GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of
354 // GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d"
355 // registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers
356 // that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD,
357 // and GR64_ABCD are classes for registers that support 8-bit h-register
359 def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, (add AL, CL, DL, BL)>;
360 def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>;
361 def GR16_ABCD : RegisterClass<"X86", [i16], 16, (add AX, CX, DX, BX)>;
362 def GR32_ABCD : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, EBX)>;
363 def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>;
364 def GR32_TC : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX)>;
365 def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI,
367 def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX,
370 // GR8_NOREX - GR8 registers which do not require a REX prefix.
371 def GR8_NOREX : RegisterClass<"X86", [i8], 8,
372 (add AL, CL, DL, AH, CH, DH, BL, BH)> {
373 let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)];
374 let AltOrderSelect = [{
375 return MF.getTarget().getSubtarget<X86Subtarget>().is64Bit();
378 // GR16_NOREX - GR16 registers which do not require a REX prefix.
379 def GR16_NOREX : RegisterClass<"X86", [i16], 16,
380 (add AX, CX, DX, SI, DI, BX, BP, SP)>;
381 // GR32_NOREX - GR32 registers which do not require a REX prefix.
382 def GR32_NOREX : RegisterClass<"X86", [i32], 32,
383 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP)>;
384 // GR64_NOREX - GR64 registers which do not require a REX prefix.
385 def GR64_NOREX : RegisterClass<"X86", [i64], 64,
386 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
388 // GR32_NOAX - GR32 registers except EAX. Used by AddRegFrm of XCHG32 in 64-bit
389 // mode to prevent encoding using the 0x90 NOP encoding. xchg %eax, %eax needs
390 // to clear upper 32-bits of RAX so is not a NOP.
391 def GR32_NOAX : RegisterClass<"X86", [i32], 32, (sub GR32, EAX)>;
393 // GR32_NOSP - GR32 registers except ESP.
394 def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)>;
396 // GR64_NOSP - GR64 registers except RSP (and RIP).
397 def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>;
399 // GR32_NOREX_NOSP - GR32 registers which do not require a REX prefix except
401 def GR32_NOREX_NOSP : RegisterClass<"X86", [i32], 32,
402 (and GR32_NOREX, GR32_NOSP)>;
404 // GR64_NOREX_NOSP - GR64_NOREX registers except RSP.
405 def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64,
406 (and GR64_NOREX, GR64_NOSP)>;
408 // A class to support the 'A' assembler constraint: EAX then EDX.
409 def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>;
411 // Scalar SSE2 floating point registers.
412 def FR32 : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 15)>;
414 def FR64 : RegisterClass<"X86", [f64], 64, (add FR32)>;
417 // FIXME: This sets up the floating point register files as though they are f64
418 // values, though they really are f80 values. This will cause us to spill
419 // values as 64-bit quantities instead of 80-bit quantities, which is much much
420 // faster on common hardware. In reality, this should be controlled by a
421 // command line option or something.
423 def RFP32 : RegisterClass<"X86",[f32], 32, (sequence "FP%u", 0, 6)>;
424 def RFP64 : RegisterClass<"X86",[f64], 32, (add RFP32)>;
425 def RFP80 : RegisterClass<"X86",[f80], 32, (add RFP32)>;
427 // Floating point stack registers (these are not allocatable by the
428 // register allocator - the floating point stackifier is responsible
429 // for transforming FPn allocations to STn registers)
430 def RST : RegisterClass<"X86", [f80, f64, f32], 32, (sequence "ST%u", 0, 7)> {
431 let isAllocatable = 0;
434 // Generic vector registers: VR64 and VR128.
435 def VR64: RegisterClass<"X86", [x86mmx], 64, (sequence "MM%u", 0, 7)>;
436 def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
438 def VR256 : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
439 256, (sequence "YMM%u", 0, 15)>;
441 // Status flags registers.
442 def CCR : RegisterClass<"X86", [i32], 32, (add EFLAGS)> {
443 let CopyCost = -1; // Don't allow copying of status registers.
444 let isAllocatable = 0;
446 def FPCCR : RegisterClass<"X86", [i16], 16, (add FPSW)> {
447 let CopyCost = -1; // Don't allow copying of status registers.
448 let isAllocatable = 0;
451 // AVX-512 vector/mask registers.
452 def VR512 : RegisterClass<"X86", [v16f32, v8f64, v16i32, v8i64], 512,
453 (sequence "ZMM%u", 0, 31)>;
455 // Scalar AVX-512 floating point registers.
456 def FR32X : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 31)>;
458 def FR64X : RegisterClass<"X86", [f64], 64, (add FR32X)>;
460 // Extended VR128 and VR256 for AVX-512 instructions
461 def VR128X : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
463 def VR256X : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
464 256, (sequence "YMM%u", 0, 31)>;
466 // The size of the all masked registers is 16 bit because we have only one
467 // KMOVW istruction that can store this register in memory, and it writes 2 bytes
468 def VK1 : RegisterClass<"X86", [i1], 16, (sequence "K%u", 0, 7)>;
469 def VK8 : RegisterClass<"X86", [v8i1], 16, (sequence "K%u", 0, 7)>;
470 def VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)>;
472 def VK1WM : RegisterClass<"X86", [i1], 16, (sub VK1, K0)>;
473 def VK8WM : RegisterClass<"X86", [v8i1], 16, (sub VK8, K0)>;
474 def VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)>;