1 //===- X86RegisterInfo.td - Describe the X86 Register File ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 Register file, defining the registers themselves,
11 // aliases between the registers, and the register classes built out of the
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Register definitions...
19 let Namespace = "X86" in {
21 // In the register alias definitions below, we define which registers alias
22 // which others. We only specify which registers the small registers alias,
23 // because the register file generator is smart enough to figure out that
24 // AL aliases AX if we tell it that AX aliased AL (for example).
27 def EAX : Register<"EAX">; def ECX : Register<"ECX">;
28 def EDX : Register<"EDX">; def EBX : Register<"EBX">;
29 def ESP : Register<"ESP">; def EBP : Register<"EBP">;
30 def ESI : Register<"ESI">; def EDI : Register<"EDI">;
33 def AX : RegisterGroup<"AX", [EAX]>; def CX : RegisterGroup<"CX", [ECX]>;
34 def DX : RegisterGroup<"DX", [EDX]>; def BX : RegisterGroup<"BX", [EBX]>;
35 def SP : RegisterGroup<"SP", [ESP]>; def BP : RegisterGroup<"BP", [EBP]>;
36 def SI : RegisterGroup<"SI", [ESI]>; def DI : RegisterGroup<"DI", [EDI]>;
39 def AL : RegisterGroup<"AL", [AX,EAX]>; def CL : RegisterGroup<"CL",[CX,ECX]>;
40 def DL : RegisterGroup<"DL", [DX,EDX]>; def BL : RegisterGroup<"BL",[BX,EBX]>;
41 def AH : RegisterGroup<"AH", [AX,EAX]>; def CH : RegisterGroup<"CH",[CX,ECX]>;
42 def DH : RegisterGroup<"DH", [DX,EDX]>; def BH : RegisterGroup<"BH",[BX,EBX]>;
44 // Pseudo Floating Point registers
45 def FP0 : Register<"FP0">; def FP1 : Register<"FP1">;
46 def FP2 : Register<"FP2">; def FP3 : Register<"FP3">;
47 def FP4 : Register<"FP4">; def FP5 : Register<"FP5">;
48 def FP6 : Register<"FP6">;
50 // XMM Registers, used by the various SSE instruction set extensions
51 def XMM0: Register<"XMM0">; def XMM1: Register<"XMM1">;
52 def XMM2: Register<"XMM2">; def XMM3: Register<"XMM3">;
53 def XMM4: Register<"XMM4">; def XMM5: Register<"XMM5">;
54 def XMM6: Register<"XMM6">; def XMM7: Register<"XMM7">;
56 // Floating point stack registers
57 def ST0 : Register<"ST(0)">; def ST1 : Register<"ST(1)">;
58 def ST2 : Register<"ST(2)">; def ST3 : Register<"ST(3)">;
59 def ST4 : Register<"ST(4)">; def ST5 : Register<"ST(5)">;
60 def ST6 : Register<"ST(6)">; def ST7 : Register<"ST(7)">;
62 // Flags, Segment registers, etc...
63 def STATUS : Register<"STATUS">;
66 //===----------------------------------------------------------------------===//
67 // Register Class Definitions... now that we have all of the pieces, define the
68 // top-level register classes. The order specified in the register list is
69 // implicitly defined to be the register allocation order.
72 // List AL,CL,DL before AH,CH,DH, as X86 processors often suffer from false
73 // dependences between upper and lower parts of the register. BL and BH are
74 // last because they are call clobbered. Both Athlon and P4 chips suffer this
76 def R8 : RegisterClass<"X86", [i8], 8, [AL, CL, DL, AH, CH, DH, BL, BH]>;
78 def R16 : RegisterClass<"X86", [i16], 16, [AX, CX, DX, SI, DI, BX, BP, SP]> {
80 iterator allocation_order_end(MachineFunction &MF) const;
84 R16Class::allocation_order_end(MachineFunction &MF) const {
85 if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
86 return end()-2; // If so, don't allocate SP or BP
88 return end()-1; // If not, just don't allocate SP
93 def R32 : RegisterClass<"X86", [i32], 32,
94 [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
96 iterator allocation_order_end(MachineFunction &MF) const;
100 R32Class::allocation_order_end(MachineFunction &MF) const {
101 if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
102 return end()-2; // If so, don't allocate ESP or EBP
104 return end()-1; // If not, just don't allocate ESP
109 // V4F4, the 4 x f32 class, and V2F8, the 2 x f64 class, which we will use for
110 // Scalar SSE2 floating point support.
111 def V4F4 : RegisterClass<"X86", [f32], 32,
112 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
113 def V2F8 : RegisterClass<"X86", [f64], 64,
114 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
116 // FIXME: This sets up the floating point register files as though they are f64
117 // values, though they really are f80 values. This will cause us to spill
118 // values as 64-bit quantities instead of 80-bit quantities, which is much much
119 // faster on common hardware. In reality, this should be controlled by a
120 // command line option or something.
122 def RFP : RegisterClass<"X86", [f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
124 // Floating point stack registers (these are not allocatable by the
125 // register allocator - the floating point stackifier is responsible
126 // for transforming FPn allocations to STn registers)
127 def RST : RegisterClass<"X86", [f64], 32,
128 [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
129 let MethodProtos = [{
130 iterator allocation_order_end(MachineFunction &MF) const;
132 let MethodBodies = [{
134 RSTClass::allocation_order_end(MachineFunction &MF) const {
140 def FLAGS_REGS : RegisterClass<"X86", [FlagVT], 32, [STATUS]> {