1 //=- X86SchedHaswell.td - X86 Haswell Scheduling -------------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the machine model for Haswell to support instruction
11 // scheduling and other instruction cost heuristics.
13 //===----------------------------------------------------------------------===//
15 def HaswellModel : SchedMachineModel {
16 // All x86 instructions are modeled as a single micro-op, and HW can decode 4
17 // instructions per cycle.
19 let MicroOpBufferSize = 192; // Based on the reorder buffer.
21 let MispredictPenalty = 16;
23 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
24 let LoopMicroOpBufferSize = 50;
26 // FIXME: SSE4 and AVX are unimplemented. This flag is set to allow
27 // the scheduler to assign a default model to unrecognized opcodes.
28 let CompleteModel = 0;
31 let SchedModel = HaswellModel in {
33 // Haswell can issue micro-ops to 8 different ports in one cycle.
35 // Ports 0, 1, 5, and 6 handle all computation.
36 // Port 4 gets the data half of stores. Store data can be available later than
37 // the store address, but since we don't model the latency of stores, we can
39 // Ports 2 and 3 are identical. They handle loads and the address half of
40 // stores. Port 7 can handle address calculations.
41 def HWPort0 : ProcResource<1>;
42 def HWPort1 : ProcResource<1>;
43 def HWPort2 : ProcResource<1>;
44 def HWPort3 : ProcResource<1>;
45 def HWPort4 : ProcResource<1>;
46 def HWPort5 : ProcResource<1>;
47 def HWPort6 : ProcResource<1>;
48 def HWPort7 : ProcResource<1>;
50 // Many micro-ops are capable of issuing on multiple ports.
51 def HWPort23 : ProcResGroup<[HWPort2, HWPort3]>;
52 def HWPort237 : ProcResGroup<[HWPort2, HWPort3, HWPort7]>;
53 def HWPort05 : ProcResGroup<[HWPort0, HWPort5]>;
54 def HWPort06 : ProcResGroup<[HWPort0, HWPort6]>;
55 def HWPort15 : ProcResGroup<[HWPort1, HWPort5]>;
56 def HWPort16 : ProcResGroup<[HWPort1, HWPort6]>;
57 def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>;
58 def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>;
60 // 60 Entry Unified Scheduler
61 def HWPortAny : ProcResGroup<[HWPort0, HWPort1, HWPort2, HWPort3, HWPort4,
62 HWPort5, HWPort6, HWPort7]> {
66 // Integer division issued on port 0.
67 def HWDivider : ProcResource<1>;
69 // Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4
70 // cycles after the memory operand.
71 def : ReadAdvance<ReadAfterLd, 4>;
73 // Many SchedWrites are defined in pairs with and without a folded load.
74 // Instructions with folded loads are usually micro-fused, so they only appear
75 // as two micro-ops when queued in the reservation station.
76 // This multiclass defines the resource usage for variants with and without
78 multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW,
79 ProcResourceKind ExePort,
81 // Register variant is using a single cycle on ExePort.
82 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
84 // Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the
86 def : WriteRes<SchedRW.Folded, [HWPort23, ExePort]> {
87 let Latency = !add(Lat, 4);
91 // A folded store needs a cycle on port 4 for the store data, but it does not
92 // need an extra port 2/3 cycle to recompute the address.
93 def : WriteRes<WriteRMW, [HWPort4]>;
97 def : WriteRes<WriteStore, [HWPort237, HWPort4]>;
98 def : WriteRes<WriteLoad, [HWPort23]> { let Latency = 4; }
99 def : WriteRes<WriteMove, [HWPort0156]>;
100 def : WriteRes<WriteZero, []>;
102 defm : HWWriteResPair<WriteALU, HWPort0156, 1>;
103 defm : HWWriteResPair<WriteIMul, HWPort1, 3>;
104 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
105 defm : HWWriteResPair<WriteShift, HWPort06, 1>;
106 defm : HWWriteResPair<WriteJump, HWPort06, 1>;
108 // This is for simple LEAs with one or two input operands.
109 // The complex ones can only execute on port 1, and they require two cycles on
110 // the port to read all inputs. We don't model that.
111 def : WriteRes<WriteLEA, [HWPort15]>;
113 // This is quite rough, latency depends on the dividend.
114 def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> {
116 let ResourceCycles = [1, 10];
118 def : WriteRes<WriteIDivLd, [HWPort23, HWPort0, HWDivider]> {
120 let ResourceCycles = [1, 1, 10];
123 // Scalar and vector floating point.
124 defm : HWWriteResPair<WriteFAdd, HWPort1, 3>;
125 defm : HWWriteResPair<WriteFMul, HWPort0, 5>;
126 defm : HWWriteResPair<WriteFDiv, HWPort0, 12>; // 10-14 cycles.
127 defm : HWWriteResPair<WriteFRcp, HWPort0, 5>;
128 defm : HWWriteResPair<WriteFSqrt, HWPort0, 15>;
129 defm : HWWriteResPair<WriteCvtF2I, HWPort1, 3>;
130 defm : HWWriteResPair<WriteCvtI2F, HWPort1, 4>;
131 defm : HWWriteResPair<WriteCvtF2F, HWPort1, 3>;
132 defm : HWWriteResPair<WriteFShuffle, HWPort5, 1>;
133 defm : HWWriteResPair<WriteFBlend, HWPort015, 1>;
134 defm : HWWriteResPair<WriteFShuffle256, HWPort5, 3>;
136 def : WriteRes<WriteFVarBlend, [HWPort5]> {
138 let ResourceCycles = [2];
140 def : WriteRes<WriteFVarBlendLd, [HWPort5, HWPort23]> {
142 let ResourceCycles = [2, 1];
145 // Vector integer operations.
146 defm : HWWriteResPair<WriteVecShift, HWPort0, 1>;
147 defm : HWWriteResPair<WriteVecLogic, HWPort015, 1>;
148 defm : HWWriteResPair<WriteVecALU, HWPort15, 1>;
149 defm : HWWriteResPair<WriteVecIMul, HWPort0, 5>;
150 defm : HWWriteResPair<WriteShuffle, HWPort5, 1>;
151 defm : HWWriteResPair<WriteBlend, HWPort15, 1>;
152 defm : HWWriteResPair<WriteShuffle256, HWPort5, 3>;
154 def : WriteRes<WriteVarBlend, [HWPort5]> {
156 let ResourceCycles = [2];
158 def : WriteRes<WriteVarBlendLd, [HWPort5, HWPort23]> {
160 let ResourceCycles = [2, 1];
163 def : WriteRes<WriteVarVecShift, [HWPort0, HWPort5]> {
165 let ResourceCycles = [2, 1];
167 def : WriteRes<WriteVarVecShiftLd, [HWPort0, HWPort5, HWPort23]> {
169 let ResourceCycles = [2, 1, 1];
172 def : WriteRes<WriteMPSAD, [HWPort0, HWPort5]> {
174 let ResourceCycles = [1, 2];
176 def : WriteRes<WriteMPSADLd, [HWPort23, HWPort0, HWPort5]> {
178 let ResourceCycles = [1, 1, 2];
181 // String instructions.
182 // Packed Compare Implicit Length Strings, Return Mask
183 def : WriteRes<WritePCmpIStrM, [HWPort0]> {
185 let ResourceCycles = [3];
187 def : WriteRes<WritePCmpIStrMLd, [HWPort0, HWPort23]> {
189 let ResourceCycles = [3, 1];
192 // Packed Compare Explicit Length Strings, Return Mask
193 def : WriteRes<WritePCmpEStrM, [HWPort0, HWPort16, HWPort5]> {
195 let ResourceCycles = [3, 2, 4];
197 def : WriteRes<WritePCmpEStrMLd, [HWPort05, HWPort16, HWPort23]> {
199 let ResourceCycles = [6, 2, 1];
202 // Packed Compare Implicit Length Strings, Return Index
203 def : WriteRes<WritePCmpIStrI, [HWPort0]> {
205 let ResourceCycles = [3];
207 def : WriteRes<WritePCmpIStrILd, [HWPort0, HWPort23]> {
209 let ResourceCycles = [3, 1];
212 // Packed Compare Explicit Length Strings, Return Index
213 def : WriteRes<WritePCmpEStrI, [HWPort05, HWPort16]> {
215 let ResourceCycles = [6, 2];
217 def : WriteRes<WritePCmpEStrILd, [HWPort0, HWPort16, HWPort5, HWPort23]> {
219 let ResourceCycles = [3, 2, 2, 1];
223 def : WriteRes<WriteAESDecEnc, [HWPort5]> {
225 let ResourceCycles = [1];
227 def : WriteRes<WriteAESDecEncLd, [HWPort5, HWPort23]> {
229 let ResourceCycles = [1, 1];
232 def : WriteRes<WriteAESIMC, [HWPort5]> {
234 let ResourceCycles = [2];
236 def : WriteRes<WriteAESIMCLd, [HWPort5, HWPort23]> {
238 let ResourceCycles = [2, 1];
241 def : WriteRes<WriteAESKeyGen, [HWPort0, HWPort5]> {
243 let ResourceCycles = [2, 8];
245 def : WriteRes<WriteAESKeyGenLd, [HWPort0, HWPort5, HWPort23]> {
247 let ResourceCycles = [2, 7, 1];
250 // Carry-less multiplication instructions.
251 def : WriteRes<WriteCLMul, [HWPort0, HWPort5]> {
253 let ResourceCycles = [2, 1];
255 def : WriteRes<WriteCLMulLd, [HWPort0, HWPort5, HWPort23]> {
257 let ResourceCycles = [2, 1, 1];
260 def : WriteRes<WriteSystem, [HWPort0156]> { let Latency = 100; }
261 def : WriteRes<WriteMicrocoded, [HWPort0156]> { let Latency = 100; }
262 def : WriteRes<WriteFence, [HWPort23, HWPort4]>;
263 def : WriteRes<WriteNop, []>;
265 //================ Exceptions ================//
267 //-- Specific Scheduling Models --//
268 def Write2P0156_Lat2 : SchedWriteRes<[HWPort0156]> {
270 let ResourceCycles = [2];
272 def Write2P0156_Lat2Ld : SchedWriteRes<[HWPort0156, HWPort23]> {
274 let ResourceCycles = [2, 1];
277 def Write2P237_P4 : SchedWriteRes<[HWPort237, HWPort4]> {
279 let ResourceCycles = [2, 1];
282 def WriteP06 : SchedWriteRes<[HWPort06]>;
286 // - mm: 64 bit mmx register.
287 // - x = 128 bit xmm register.
288 // - (x)mm = mmx or xmm register.
289 // - y = 256 bit ymm register.
290 // - v = any vector register.
293 //=== Integer Instructions ===//
294 //-- Move instructions --//
298 def : InstRW<[WriteALULd], (instregex "MOV16rm")>;
302 def : InstRW<[WriteLoad], (instregex "MOV(S|Z)X32rm(8|16)")>;
306 def : InstRW<[Write2P0156_Lat2],
307 (instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rr")>;
309 def : InstRW<[Write2P0156_Lat2Ld, ReadAfterLd],
310 (instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rm")>;
314 def WriteXCHG : SchedWriteRes<[HWPort0156]> {
316 let ResourceCycles = [3];
319 def : InstRW<[WriteXCHG], (instregex "XCHG(8|16|32|64)rr", "XCHG(16|32|64)ar")>;
322 def WriteXCHGrm : SchedWriteRes<[]> {
326 def : InstRW<[WriteXCHGrm], (instregex "XCHG(8|16|32|64)rm")>;
329 def WriteXLAT : SchedWriteRes<[]> {
333 def : InstRW<[WriteXLAT], (instregex "XLAT")>;
337 def : InstRW<[Write2P237_P4], (instregex "PUSH(16|32)rmm")>;
340 def WritePushF : SchedWriteRes<[HWPort1, HWPort4, HWPort237, HWPort06]> {
343 def : InstRW<[WritePushF], (instregex "PUSHF(16|32)")>;
346 def WritePushA : SchedWriteRes<[]> {
347 let NumMicroOps = 19;
349 def : InstRW<[WritePushA], (instregex "PUSHA(16|32)")>;
353 def : InstRW<[Write2P237_P4], (instregex "POP(16|32)rmm")>;
356 def WritePopF : SchedWriteRes<[]> {
359 def : InstRW<[WritePopF], (instregex "POPF(16|32)")>;
362 def WritePopA : SchedWriteRes<[]> {
363 let NumMicroOps = 18;
365 def : InstRW<[WritePopA], (instregex "POPA(16|32)")>;
368 def : InstRW<[WriteP06], (instregex "(S|L)AHF")>;
372 def WriteBSwap32 : SchedWriteRes<[HWPort15]>;
373 def : InstRW<[WriteBSwap32], (instregex "BSWAP32r")>;
376 def WriteBSwap64 : SchedWriteRes<[HWPort06, HWPort15]> {
379 def : InstRW<[WriteBSwap64], (instregex "BSWAP64r")>;
382 // r16,m16 / r64,m64.
383 def : InstRW<[Write2P0156_Lat2Ld], (instregex "MOVBE(16|64)rm")>;
386 def WriteMoveBE32rm : SchedWriteRes<[HWPort15, HWPort23]> {
389 def : InstRW<[WriteMoveBE32rm], (instregex "MOVBE32rm")>;
392 def WriteMoveBE16mr : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
395 def : InstRW<[WriteMoveBE16mr], (instregex "MOVBE16mr")>;
398 def WriteMoveBE32mr : SchedWriteRes<[HWPort15, HWPort237, HWPort4]> {
401 def : InstRW<[WriteMoveBE32mr], (instregex "MOVBE32mr")>;
404 def WriteMoveBE64mr : SchedWriteRes<[HWPort06, HWPort15, HWPort237, HWPort4]> {
407 def : InstRW<[WriteMoveBE64mr], (instregex "MOVBE64mr")>;