1 //=- X86SchedHaswell.td - X86 Haswell Scheduling -------------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the machine model for Haswell to support instruction
11 // scheduling and other instruction cost heuristics.
13 //===----------------------------------------------------------------------===//
15 def HaswellModel : SchedMachineModel {
16 // All x86 instructions are modeled as a single micro-op, and HW can decode 4
17 // instructions per cycle.
19 let MicroOpBufferSize = 192; // Based on the reorder buffer.
21 let MispredictPenalty = 16;
23 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
24 let LoopMicroOpBufferSize = 50;
26 // FIXME: SSE4 and AVX are unimplemented. This flag is set to allow
27 // the scheduler to assign a default model to unrecognized opcodes.
28 let CompleteModel = 0;
31 let SchedModel = HaswellModel in {
33 // Haswell can issue micro-ops to 8 different ports in one cycle.
35 // Ports 0, 1, 5, and 6 handle all computation.
36 // Port 4 gets the data half of stores. Store data can be available later than
37 // the store address, but since we don't model the latency of stores, we can
39 // Ports 2 and 3 are identical. They handle loads and the address half of
40 // stores. Port 7 can handle address calculations.
41 def HWPort0 : ProcResource<1>;
42 def HWPort1 : ProcResource<1>;
43 def HWPort2 : ProcResource<1>;
44 def HWPort3 : ProcResource<1>;
45 def HWPort4 : ProcResource<1>;
46 def HWPort5 : ProcResource<1>;
47 def HWPort6 : ProcResource<1>;
48 def HWPort7 : ProcResource<1>;
50 // Many micro-ops are capable of issuing on multiple ports.
51 def HWPort23 : ProcResGroup<[HWPort2, HWPort3]>;
52 def HWPort237 : ProcResGroup<[HWPort2, HWPort3, HWPort7]>;
53 def HWPort05 : ProcResGroup<[HWPort0, HWPort5]>;
54 def HWPort06 : ProcResGroup<[HWPort0, HWPort6]>;
55 def HWPort15 : ProcResGroup<[HWPort1, HWPort5]>;
56 def HWPort16 : ProcResGroup<[HWPort1, HWPort6]>;
57 def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>;
58 def HWPort056: ProcResGroup<[HWPort0, HWPort5, HWPort6]>;
59 def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>;
61 // 60 Entry Unified Scheduler
62 def HWPortAny : ProcResGroup<[HWPort0, HWPort1, HWPort2, HWPort3, HWPort4,
63 HWPort5, HWPort6, HWPort7]> {
67 // Integer division issued on port 0.
68 def HWDivider : ProcResource<1>;
70 // Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4
71 // cycles after the memory operand.
72 def : ReadAdvance<ReadAfterLd, 4>;
74 // Many SchedWrites are defined in pairs with and without a folded load.
75 // Instructions with folded loads are usually micro-fused, so they only appear
76 // as two micro-ops when queued in the reservation station.
77 // This multiclass defines the resource usage for variants with and without
79 multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW,
80 ProcResourceKind ExePort,
82 // Register variant is using a single cycle on ExePort.
83 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
85 // Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the
87 def : WriteRes<SchedRW.Folded, [HWPort23, ExePort]> {
88 let Latency = !add(Lat, 4);
92 // A folded store needs a cycle on port 4 for the store data, but it does not
93 // need an extra port 2/3 cycle to recompute the address.
94 def : WriteRes<WriteRMW, [HWPort4]>;
98 def : WriteRes<WriteStore, [HWPort237, HWPort4]>;
99 def : WriteRes<WriteLoad, [HWPort23]> { let Latency = 4; }
100 def : WriteRes<WriteMove, [HWPort0156]>;
101 def : WriteRes<WriteZero, []>;
103 defm : HWWriteResPair<WriteALU, HWPort0156, 1>;
104 defm : HWWriteResPair<WriteIMul, HWPort1, 3>;
105 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
106 defm : HWWriteResPair<WriteShift, HWPort06, 1>;
107 defm : HWWriteResPair<WriteJump, HWPort06, 1>;
109 // This is for simple LEAs with one or two input operands.
110 // The complex ones can only execute on port 1, and they require two cycles on
111 // the port to read all inputs. We don't model that.
112 def : WriteRes<WriteLEA, [HWPort15]>;
114 // This is quite rough, latency depends on the dividend.
115 def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> {
117 let ResourceCycles = [1, 10];
119 def : WriteRes<WriteIDivLd, [HWPort23, HWPort0, HWDivider]> {
121 let ResourceCycles = [1, 1, 10];
124 // Scalar and vector floating point.
125 defm : HWWriteResPair<WriteFAdd, HWPort1, 3>;
126 defm : HWWriteResPair<WriteFMul, HWPort0, 5>;
127 defm : HWWriteResPair<WriteFDiv, HWPort0, 12>; // 10-14 cycles.
128 defm : HWWriteResPair<WriteFRcp, HWPort0, 5>;
129 defm : HWWriteResPair<WriteFSqrt, HWPort0, 15>;
130 defm : HWWriteResPair<WriteCvtF2I, HWPort1, 3>;
131 defm : HWWriteResPair<WriteCvtI2F, HWPort1, 4>;
132 defm : HWWriteResPair<WriteCvtF2F, HWPort1, 3>;
133 defm : HWWriteResPair<WriteFShuffle, HWPort5, 1>;
134 defm : HWWriteResPair<WriteFBlend, HWPort015, 1>;
135 defm : HWWriteResPair<WriteFShuffle256, HWPort5, 3>;
137 def : WriteRes<WriteFVarBlend, [HWPort5]> {
139 let ResourceCycles = [2];
141 def : WriteRes<WriteFVarBlendLd, [HWPort5, HWPort23]> {
143 let ResourceCycles = [2, 1];
146 // Vector integer operations.
147 defm : HWWriteResPair<WriteVecShift, HWPort0, 1>;
148 defm : HWWriteResPair<WriteVecLogic, HWPort015, 1>;
149 defm : HWWriteResPair<WriteVecALU, HWPort15, 1>;
150 defm : HWWriteResPair<WriteVecIMul, HWPort0, 5>;
151 defm : HWWriteResPair<WriteShuffle, HWPort5, 1>;
152 defm : HWWriteResPair<WriteBlend, HWPort15, 1>;
153 defm : HWWriteResPair<WriteShuffle256, HWPort5, 3>;
155 def : WriteRes<WriteVarBlend, [HWPort5]> {
157 let ResourceCycles = [2];
159 def : WriteRes<WriteVarBlendLd, [HWPort5, HWPort23]> {
161 let ResourceCycles = [2, 1];
164 def : WriteRes<WriteVarVecShift, [HWPort0, HWPort5]> {
166 let ResourceCycles = [2, 1];
168 def : WriteRes<WriteVarVecShiftLd, [HWPort0, HWPort5, HWPort23]> {
170 let ResourceCycles = [2, 1, 1];
173 def : WriteRes<WriteMPSAD, [HWPort0, HWPort5]> {
175 let ResourceCycles = [1, 2];
177 def : WriteRes<WriteMPSADLd, [HWPort23, HWPort0, HWPort5]> {
179 let ResourceCycles = [1, 1, 2];
182 // String instructions.
183 // Packed Compare Implicit Length Strings, Return Mask
184 def : WriteRes<WritePCmpIStrM, [HWPort0]> {
186 let ResourceCycles = [3];
188 def : WriteRes<WritePCmpIStrMLd, [HWPort0, HWPort23]> {
190 let ResourceCycles = [3, 1];
193 // Packed Compare Explicit Length Strings, Return Mask
194 def : WriteRes<WritePCmpEStrM, [HWPort0, HWPort16, HWPort5]> {
196 let ResourceCycles = [3, 2, 4];
198 def : WriteRes<WritePCmpEStrMLd, [HWPort05, HWPort16, HWPort23]> {
200 let ResourceCycles = [6, 2, 1];
203 // Packed Compare Implicit Length Strings, Return Index
204 def : WriteRes<WritePCmpIStrI, [HWPort0]> {
206 let ResourceCycles = [3];
208 def : WriteRes<WritePCmpIStrILd, [HWPort0, HWPort23]> {
210 let ResourceCycles = [3, 1];
213 // Packed Compare Explicit Length Strings, Return Index
214 def : WriteRes<WritePCmpEStrI, [HWPort05, HWPort16]> {
216 let ResourceCycles = [6, 2];
218 def : WriteRes<WritePCmpEStrILd, [HWPort0, HWPort16, HWPort5, HWPort23]> {
220 let ResourceCycles = [3, 2, 2, 1];
224 def : WriteRes<WriteAESDecEnc, [HWPort5]> {
226 let ResourceCycles = [1];
228 def : WriteRes<WriteAESDecEncLd, [HWPort5, HWPort23]> {
230 let ResourceCycles = [1, 1];
233 def : WriteRes<WriteAESIMC, [HWPort5]> {
235 let ResourceCycles = [2];
237 def : WriteRes<WriteAESIMCLd, [HWPort5, HWPort23]> {
239 let ResourceCycles = [2, 1];
242 def : WriteRes<WriteAESKeyGen, [HWPort0, HWPort5]> {
244 let ResourceCycles = [2, 8];
246 def : WriteRes<WriteAESKeyGenLd, [HWPort0, HWPort5, HWPort23]> {
248 let ResourceCycles = [2, 7, 1];
251 // Carry-less multiplication instructions.
252 def : WriteRes<WriteCLMul, [HWPort0, HWPort5]> {
254 let ResourceCycles = [2, 1];
256 def : WriteRes<WriteCLMulLd, [HWPort0, HWPort5, HWPort23]> {
258 let ResourceCycles = [2, 1, 1];
261 def : WriteRes<WriteSystem, [HWPort0156]> { let Latency = 100; }
262 def : WriteRes<WriteMicrocoded, [HWPort0156]> { let Latency = 100; }
263 def : WriteRes<WriteFence, [HWPort23, HWPort4]>;
264 def : WriteRes<WriteNop, []>;
266 //================ Exceptions ================//
268 //-- Specific Scheduling Models --//
269 def WriteP1_Lat3 : SchedWriteRes<[HWPort1]> {
272 def WriteP1_Lat3Ld : SchedWriteRes<[HWPort1, HWPort23]> {
276 def Write2P0156_Lat2 : SchedWriteRes<[HWPort0156]> {
278 let ResourceCycles = [2];
280 def Write2P0156_Lat2Ld : SchedWriteRes<[HWPort0156, HWPort23]> {
282 let ResourceCycles = [2, 1];
285 def Write2P237_P4 : SchedWriteRes<[HWPort237, HWPort4]> {
287 let ResourceCycles = [2, 1];
290 def WriteP06 : SchedWriteRes<[HWPort06]>;
292 def Write2P06 : SchedWriteRes<[HWPort06]> {
295 let ResourceCycles = [2];
298 def WriteP15 : SchedWriteRes<[HWPort15]>;
299 def WriteP15Ld : SchedWriteRes<[HWPort15, HWPort23]> {
303 def Write3P06_Lat2 : SchedWriteRes<[HWPort06]> {
306 let ResourceCycles = [3];
309 def WriteP0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
311 let ResourceCycles = [1, 2, 1];
314 def Write2P0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
316 let ResourceCycles = [2, 2, 1];
319 def Write3P0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
321 let ResourceCycles = [3, 2, 1];
326 // - mm: 64 bit mmx register.
327 // - x = 128 bit xmm register.
328 // - (x)mm = mmx or xmm register.
329 // - y = 256 bit ymm register.
330 // - v = any vector register.
333 //=== Integer Instructions ===//
334 //-- Move instructions --//
338 def : InstRW<[WriteALULd], (instregex "MOV16rm")>;
342 def : InstRW<[WriteLoad], (instregex "MOV(S|Z)X32rm(8|16)")>;
346 def : InstRW<[Write2P0156_Lat2],
347 (instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rr")>;
349 def : InstRW<[Write2P0156_Lat2Ld, ReadAfterLd],
350 (instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rm")>;
354 def WriteXCHG : SchedWriteRes<[HWPort0156]> {
356 let ResourceCycles = [3];
359 def : InstRW<[WriteXCHG], (instregex "XCHG(8|16|32|64)rr", "XCHG(16|32|64)ar")>;
362 def WriteXCHGrm : SchedWriteRes<[]> {
366 def : InstRW<[WriteXCHGrm], (instregex "XCHG(8|16|32|64)rm")>;
369 def WriteXLAT : SchedWriteRes<[]> {
373 def : InstRW<[WriteXLAT], (instregex "XLAT")>;
377 def : InstRW<[Write2P237_P4], (instregex "PUSH(16|32)rmm")>;
380 def WritePushF : SchedWriteRes<[HWPort1, HWPort4, HWPort237, HWPort06]> {
383 def : InstRW<[WritePushF], (instregex "PUSHF(16|32)")>;
386 def WritePushA : SchedWriteRes<[]> {
387 let NumMicroOps = 19;
389 def : InstRW<[WritePushA], (instregex "PUSHA(16|32)")>;
393 def : InstRW<[Write2P237_P4], (instregex "POP(16|32)rmm")>;
396 def WritePopF : SchedWriteRes<[]> {
399 def : InstRW<[WritePopF], (instregex "POPF(16|32)")>;
402 def WritePopA : SchedWriteRes<[]> {
403 let NumMicroOps = 18;
405 def : InstRW<[WritePopA], (instregex "POPA(16|32)")>;
408 def : InstRW<[WriteP06], (instregex "(S|L)AHF")>;
412 def WriteBSwap32 : SchedWriteRes<[HWPort15]>;
413 def : InstRW<[WriteBSwap32], (instregex "BSWAP32r")>;
416 def WriteBSwap64 : SchedWriteRes<[HWPort06, HWPort15]> {
419 def : InstRW<[WriteBSwap64], (instregex "BSWAP64r")>;
422 // r16,m16 / r64,m64.
423 def : InstRW<[Write2P0156_Lat2Ld], (instregex "MOVBE(16|64)rm")>;
426 def WriteMoveBE32rm : SchedWriteRes<[HWPort15, HWPort23]> {
429 def : InstRW<[WriteMoveBE32rm], (instregex "MOVBE32rm")>;
432 def WriteMoveBE16mr : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
435 def : InstRW<[WriteMoveBE16mr], (instregex "MOVBE16mr")>;
438 def WriteMoveBE32mr : SchedWriteRes<[HWPort15, HWPort237, HWPort4]> {
441 def : InstRW<[WriteMoveBE32mr], (instregex "MOVBE32mr")>;
444 def WriteMoveBE64mr : SchedWriteRes<[HWPort06, HWPort15, HWPort237, HWPort4]> {
447 def : InstRW<[WriteMoveBE64mr], (instregex "MOVBE64mr")>;
449 //-- Arithmetic instructions --//
453 def : InstRW<[Write2P0156_2P237_P4],
454 (instregex "(ADD|SUB)(8|16|32|64)m(r|i)",
455 "(ADD|SUB)(8|16|32|64)mi8", "(ADD|SUB)64mi32")>;
459 def : InstRW<[Write2P0156_Lat2], (instregex "(ADC|SBB)(8|16|32|64)r(r|i)",
460 "(ADC|SBB)(16|32|64)ri8",
462 "(ADC|SBB)(8|16|32|64)rr_REV")>;
465 def : InstRW<[Write2P0156_Lat2Ld, ReadAfterLd], (instregex "(ADC|SBB)(8|16|32|64)rm")>;
468 def : InstRW<[Write3P0156_2P237_P4],
469 (instregex "(ADC|SBB)(8|16|32|64)m(r|i)",
470 "(ADC|SBB)(16|32|64)mi8",
475 def : InstRW<[WriteP0156_2P237_P4],
476 (instregex "(INC|DEC|NOT|NEG)(8|16|32|64)m",
477 "(INC|DEC)64(16|32)m")>;
481 def WriteMul16 : SchedWriteRes<[HWPort1, HWPort0156]> {
485 def : InstRW<[WriteMul16], (instregex "IMUL16r", "MUL16r")>;
488 def WriteMul16Ld : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> {
492 def : InstRW<[WriteMul16Ld], (instregex "IMUL16m", "MUL16m")>;
495 def WriteMul32 : SchedWriteRes<[HWPort1, HWPort0156]> {
499 def : InstRW<[WriteMul32], (instregex "IMUL32r", "MUL32r")>;
502 def WriteMul32Ld : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> {
506 def : InstRW<[WriteMul32Ld], (instregex "IMUL32m", "MUL32m")>;
509 def WriteMul64 : SchedWriteRes<[HWPort1, HWPort6]> {
513 def : InstRW<[WriteMul64], (instregex "IMUL64r", "MUL64r")>;
516 def WriteMul64Ld : SchedWriteRes<[HWPort1, HWPort6, HWPort23]> {
520 def : InstRW<[WriteMul64Ld], (instregex "IMUL64m", "MUL64m")>;
523 def WriteMul16rri : SchedWriteRes<[HWPort1, HWPort0156]> {
527 def : InstRW<[WriteMul16rri], (instregex "IMUL16rri", "IMUL16rri8")>;
530 def WriteMul16rmi : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> {
534 def : InstRW<[WriteMul16rmi], (instregex "IMUL16rmi", "IMUL16rmi8")>;
538 def WriteMulX32 : SchedWriteRes<[HWPort1, HWPort056]> {
541 let ResourceCycles = [1, 2];
543 def : InstRW<[WriteMulX32], (instregex "MULX32rr")>;
546 def WriteMulX32Ld : SchedWriteRes<[HWPort1, HWPort056, HWPort23]> {
549 let ResourceCycles = [1, 2, 1];
551 def : InstRW<[WriteMulX32Ld], (instregex "MULX32rm")>;
554 def WriteMulX64 : SchedWriteRes<[HWPort1, HWPort6]> {
558 def : InstRW<[WriteMulX64], (instregex "MULX64rr")>;
561 def WriteMulX64Ld : SchedWriteRes<[HWPort1, HWPort6, HWPort23]> {
565 def : InstRW<[WriteMulX64Ld], (instregex "MULX64rm")>;
569 def WriteDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
573 def : InstRW<[WriteDiv8], (instregex "DIV8r")>;
576 def WriteDiv16 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
578 let NumMicroOps = 10;
580 def : InstRW<[WriteDiv16], (instregex "DIV16r")>;
583 def WriteDiv32 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
585 let NumMicroOps = 10;
587 def : InstRW<[WriteDiv32], (instregex "DIV32r")>;
590 def WriteDiv64 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
592 let NumMicroOps = 36;
594 def : InstRW<[WriteDiv64], (instregex "DIV64r")>;
598 def WriteIDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
602 def : InstRW<[WriteIDiv8], (instregex "IDIV8r")>;
605 def WriteIDiv16 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
607 let NumMicroOps = 10;
609 def : InstRW<[WriteIDiv16], (instregex "IDIV16r")>;
612 def WriteIDiv32 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
616 def : InstRW<[WriteIDiv32], (instregex "IDIV32r")>;
619 def WriteIDiv64 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
621 let NumMicroOps = 59;
623 def : InstRW<[WriteIDiv64], (instregex "IDIV64r")>;
625 //-- Logic instructions --//
629 def : InstRW<[Write2P0156_2P237_P4],
630 (instregex "(AND|OR|XOR)(8|16|32|64)m(r|i)",
631 "(AND|OR|XOR)(8|16|32|64)mi8", "(AND|OR|XOR)64mi32")>;
635 def WriteShiftRMW : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
637 let ResourceCycles = [2, 1, 1];
639 def : InstRW<[WriteShiftRMW], (instregex "S(A|H)(R|L)(8|16|32|64)m(i|1)")>;
642 def : InstRW<[Write3P06_Lat2], (instregex "S(A|H)(R|L)(8|16|32|64)rCL")>;
645 def WriteShiftClLdRMW : SchedWriteRes<[HWPort06, HWPort23, HWPort4]> {
647 let ResourceCycles = [3, 2, 1];
649 def : InstRW<[WriteShiftClLdRMW], (instregex "S(A|H)(R|L)(8|16|32|64)mCL")>;
653 def : InstRW<[Write2P06], (instregex "RO(R|L)(8|16|32|64)r1")>;
656 def WriteRotateRMW : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
658 let ResourceCycles = [2, 2, 1];
660 def : InstRW<[WriteRotateRMW], (instregex "RO(R|L)(8|16|32|64)mi")>;
663 def : InstRW<[Write3P06_Lat2], (instregex "RO(R|L)(8|16|32|64)rCL")>;
666 def WriteRotateRMWCL : SchedWriteRes<[]> {
669 def : InstRW<[WriteRotateRMWCL], (instregex "RO(R|L)(8|16|32|64)mCL")>;
673 def WriteRCr1 : SchedWriteRes<[HWPort06, HWPort0156]> {
676 let ResourceCycles = [2, 1];
678 def : InstRW<[WriteRCr1], (instregex "RC(R|L)(8|16|32|64)r1")>;
681 def WriteRCm1 : SchedWriteRes<[]> {
684 def : InstRW<[WriteRCm1], (instregex "RC(R|L)(8|16|32|64)m1")>;
687 def WriteRCri : SchedWriteRes<[HWPort0156]> {
691 def : InstRW<[WriteRCri], (instregex "RC(R|L)(8|16|32|64)r(i|CL)")>;
694 def WriteRCmi : SchedWriteRes<[]> {
695 let NumMicroOps = 11;
697 def : InstRW<[WriteRCmi], (instregex "RC(R|L)(8|16|32|64)m(i|CL)")>;
701 def WriteShDrr : SchedWriteRes<[HWPort1]> {
704 def : InstRW<[WriteShDrr], (instregex "SH(R|L)D(16|32|64)rri8")>;
707 def WriteShDmr : SchedWriteRes<[]> {
710 def : InstRW<[WriteShDmr], (instregex "SH(R|L)D(16|32|64)mri8")>;
713 def WriteShlDCL : SchedWriteRes<[HWPort0156]> {
717 def : InstRW<[WriteShlDCL], (instregex "SHLD(16|32|64)rrCL")>;
720 def WriteShrDCL : SchedWriteRes<[HWPort0156]> {
724 def : InstRW<[WriteShrDCL], (instregex "SHRD(16|32|64)rrCL")>;
727 def WriteShDmrCL : SchedWriteRes<[]> {
730 def : InstRW<[WriteShDmrCL], (instregex "SH(R|L)D(16|32|64)mrCL")>;
734 def : InstRW<[WriteShift], (instregex "BT(16|32|64)r(r|i8)")>;
737 def WriteBTmr : SchedWriteRes<[]> {
738 let NumMicroOps = 10;
740 def : InstRW<[WriteBTmr], (instregex "BT(16|32|64)mr")>;
743 def : InstRW<[WriteShiftLd], (instregex "BT(16|32|64)mi8")>;
747 def : InstRW<[WriteShift], (instregex "BT(R|S|C)(16|32|64)r(r|i8)")>;
750 def WriteBTRSCmr : SchedWriteRes<[]> {
751 let NumMicroOps = 11;
753 def : InstRW<[WriteBTRSCmr], (instregex "BT(R|S|C)(16|32|64)mr")>;
756 def : InstRW<[WriteShiftLd], (instregex "BT(R|S|C)(16|32|64)mi8")>;
760 def : InstRW<[WriteP1_Lat3], (instregex "BS(R|F)(16|32|64)rr")>;
762 def : InstRW<[WriteP1_Lat3Ld], (instregex "BS(R|F)(16|32|64)rm")>;
766 def : InstRW<[WriteShift],
767 (instregex "SET(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)r")>;
769 def WriteSetCCm : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
772 def : InstRW<[WriteSetCCm],
773 (instregex "SET(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)m")>;
776 def WriteCldStd : SchedWriteRes<[HWPort15, HWPort6]> {
779 def : InstRW<[WriteCldStd], (instregex "STD", "CLD")>;
783 def : InstRW<[WriteP1_Lat3], (instregex "(L|TZCNT)(16|32|64)rr")>;
785 def : InstRW<[WriteP1_Lat3Ld], (instregex "(L|TZCNT)(16|32|64)rm")>;
789 def : InstRW<[WriteP15], (instregex "ANDN(32|64)rr")>;
791 def : InstRW<[WriteP15Ld], (instregex "ANDN(32|64)rm")>;
795 def : InstRW<[WriteP15], (instregex "BLS(I|MSK|R)(32|64)rr")>;
797 def : InstRW<[WriteP15Ld], (instregex "BLS(I|MSK|R)(32|64)rm")>;
801 def : InstRW<[Write2P0156_Lat2], (instregex "BEXTR(32|64)rr")>;
803 def : InstRW<[Write2P0156_Lat2Ld], (instregex "BEXTR(32|64)rm")>;
807 def : InstRW<[WriteP15], (instregex "BZHI(32|64)rr")>;
809 def : InstRW<[WriteP15Ld], (instregex "BZHI(32|64)rm")>;
813 def : InstRW<[WriteP1_Lat3], (instregex "PDEP(32|64)rr", "PEXT(32|64)rr")>;
815 def : InstRW<[WriteP1_Lat3Ld], (instregex "PDEP(32|64)rm", "PEXT(32|64)rm")>;