1 //=- X86SchedHaswell.td - X86 Haswell Scheduling -------------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the machine model for Haswell to support instruction
11 // scheduling and other instruction cost heuristics.
13 //===----------------------------------------------------------------------===//
15 def HaswellModel : SchedMachineModel {
16 // All x86 instructions are modeled as a single micro-op, and HW can decode 4
17 // instructions per cycle.
19 let MicroOpBufferSize = 192; // Based on the reorder buffer.
21 let MispredictPenalty = 16;
23 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
24 let LoopMicroOpBufferSize = 50;
26 // FIXME: SSE4 and AVX are unimplemented. This flag is set to allow
27 // the scheduler to assign a default model to unrecognized opcodes.
28 let CompleteModel = 0;
31 let SchedModel = HaswellModel in {
33 // Haswell can issue micro-ops to 8 different ports in one cycle.
35 // Ports 0, 1, 5, and 6 handle all computation.
36 // Port 4 gets the data half of stores. Store data can be available later than
37 // the store address, but since we don't model the latency of stores, we can
39 // Ports 2 and 3 are identical. They handle loads and the address half of
40 // stores. Port 7 can handle address calculations.
41 def HWPort0 : ProcResource<1>;
42 def HWPort1 : ProcResource<1>;
43 def HWPort2 : ProcResource<1>;
44 def HWPort3 : ProcResource<1>;
45 def HWPort4 : ProcResource<1>;
46 def HWPort5 : ProcResource<1>;
47 def HWPort6 : ProcResource<1>;
48 def HWPort7 : ProcResource<1>;
50 // Many micro-ops are capable of issuing on multiple ports.
51 def HWPort01 : ProcResGroup<[HWPort0, HWPort1]>;
52 def HWPort23 : ProcResGroup<[HWPort2, HWPort3]>;
53 def HWPort237 : ProcResGroup<[HWPort2, HWPort3, HWPort7]>;
54 def HWPort04 : ProcResGroup<[HWPort0, HWPort4]>;
55 def HWPort05 : ProcResGroup<[HWPort0, HWPort5]>;
56 def HWPort06 : ProcResGroup<[HWPort0, HWPort6]>;
57 def HWPort15 : ProcResGroup<[HWPort1, HWPort5]>;
58 def HWPort16 : ProcResGroup<[HWPort1, HWPort6]>;
59 def HWPort56 : ProcResGroup<[HWPort5, HWPort6]>;
60 def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>;
61 def HWPort056 : ProcResGroup<[HWPort0, HWPort5, HWPort6]>;
62 def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>;
64 // 60 Entry Unified Scheduler
65 def HWPortAny : ProcResGroup<[HWPort0, HWPort1, HWPort2, HWPort3, HWPort4,
66 HWPort5, HWPort6, HWPort7]> {
70 // Integer division issued on port 0.
71 def HWDivider : ProcResource<1>;
73 // Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4
74 // cycles after the memory operand.
75 def : ReadAdvance<ReadAfterLd, 4>;
77 // Many SchedWrites are defined in pairs with and without a folded load.
78 // Instructions with folded loads are usually micro-fused, so they only appear
79 // as two micro-ops when queued in the reservation station.
80 // This multiclass defines the resource usage for variants with and without
82 multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW,
83 ProcResourceKind ExePort,
85 // Register variant is using a single cycle on ExePort.
86 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
88 // Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the
90 def : WriteRes<SchedRW.Folded, [HWPort23, ExePort]> {
91 let Latency = !add(Lat, 4);
95 // A folded store needs a cycle on port 4 for the store data, but it does not
96 // need an extra port 2/3 cycle to recompute the address.
97 def : WriteRes<WriteRMW, [HWPort4]>;
101 def : WriteRes<WriteStore, [HWPort237, HWPort4]>;
102 def : WriteRes<WriteLoad, [HWPort23]> { let Latency = 4; }
103 def : WriteRes<WriteMove, [HWPort0156]>;
104 def : WriteRes<WriteZero, []>;
106 defm : HWWriteResPair<WriteALU, HWPort0156, 1>;
107 defm : HWWriteResPair<WriteIMul, HWPort1, 3>;
108 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
109 defm : HWWriteResPair<WriteShift, HWPort06, 1>;
110 defm : HWWriteResPair<WriteJump, HWPort06, 1>;
112 // This is for simple LEAs with one or two input operands.
113 // The complex ones can only execute on port 1, and they require two cycles on
114 // the port to read all inputs. We don't model that.
115 def : WriteRes<WriteLEA, [HWPort15]>;
117 // This is quite rough, latency depends on the dividend.
118 def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> {
120 let ResourceCycles = [1, 10];
122 def : WriteRes<WriteIDivLd, [HWPort23, HWPort0, HWDivider]> {
124 let ResourceCycles = [1, 1, 10];
127 // Scalar and vector floating point.
128 defm : HWWriteResPair<WriteFAdd, HWPort1, 3>;
129 defm : HWWriteResPair<WriteFMul, HWPort0, 5>;
130 defm : HWWriteResPair<WriteFDiv, HWPort0, 12>; // 10-14 cycles.
131 defm : HWWriteResPair<WriteFRcp, HWPort0, 5>;
132 defm : HWWriteResPair<WriteFSqrt, HWPort0, 15>;
133 defm : HWWriteResPair<WriteCvtF2I, HWPort1, 3>;
134 defm : HWWriteResPair<WriteCvtI2F, HWPort1, 4>;
135 defm : HWWriteResPair<WriteCvtF2F, HWPort1, 3>;
136 defm : HWWriteResPair<WriteFShuffle, HWPort5, 1>;
137 defm : HWWriteResPair<WriteFBlend, HWPort015, 1>;
138 defm : HWWriteResPair<WriteFShuffle256, HWPort5, 3>;
140 def : WriteRes<WriteFVarBlend, [HWPort5]> {
142 let ResourceCycles = [2];
144 def : WriteRes<WriteFVarBlendLd, [HWPort5, HWPort23]> {
146 let ResourceCycles = [2, 1];
149 // Vector integer operations.
150 defm : HWWriteResPair<WriteVecShift, HWPort0, 1>;
151 defm : HWWriteResPair<WriteVecLogic, HWPort015, 1>;
152 defm : HWWriteResPair<WriteVecALU, HWPort15, 1>;
153 defm : HWWriteResPair<WriteVecIMul, HWPort0, 5>;
154 defm : HWWriteResPair<WriteShuffle, HWPort5, 1>;
155 defm : HWWriteResPair<WriteBlend, HWPort15, 1>;
156 defm : HWWriteResPair<WriteShuffle256, HWPort5, 3>;
158 def : WriteRes<WriteVarBlend, [HWPort5]> {
160 let ResourceCycles = [2];
162 def : WriteRes<WriteVarBlendLd, [HWPort5, HWPort23]> {
164 let ResourceCycles = [2, 1];
167 def : WriteRes<WriteVarVecShift, [HWPort0, HWPort5]> {
169 let ResourceCycles = [2, 1];
171 def : WriteRes<WriteVarVecShiftLd, [HWPort0, HWPort5, HWPort23]> {
173 let ResourceCycles = [2, 1, 1];
176 def : WriteRes<WriteMPSAD, [HWPort0, HWPort5]> {
178 let ResourceCycles = [1, 2];
180 def : WriteRes<WriteMPSADLd, [HWPort23, HWPort0, HWPort5]> {
182 let ResourceCycles = [1, 1, 2];
185 // String instructions.
186 // Packed Compare Implicit Length Strings, Return Mask
187 def : WriteRes<WritePCmpIStrM, [HWPort0]> {
189 let ResourceCycles = [3];
191 def : WriteRes<WritePCmpIStrMLd, [HWPort0, HWPort23]> {
193 let ResourceCycles = [3, 1];
196 // Packed Compare Explicit Length Strings, Return Mask
197 def : WriteRes<WritePCmpEStrM, [HWPort0, HWPort16, HWPort5]> {
199 let ResourceCycles = [3, 2, 4];
201 def : WriteRes<WritePCmpEStrMLd, [HWPort05, HWPort16, HWPort23]> {
203 let ResourceCycles = [6, 2, 1];
206 // Packed Compare Implicit Length Strings, Return Index
207 def : WriteRes<WritePCmpIStrI, [HWPort0]> {
209 let ResourceCycles = [3];
211 def : WriteRes<WritePCmpIStrILd, [HWPort0, HWPort23]> {
213 let ResourceCycles = [3, 1];
216 // Packed Compare Explicit Length Strings, Return Index
217 def : WriteRes<WritePCmpEStrI, [HWPort05, HWPort16]> {
219 let ResourceCycles = [6, 2];
221 def : WriteRes<WritePCmpEStrILd, [HWPort0, HWPort16, HWPort5, HWPort23]> {
223 let ResourceCycles = [3, 2, 2, 1];
227 def : WriteRes<WriteAESDecEnc, [HWPort5]> {
229 let ResourceCycles = [1];
231 def : WriteRes<WriteAESDecEncLd, [HWPort5, HWPort23]> {
233 let ResourceCycles = [1, 1];
236 def : WriteRes<WriteAESIMC, [HWPort5]> {
238 let ResourceCycles = [2];
240 def : WriteRes<WriteAESIMCLd, [HWPort5, HWPort23]> {
242 let ResourceCycles = [2, 1];
245 def : WriteRes<WriteAESKeyGen, [HWPort0, HWPort5]> {
247 let ResourceCycles = [2, 8];
249 def : WriteRes<WriteAESKeyGenLd, [HWPort0, HWPort5, HWPort23]> {
251 let ResourceCycles = [2, 7, 1];
254 // Carry-less multiplication instructions.
255 def : WriteRes<WriteCLMul, [HWPort0, HWPort5]> {
257 let ResourceCycles = [2, 1];
259 def : WriteRes<WriteCLMulLd, [HWPort0, HWPort5, HWPort23]> {
261 let ResourceCycles = [2, 1, 1];
264 def : WriteRes<WriteSystem, [HWPort0156]> { let Latency = 100; }
265 def : WriteRes<WriteMicrocoded, [HWPort0156]> { let Latency = 100; }
266 def : WriteRes<WriteFence, [HWPort23, HWPort4]>;
267 def : WriteRes<WriteNop, []>;
269 //================ Exceptions ================//
271 //-- Specific Scheduling Models --//
274 def WriteP0 : SchedWriteRes<[HWPort0]>;
276 def WriteP0_P1_Lat4 : SchedWriteRes<[HWPort0, HWPort1]> {
279 let ResourceCycles = [1, 1];
282 def WriteP0_P1_Lat4Ld : SchedWriteRes<[HWPort0, HWPort1, HWPort23]> {
285 let ResourceCycles = [1, 1, 1];
288 def WriteP01 : SchedWriteRes<[HWPort01]>;
290 def Write2P01 : SchedWriteRes<[HWPort01]> {
293 def Write3P01 : SchedWriteRes<[HWPort01]> {
297 def WriteP015 : SchedWriteRes<[HWPort015]>;
299 def WriteP01_P5 : SchedWriteRes<[HWPort01, HWPort5]> {
302 def WriteP06 : SchedWriteRes<[HWPort06]>;
304 def Write2P06 : SchedWriteRes<[HWPort06]> {
307 let ResourceCycles = [2];
310 def Write3P06_Lat2 : SchedWriteRes<[HWPort06]> {
313 let ResourceCycles = [3];
316 def WriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
320 def Write2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
322 let ResourceCycles = [2, 1];
325 def Write2P0156_Lat2 : SchedWriteRes<[HWPort0156]> {
327 let ResourceCycles = [2];
329 def Write2P0156_Lat2Ld : SchedWriteRes<[HWPort0156, HWPort23]> {
331 let ResourceCycles = [2, 1];
334 def Write5P0156 : SchedWriteRes<[HWPort0156]> {
336 let ResourceCycles = [5];
339 def WriteP0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
341 let ResourceCycles = [1, 2, 1];
344 def Write2P0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
346 let ResourceCycles = [2, 2, 1];
349 def Write3P0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
351 let ResourceCycles = [3, 2, 1];
355 def WriteP1 : SchedWriteRes<[HWPort1]>;
357 def WriteP1_P23 : SchedWriteRes<[HWPort1, HWPort23]> {
360 def WriteP1_Lat3 : SchedWriteRes<[HWPort1]> {
363 def WriteP1_Lat3Ld : SchedWriteRes<[HWPort1, HWPort23]> {
367 def Write2P1 : SchedWriteRes<[HWPort1]> {
369 let ResourceCycles = [2];
371 def Write2P1_P23 : SchedWriteRes<[HWPort1, HWPort23]> {
373 let ResourceCycles = [2, 1];
375 def WriteP15 : SchedWriteRes<[HWPort15]>;
376 def WriteP15Ld : SchedWriteRes<[HWPort15, HWPort23]> {
380 def WriteP1_P5_Lat4 : SchedWriteRes<[HWPort1, HWPort5]> {
383 let ResourceCycles = [1, 1];
386 def WriteP1_P5_Lat4Ld : SchedWriteRes<[HWPort1, HWPort5, HWPort23]> {
389 let ResourceCycles = [1, 1, 1];
392 def WriteP1_P5_Lat6 : SchedWriteRes<[HWPort1, HWPort5]> {
395 let ResourceCycles = [1, 1];
398 def WriteP1_P5_Lat6Ld : SchedWriteRes<[HWPort1, HWPort5, HWPort23]> {
401 let ResourceCycles = [1, 1, 1];
405 def Write2P237_P4 : SchedWriteRes<[HWPort237, HWPort4]> {
407 let ResourceCycles = [2, 1];
411 def WriteP5 : SchedWriteRes<[HWPort5]>;
412 def WriteP5Ld : SchedWriteRes<[HWPort5, HWPort23]> {
415 let ResourceCycles = [1, 1];
420 // - mm: 64 bit mmx register.
421 // - x = 128 bit xmm register.
422 // - (x)mm = mmx or xmm register.
423 // - y = 256 bit ymm register.
424 // - v = any vector register.
427 //=== Integer Instructions ===//
428 //-- Move instructions --//
432 def : InstRW<[WriteALULd], (instregex "MOV16rm")>;
436 def : InstRW<[WriteLoad], (instregex "MOV(S|Z)X32rm(8|16)")>;
440 def : InstRW<[Write2P0156_Lat2],
441 (instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rr")>;
443 def : InstRW<[Write2P0156_Lat2Ld, ReadAfterLd],
444 (instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rm")>;
448 def WriteXCHG : SchedWriteRes<[HWPort0156]> {
450 let ResourceCycles = [3];
453 def : InstRW<[WriteXCHG], (instregex "XCHG(8|16|32|64)rr", "XCHG(16|32|64)ar")>;
456 def WriteXCHGrm : SchedWriteRes<[]> {
460 def : InstRW<[WriteXCHGrm], (instregex "XCHG(8|16|32|64)rm")>;
463 def WriteXLAT : SchedWriteRes<[]> {
467 def : InstRW<[WriteXLAT], (instregex "XLAT")>;
471 def : InstRW<[Write2P237_P4], (instregex "PUSH(16|32)rmm")>;
474 def WritePushF : SchedWriteRes<[HWPort1, HWPort4, HWPort237, HWPort06]> {
477 def : InstRW<[WritePushF], (instregex "PUSHF(16|32)")>;
480 def WritePushA : SchedWriteRes<[]> {
481 let NumMicroOps = 19;
483 def : InstRW<[WritePushA], (instregex "PUSHA(16|32)")>;
487 def : InstRW<[Write2P237_P4], (instregex "POP(16|32)rmm")>;
490 def WritePopF : SchedWriteRes<[]> {
493 def : InstRW<[WritePopF], (instregex "POPF(16|32)")>;
496 def WritePopA : SchedWriteRes<[]> {
497 let NumMicroOps = 18;
499 def : InstRW<[WritePopA], (instregex "POPA(16|32)")>;
502 def : InstRW<[WriteP06], (instregex "(S|L)AHF")>;
506 def WriteBSwap32 : SchedWriteRes<[HWPort15]>;
507 def : InstRW<[WriteBSwap32], (instregex "BSWAP32r")>;
510 def WriteBSwap64 : SchedWriteRes<[HWPort06, HWPort15]> {
513 def : InstRW<[WriteBSwap64], (instregex "BSWAP64r")>;
516 // r16,m16 / r64,m64.
517 def : InstRW<[Write2P0156_Lat2Ld], (instregex "MOVBE(16|64)rm")>;
520 def WriteMoveBE32rm : SchedWriteRes<[HWPort15, HWPort23]> {
523 def : InstRW<[WriteMoveBE32rm], (instregex "MOVBE32rm")>;
526 def WriteMoveBE16mr : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
529 def : InstRW<[WriteMoveBE16mr], (instregex "MOVBE16mr")>;
532 def WriteMoveBE32mr : SchedWriteRes<[HWPort15, HWPort237, HWPort4]> {
535 def : InstRW<[WriteMoveBE32mr], (instregex "MOVBE32mr")>;
538 def WriteMoveBE64mr : SchedWriteRes<[HWPort06, HWPort15, HWPort237, HWPort4]> {
541 def : InstRW<[WriteMoveBE64mr], (instregex "MOVBE64mr")>;
543 //-- Arithmetic instructions --//
547 def : InstRW<[Write2P0156_2P237_P4],
548 (instregex "(ADD|SUB)(8|16|32|64)m(r|i)",
549 "(ADD|SUB)(8|16|32|64)mi8", "(ADD|SUB)64mi32")>;
553 def : InstRW<[Write2P0156_Lat2], (instregex "(ADC|SBB)(8|16|32|64)r(r|i)",
554 "(ADC|SBB)(16|32|64)ri8",
556 "(ADC|SBB)(8|16|32|64)rr_REV")>;
559 def : InstRW<[Write2P0156_Lat2Ld, ReadAfterLd], (instregex "(ADC|SBB)(8|16|32|64)rm")>;
562 def : InstRW<[Write3P0156_2P237_P4],
563 (instregex "(ADC|SBB)(8|16|32|64)m(r|i)",
564 "(ADC|SBB)(16|32|64)mi8",
569 def : InstRW<[WriteP0156_2P237_P4],
570 (instregex "(INC|DEC|NOT|NEG)(8|16|32|64)m",
571 "(INC|DEC)64(16|32)m")>;
575 def WriteMul16 : SchedWriteRes<[HWPort1, HWPort0156]> {
579 def : InstRW<[WriteMul16], (instregex "IMUL16r", "MUL16r")>;
582 def WriteMul16Ld : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> {
586 def : InstRW<[WriteMul16Ld], (instregex "IMUL16m", "MUL16m")>;
589 def WriteMul32 : SchedWriteRes<[HWPort1, HWPort0156]> {
593 def : InstRW<[WriteMul32], (instregex "IMUL32r", "MUL32r")>;
596 def WriteMul32Ld : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> {
600 def : InstRW<[WriteMul32Ld], (instregex "IMUL32m", "MUL32m")>;
603 def WriteMul64 : SchedWriteRes<[HWPort1, HWPort6]> {
607 def : InstRW<[WriteMul64], (instregex "IMUL64r", "MUL64r")>;
610 def WriteMul64Ld : SchedWriteRes<[HWPort1, HWPort6, HWPort23]> {
614 def : InstRW<[WriteMul64Ld], (instregex "IMUL64m", "MUL64m")>;
617 def WriteMul16rri : SchedWriteRes<[HWPort1, HWPort0156]> {
621 def : InstRW<[WriteMul16rri], (instregex "IMUL16rri", "IMUL16rri8")>;
624 def WriteMul16rmi : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> {
628 def : InstRW<[WriteMul16rmi], (instregex "IMUL16rmi", "IMUL16rmi8")>;
632 def WriteMulX32 : SchedWriteRes<[HWPort1, HWPort056]> {
635 let ResourceCycles = [1, 2];
637 def : InstRW<[WriteMulX32], (instregex "MULX32rr")>;
640 def WriteMulX32Ld : SchedWriteRes<[HWPort1, HWPort056, HWPort23]> {
643 let ResourceCycles = [1, 2, 1];
645 def : InstRW<[WriteMulX32Ld], (instregex "MULX32rm")>;
648 def WriteMulX64 : SchedWriteRes<[HWPort1, HWPort6]> {
652 def : InstRW<[WriteMulX64], (instregex "MULX64rr")>;
655 def WriteMulX64Ld : SchedWriteRes<[HWPort1, HWPort6, HWPort23]> {
659 def : InstRW<[WriteMulX64Ld], (instregex "MULX64rm")>;
663 def WriteDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
667 def : InstRW<[WriteDiv8], (instregex "DIV8r")>;
670 def WriteDiv16 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
672 let NumMicroOps = 10;
674 def : InstRW<[WriteDiv16], (instregex "DIV16r")>;
677 def WriteDiv32 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
679 let NumMicroOps = 10;
681 def : InstRW<[WriteDiv32], (instregex "DIV32r")>;
684 def WriteDiv64 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
686 let NumMicroOps = 36;
688 def : InstRW<[WriteDiv64], (instregex "DIV64r")>;
692 def WriteIDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
696 def : InstRW<[WriteIDiv8], (instregex "IDIV8r")>;
699 def WriteIDiv16 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
701 let NumMicroOps = 10;
703 def : InstRW<[WriteIDiv16], (instregex "IDIV16r")>;
706 def WriteIDiv32 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
710 def : InstRW<[WriteIDiv32], (instregex "IDIV32r")>;
713 def WriteIDiv64 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
715 let NumMicroOps = 59;
717 def : InstRW<[WriteIDiv64], (instregex "IDIV64r")>;
719 //-- Logic instructions --//
723 def : InstRW<[Write2P0156_2P237_P4],
724 (instregex "(AND|OR|XOR)(8|16|32|64)m(r|i)",
725 "(AND|OR|XOR)(8|16|32|64)mi8", "(AND|OR|XOR)64mi32")>;
729 def WriteShiftRMW : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
731 let ResourceCycles = [2, 1, 1];
733 def : InstRW<[WriteShiftRMW], (instregex "S(A|H)(R|L)(8|16|32|64)m(i|1)")>;
736 def : InstRW<[Write3P06_Lat2], (instregex "S(A|H)(R|L)(8|16|32|64)rCL")>;
739 def WriteShiftClLdRMW : SchedWriteRes<[HWPort06, HWPort23, HWPort4]> {
741 let ResourceCycles = [3, 2, 1];
743 def : InstRW<[WriteShiftClLdRMW], (instregex "S(A|H)(R|L)(8|16|32|64)mCL")>;
747 def : InstRW<[Write2P06], (instregex "RO(R|L)(8|16|32|64)r1")>;
750 def WriteRotateRMW : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
752 let ResourceCycles = [2, 2, 1];
754 def : InstRW<[WriteRotateRMW], (instregex "RO(R|L)(8|16|32|64)mi")>;
757 def : InstRW<[Write3P06_Lat2], (instregex "RO(R|L)(8|16|32|64)rCL")>;
760 def WriteRotateRMWCL : SchedWriteRes<[]> {
763 def : InstRW<[WriteRotateRMWCL], (instregex "RO(R|L)(8|16|32|64)mCL")>;
767 def WriteRCr1 : SchedWriteRes<[HWPort06, HWPort0156]> {
770 let ResourceCycles = [2, 1];
772 def : InstRW<[WriteRCr1], (instregex "RC(R|L)(8|16|32|64)r1")>;
775 def WriteRCm1 : SchedWriteRes<[]> {
778 def : InstRW<[WriteRCm1], (instregex "RC(R|L)(8|16|32|64)m1")>;
781 def WriteRCri : SchedWriteRes<[HWPort0156]> {
785 def : InstRW<[WriteRCri], (instregex "RC(R|L)(8|16|32|64)r(i|CL)")>;
788 def WriteRCmi : SchedWriteRes<[]> {
789 let NumMicroOps = 11;
791 def : InstRW<[WriteRCmi], (instregex "RC(R|L)(8|16|32|64)m(i|CL)")>;
795 def WriteShDrr : SchedWriteRes<[HWPort1]> {
798 def : InstRW<[WriteShDrr], (instregex "SH(R|L)D(16|32|64)rri8")>;
801 def WriteShDmr : SchedWriteRes<[]> {
804 def : InstRW<[WriteShDmr], (instregex "SH(R|L)D(16|32|64)mri8")>;
807 def WriteShlDCL : SchedWriteRes<[HWPort0156]> {
811 def : InstRW<[WriteShlDCL], (instregex "SHLD(16|32|64)rrCL")>;
814 def WriteShrDCL : SchedWriteRes<[HWPort0156]> {
818 def : InstRW<[WriteShrDCL], (instregex "SHRD(16|32|64)rrCL")>;
821 def WriteShDmrCL : SchedWriteRes<[]> {
824 def : InstRW<[WriteShDmrCL], (instregex "SH(R|L)D(16|32|64)mrCL")>;
828 def : InstRW<[WriteShift], (instregex "BT(16|32|64)r(r|i8)")>;
831 def WriteBTmr : SchedWriteRes<[]> {
832 let NumMicroOps = 10;
834 def : InstRW<[WriteBTmr], (instregex "BT(16|32|64)mr")>;
837 def : InstRW<[WriteShiftLd], (instregex "BT(16|32|64)mi8")>;
841 def : InstRW<[WriteShift], (instregex "BT(R|S|C)(16|32|64)r(r|i8)")>;
844 def WriteBTRSCmr : SchedWriteRes<[]> {
845 let NumMicroOps = 11;
847 def : InstRW<[WriteBTRSCmr], (instregex "BT(R|S|C)(16|32|64)mr")>;
850 def : InstRW<[WriteShiftLd], (instregex "BT(R|S|C)(16|32|64)mi8")>;
854 def : InstRW<[WriteP1_Lat3], (instregex "BS(R|F)(16|32|64)rr")>;
856 def : InstRW<[WriteP1_Lat3Ld], (instregex "BS(R|F)(16|32|64)rm")>;
860 def : InstRW<[WriteShift],
861 (instregex "SET(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)r")>;
863 def WriteSetCCm : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
866 def : InstRW<[WriteSetCCm],
867 (instregex "SET(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)m")>;
870 def WriteCldStd : SchedWriteRes<[HWPort15, HWPort6]> {
873 def : InstRW<[WriteCldStd], (instregex "STD", "CLD")>;
877 def : InstRW<[WriteP1_Lat3], (instregex "(L|TZCNT)(16|32|64)rr")>;
879 def : InstRW<[WriteP1_Lat3Ld], (instregex "(L|TZCNT)(16|32|64)rm")>;
883 def : InstRW<[WriteP15], (instregex "ANDN(32|64)rr")>;
885 def : InstRW<[WriteP15Ld], (instregex "ANDN(32|64)rm")>;
889 def : InstRW<[WriteP15], (instregex "BLS(I|MSK|R)(32|64)rr")>;
891 def : InstRW<[WriteP15Ld], (instregex "BLS(I|MSK|R)(32|64)rm")>;
895 def : InstRW<[Write2P0156_Lat2], (instregex "BEXTR(32|64)rr")>;
897 def : InstRW<[Write2P0156_Lat2Ld], (instregex "BEXTR(32|64)rm")>;
901 def : InstRW<[WriteP15], (instregex "BZHI(32|64)rr")>;
903 def : InstRW<[WriteP15Ld], (instregex "BZHI(32|64)rm")>;
907 def : InstRW<[WriteP1_Lat3], (instregex "PDEP(32|64)rr", "PEXT(32|64)rr")>;
909 def : InstRW<[WriteP1_Lat3Ld], (instregex "PDEP(32|64)rm", "PEXT(32|64)rm")>;
911 //-- Control transfer instructions --//
914 def WriteJCXZ : SchedWriteRes<[HWPort0156, HWPort6]> {
917 def : InstRW<[WriteJCXZ], (instregex "JCXZ", "JECXZ_(32|64)", "JRCXZ")>;
920 def WriteLOOP : SchedWriteRes<[]> {
923 def : InstRW<[WriteLOOP], (instregex "LOOP")>;
926 def WriteLOOPE : SchedWriteRes<[]> {
927 let NumMicroOps = 11;
929 def : InstRW<[WriteLOOPE], (instregex "LOOPE", "LOOPNE")>;
933 def WriteCALLr : SchedWriteRes<[HWPort237, HWPort4, HWPort6]> {
936 def : InstRW<[WriteCALLr], (instregex "CALL(16|32)r")>;
939 def WriteCALLm : SchedWriteRes<[HWPort237, HWPort4, HWPort6]> {
941 let ResourceCycles = [2, 1, 1];
943 def : InstRW<[WriteCALLm], (instregex "CALL(16|32)m")>;
946 def WriteRET : SchedWriteRes<[HWPort237, HWPort6]> {
949 def : InstRW<[WriteRET], (instregex "RET(L|Q|W)", "LRET(L|Q|W)")>;
952 def WriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> {
954 let ResourceCycles = [1, 2, 1];
956 def : InstRW<[WriteRETI], (instregex "RETI(L|Q|W)", "LRETI(L|Q|W)")>;
960 def WriteBOUND : SchedWriteRes<[]> {
961 let NumMicroOps = 15;
963 def : InstRW<[WriteBOUND], (instregex "BOUNDS(16|32)rm")>;
966 def WriteINTO : SchedWriteRes<[]> {
969 def : InstRW<[WriteINTO], (instregex "INTO")>;
971 //-- String instructions --//
974 def : InstRW<[Write2P0156_P23], (instregex "LODS(B|W)")>;
977 def : InstRW<[WriteP0156_P23], (instregex "LODS(L|Q)")>;
980 def WriteSTOS : SchedWriteRes<[HWPort23, HWPort0156, HWPort4]> {
983 def : InstRW<[WriteSTOS], (instregex "STOS(B|L|Q|W)")>;
986 def WriteMOVS : SchedWriteRes<[HWPort23, HWPort4, HWPort0156]> {
989 let ResourceCycles = [2, 1, 2];
991 def : InstRW<[WriteMOVS], (instregex "MOVS(B|L|Q|W)")>;
994 def : InstRW<[Write2P0156_P23], (instregex "SCAS(B|W|L|Q)")>;
997 def WriteCMPS : SchedWriteRes<[HWPort23, HWPort0156]> {
1000 let ResourceCycles = [2, 3];
1002 def : InstRW<[WriteCMPS], (instregex "CMPS(B|L|Q|W)")>;
1004 //-- Synchronization instructions --//
1007 def WriteXADD : SchedWriteRes<[]> {
1008 let NumMicroOps = 5;
1010 def : InstRW<[WriteXADD], (instregex "XADD(8|16|32|64)rm")>;
1013 def WriteCMPXCHG : SchedWriteRes<[]> {
1014 let NumMicroOps = 6;
1016 def : InstRW<[WriteCMPXCHG], (instregex "CMPXCHG(8|16|32|64)rm")>;
1019 def WriteCMPXCHG8B : SchedWriteRes<[]> {
1020 let NumMicroOps = 15;
1022 def : InstRW<[WriteCMPXCHG8B], (instregex "CMPXCHG8B")>;
1025 def WriteCMPXCHG16B : SchedWriteRes<[]> {
1026 let NumMicroOps = 22;
1028 def : InstRW<[WriteCMPXCHG16B], (instregex "CMPXCHG16B")>;
1033 def WritePAUSE : SchedWriteRes<[HWPort05, HWPort6]> {
1034 let NumMicroOps = 5;
1035 let ResourceCycles = [1, 3];
1037 def : InstRW<[WritePAUSE], (instregex "PAUSE")>;
1040 def : InstRW<[Write2P0156_P23], (instregex "LEAVE")>;
1043 def WriteXGETBV : SchedWriteRes<[]> {
1044 let NumMicroOps = 8;
1046 def : InstRW<[WriteXGETBV], (instregex "XGETBV")>;
1049 def WriteRDTSC : SchedWriteRes<[]> {
1050 let NumMicroOps = 15;
1052 def : InstRW<[WriteRDTSC], (instregex "RDTSC")>;
1055 def WriteRDPMC : SchedWriteRes<[]> {
1056 let NumMicroOps = 34;
1058 def : InstRW<[WriteRDPMC], (instregex "RDPMC")>;
1061 def WriteRDRAND : SchedWriteRes<[HWPort23, HWPort015]> {
1062 let NumMicroOps = 17;
1063 let ResourceCycles = [1, 16];
1065 def : InstRW<[WriteRDRAND], (instregex "RDRAND(16|32|64)r")>;
1067 //=== Floating Point x87 Instructions ===//
1068 //-- Move instructions --//
1072 def : InstRW<[WriteP01], (instregex "LD_Frr")>;
1074 def WriteLD_F80m : SchedWriteRes<[HWPort01, HWPort23]> {
1076 let NumMicroOps = 4;
1077 let ResourceCycles = [2, 2];
1079 def : InstRW<[WriteLD_F80m], (instregex "LD_F80m")>;
1083 def WriteFBLD : SchedWriteRes<[]> {
1085 let NumMicroOps = 43;
1087 def : InstRW<[WriteFBLD], (instregex "FBLDm")>;
1091 def : InstRW<[WriteP01], (instregex "ST_(F|FP)rr")>;
1094 def WriteST_FP80m : SchedWriteRes<[HWPort0156, HWPort23, HWPort4]> {
1095 let NumMicroOps = 7;
1096 let ResourceCycles = [3, 2, 2];
1098 def : InstRW<[WriteST_FP80m], (instregex "ST_FP80m")>;
1102 def WriteFBSTP : SchedWriteRes<[]> {
1103 let NumMicroOps = 226;
1105 def : InstRW<[WriteFBSTP], (instregex "FBSTPm")>;
1108 def : InstRW<[WriteNop], (instregex "XCH_F")>;
1111 def WriteFILD : SchedWriteRes<[HWPort01, HWPort23]> {
1113 let NumMicroOps = 2;
1115 def : InstRW<[WriteFILD], (instregex "ILD_F(16|32|64)m")>;
1118 def WriteFIST : SchedWriteRes<[HWPort1, HWPort23, HWPort4]> {
1120 let NumMicroOps = 3;
1122 def : InstRW<[WriteFIST], (instregex "IST_(F|FP)(16|32)m")>;
1125 def : InstRW<[WriteP01], (instregex "LD_F0")>;
1128 def : InstRW<[Write2P01], (instregex "LD_F1")>;
1130 // FLDPI FLDL2E etc.
1131 def : InstRW<[Write2P01], (instregex "FLDPI", "FLDL2(T|E)" "FLDL(G|N)2")>;
1134 def WriteFCMOVcc : SchedWriteRes<[HWPort0, HWPort5]> {
1136 let NumMicroOps = 3;
1137 let ResourceCycles = [2, 1];
1139 def : InstRW<[WriteFCMOVcc], (instregex "CMOV(B|BE|P|NB|NBE|NE|NP)_F")>;
1143 def WriteFNSTSW : SchedWriteRes<[HWPort0, HWPort0156]> {
1144 let NumMicroOps = 2;
1146 def : InstRW<[WriteFNSTSW], (instregex "FNSTSW16r")>;
1149 def WriteFNSTSWm : SchedWriteRes<[HWPort0, HWPort4, HWPort237]> {
1151 let NumMicroOps = 3;
1153 def : InstRW<[WriteFNSTSWm], (instregex "FNSTSWm")>;
1156 def WriteFLDCW : SchedWriteRes<[HWPort01, HWPort23, HWPort6]> {
1158 let NumMicroOps = 3;
1160 def : InstRW<[WriteFLDCW], (instregex "FLDCW16m")>;
1163 def WriteFNSTCW : SchedWriteRes<[HWPort237, HWPort4, HWPort6]> {
1164 let NumMicroOps = 3;
1166 def : InstRW<[WriteFNSTCW], (instregex "FNSTCW16m")>;
1169 def : InstRW<[WriteP01], (instregex "FINCSTP", "FDECSTP")>;
1172 def : InstRW<[WriteP01], (instregex "FFREE")>;
1175 def WriteFNSAVE : SchedWriteRes<[]> {
1176 let NumMicroOps = 147;
1178 def : InstRW<[WriteFNSAVE], (instregex "FSAVEm")>;
1181 def WriteFRSTOR : SchedWriteRes<[]> {
1182 let NumMicroOps = 90;
1184 def : InstRW<[WriteFRSTOR], (instregex "FRSTORm")>;
1186 //-- Arithmetic instructions --//
1189 def : InstRW<[WriteP0], (instregex "ABS_F")>;
1192 def : InstRW<[WriteP0], (instregex "CHS_F")>;
1194 // FCOM(P) FUCOM(P).
1196 def : InstRW<[WriteP1], (instregex "COM_FST0r", "COMP_FST0r", "UCOM_Fr",
1199 def : InstRW<[WriteP1_P23], (instregex "FCOM(32|64)m", "FCOMP(32|64)m")>;
1203 def : InstRW<[Write2P01], (instregex "FCOMPP", "UCOM_FPPr")>;
1205 // FCOMI(P) FUCOMI(P).
1207 def : InstRW<[Write3P01], (instregex "COM_FIr", "COM_FIPr", "UCOM_FIr",
1211 def : InstRW<[Write2P1_P23], (instregex "FICOM(16|32)m", "FICOMP(16|32)m")>;
1214 def : InstRW<[WriteP1], (instregex "TST_F")>;
1217 def : InstRW<[Write2P1], (instregex "FXAM")>;
1220 def WriteFPREM : SchedWriteRes<[]> {
1222 let NumMicroOps = 28;
1224 def : InstRW<[WriteFPREM], (instregex "FPREM")>;
1227 def WriteFPREM1 : SchedWriteRes<[]> {
1229 let NumMicroOps = 41;
1231 def : InstRW<[WriteFPREM1], (instregex "FPREM1")>;
1234 def WriteFRNDINT : SchedWriteRes<[]> {
1236 let NumMicroOps = 17;
1238 def : InstRW<[WriteFRNDINT], (instregex "FRNDINT")>;
1240 //-- Math instructions --//
1243 def WriteFSCALE : SchedWriteRes<[]> {
1244 let Latency = 75; // 49-125
1245 let NumMicroOps = 50; // 25-75
1247 def : InstRW<[WriteFSCALE], (instregex "FSCALE")>;
1250 def WriteFXTRACT : SchedWriteRes<[]> {
1252 let NumMicroOps = 17;
1254 def : InstRW<[WriteFXTRACT], (instregex "FXTRACT")>;
1256 //-- Other instructions --//
1259 def : InstRW<[WriteP01], (instregex "FNOP")>;
1262 def : InstRW<[Write2P01], (instregex "WAIT")>;
1265 def : InstRW<[Write5P0156], (instregex "FNCLEX")>;
1268 def WriteFNINIT : SchedWriteRes<[]> {
1269 let NumMicroOps = 26;
1271 def : InstRW<[WriteFNINIT], (instregex "FNINIT")>;
1273 //=== Integer MMX and XMM Instructions ===//
1274 //-- Move instructions --//
1278 def : InstRW<[WriteP0], (instregex "MMX_MOVD64grr", "MMX_MOVD64from64rr",
1279 "VMOVPDI2DIrr", "MOVPDI2DIrr")>;
1282 def : InstRW<[WriteP5], (instregex "MMX_MOVD64rr", "MMX_MOVD64to64rr",
1283 "VMOVDI2PDIrr", "MOVDI2PDIrr")>;
1287 def : InstRW<[WriteP0], (instregex "VMOVPQIto64rr")>;
1290 def : InstRW<[WriteP5], (instregex "VMOV64toPQIrr", "VMOVZQI2PQIrr")>;
1293 def : InstRW<[WriteP015], (instregex "MMX_MOVQ64rr")>;
1297 def : InstRW<[WriteP015], (instregex "MOVDQ(A|U)rr", "VMOVDQ(A|U)rr",
1298 "MOVDQ(A|U)rr_REV", "VMOVDQ(A|U)rr_REV",
1299 "VMOVDQ(A|U)Yrr", "VMOVDQ(A|U)Yrr_REV")>;
1302 def : InstRW<[WriteP01_P5], (instregex "MMX_MOVDQ2Qrr")>;
1305 def : InstRW<[WriteP015], (instregex "MMX_MOVQ2DQrr")>;
1310 def WriteMMXPACKSSrr : SchedWriteRes<[HWPort5]> {
1312 let NumMicroOps = 3;
1313 let ResourceCycles = [3];
1315 def : InstRW<[WriteMMXPACKSSrr], (instregex "MMX_PACKSSDWirr",
1316 "MMX_PACKSSWBirr", "MMX_PACKUSWBirr")>;
1319 def WriteMMXPACKSSrm : SchedWriteRes<[HWPort23, HWPort5]> {
1321 let NumMicroOps = 3;
1322 let ResourceCycles = [1, 3];
1324 def : InstRW<[WriteMMXPACKSSrm], (instregex "MMX_PACKSSDWirm",
1325 "MMX_PACKSSWBirm", "MMX_PACKUSWBirm")>;
1327 // VPMOVSX/ZX BW BD BQ DW DQ.
1329 def WriteVPMOVSX : SchedWriteRes<[HWPort5]> {
1331 let NumMicroOps = 1;
1333 def : InstRW<[WriteVPMOVSX], (instregex "VPMOV(SX|ZX)(BW|BQ|DW|DQ)Yrr")>;
1337 def WritePBLENDWr : SchedWriteRes<[HWPort5]>;
1338 def : InstRW<[WritePBLENDWr], (instregex "(V?)PBLENDW(Y?)rri")>;
1341 def WritePBLENDWm : SchedWriteRes<[HWPort5, HWPort23]> {
1342 let NumMicroOps = 2;
1344 let ResourceCycles = [1, 1];
1346 def : InstRW<[WritePBLENDWm, ReadAfterLd], (instregex "(V?)PBLENDW(Y?)rmi")>;
1350 def WriteVPBLENDDr : SchedWriteRes<[HWPort015]>;
1351 def : InstRW<[WriteVPBLENDDr], (instregex "VPBLENDD(Y?)rri")>;
1354 def WriteVPBLENDDm : SchedWriteRes<[HWPort015, HWPort23]> {
1355 let NumMicroOps = 2;
1357 let ResourceCycles = [1, 1];
1359 def : InstRW<[WriteVPBLENDDm, ReadAfterLd], (instregex "VPBLENDD(Y?)rmi")>;
1362 def WriteMASKMOVQ : SchedWriteRes<[HWPort0, HWPort4, HWPort23]> {
1364 let NumMicroOps = 4;
1365 let ResourceCycles = [1, 1, 2];
1367 def : InstRW<[WriteMASKMOVQ], (instregex "MMX_MASKMOVQ(64)?")>;
1370 def WriteMASKMOVDQU : SchedWriteRes<[HWPort04, HWPort56, HWPort23]> {
1372 let NumMicroOps = 10;
1373 let ResourceCycles = [4, 2, 4];
1375 def : InstRW<[WriteMASKMOVDQU], (instregex "(V?)MASKMOVDQU(64)?")>;
1379 def WriteVPMASKMOVr : SchedWriteRes<[HWPort5, HWPort23]> {
1381 let NumMicroOps = 3;
1382 let ResourceCycles = [2, 1];
1384 def : InstRW<[WriteVPMASKMOVr, ReadAfterLd],
1385 (instregex "VPMASKMOV(D|Q)(Y?)rm")>;
1388 def WriteVPMASKMOVm : SchedWriteRes<[HWPort0, HWPort1, HWPort4, HWPort23]> {
1390 let NumMicroOps = 4;
1391 let ResourceCycles = [1, 1, 1, 1];
1393 def : InstRW<[WriteVPMASKMOVm], (instregex "VPMASKMOV(D|Q)(Y?)mr")>;
1396 def WritePMOVMSKB : SchedWriteRes<[HWPort0]> {
1399 def : InstRW<[WritePMOVMSKB], (instregex "(V|MMX_)?PMOVMSKB(Y?)rr")>;
1403 def WritePEXTRr : SchedWriteRes<[HWPort0, HWPort5]> {
1405 let NumMicroOps = 2;
1406 let ResourceCycles = [1, 1];
1408 def : InstRW<[WritePEXTRr], (instregex "PEXTR(B|W|D|Q)rr", "MMX_PEXTRWirri")>;
1411 def WritePEXTRm : SchedWriteRes<[HWPort23, HWPort4, HWPort5]> {
1412 let NumMicroOps = 3;
1413 let ResourceCycles = [1, 1, 1];
1415 def : InstRW<[WritePEXTRm], (instregex "PEXTR(B|W|D|Q)mr")>;
1419 def WriteVPBROADCAST128Ld : SchedWriteRes<[HWPort01, HWPort23, HWPort5]> {
1421 let NumMicroOps = 3;
1422 let ResourceCycles = [1, 1, 1];
1424 def : InstRW<[WriteVPBROADCAST128Ld, ReadAfterLd],
1425 (instregex "VPBROADCAST(B|W)rm")>;
1428 def WriteVPBROADCAST256Ld : SchedWriteRes<[HWPort01, HWPort23, HWPort5]> {
1430 let NumMicroOps = 3;
1431 let ResourceCycles = [1, 1, 1];
1433 def : InstRW<[WriteVPBROADCAST256Ld, ReadAfterLd],
1434 (instregex "VPBROADCAST(B|W)Yrm")>;
1438 def WriteVPGATHERDD128 : SchedWriteRes<[]> {
1439 let NumMicroOps = 20;
1441 def : InstRW<[WriteVPGATHERDD128, ReadAfterLd], (instregex "VPGATHERDDrm")>;
1444 def WriteVPGATHERDD256 : SchedWriteRes<[]> {
1445 let NumMicroOps = 34;
1447 def : InstRW<[WriteVPGATHERDD256, ReadAfterLd], (instregex "VPGATHERDDYrm")>;
1451 def WriteVPGATHERQD128 : SchedWriteRes<[]> {
1452 let NumMicroOps = 15;
1454 def : InstRW<[WriteVPGATHERQD128, ReadAfterLd], (instregex "VPGATHERQDrm")>;
1457 def WriteVPGATHERQD256 : SchedWriteRes<[]> {
1458 let NumMicroOps = 22;
1460 def : InstRW<[WriteVPGATHERQD256, ReadAfterLd], (instregex "VPGATHERQDYrm")>;
1464 def WriteVPGATHERDQ128 : SchedWriteRes<[]> {
1465 let NumMicroOps = 12;
1467 def : InstRW<[WriteVPGATHERDQ128, ReadAfterLd], (instregex "VPGATHERDQrm")>;
1470 def WriteVPGATHERDQ256 : SchedWriteRes<[]> {
1471 let NumMicroOps = 20;
1473 def : InstRW<[WriteVPGATHERDQ256, ReadAfterLd], (instregex "VPGATHERDQYrm")>;
1477 def WriteVPGATHERQQ128 : SchedWriteRes<[]> {
1478 let NumMicroOps = 14;
1480 def : InstRW<[WriteVPGATHERQQ128, ReadAfterLd], (instregex "VPGATHERQQrm")>;
1483 def WriteVPGATHERQQ256 : SchedWriteRes<[]> {
1484 let NumMicroOps = 22;
1486 def : InstRW<[WriteVPGATHERQQ256, ReadAfterLd], (instregex "VPGATHERQQYrm")>;
1488 //-- Arithmetic instructions --//
1490 // PHADD|PHSUB (S) W/D.
1492 def WritePHADDSUBr : SchedWriteRes<[HWPort1, HWPort5]> {
1494 let NumMicroOps = 3;
1495 let ResourceCycles = [1, 2];
1497 def : InstRW<[WritePHADDSUBr], (instregex "MMX_PHADD(W?)rr64",
1499 "MMX_PHSUB(W|D)rr64",
1501 "(V?)PH(ADD|SUB)(W|D)(Y?)rr",
1502 "(V?)PH(ADD|SUB)SWrr(256)?")>;
1505 def WritePHADDSUBm : SchedWriteRes<[HWPort1, HWPort5, HWPort23]> {
1507 let NumMicroOps = 3;
1508 let ResourceCycles = [1, 2, 1];
1510 def : InstRW<[WritePHADDSUBm, ReadAfterLd],
1511 (instregex "MMX_PHADD(W?)rm64",
1513 "MMX_PHSUB(W|D)rm64",
1515 "(V?)PH(ADD|SUB)(W|D)(Y?)rm",
1516 "(V?)PH(ADD|SUB)SWrm(128|256)?")>;
1520 def WritePCMPGTQr : SchedWriteRes<[HWPort0]> {
1522 let NumMicroOps = 1;
1524 def : InstRW<[WritePCMPGTQr], (instregex "(V?)PCMPGTQ(Y?)rr")>;
1527 def WritePCMPGTQm : SchedWriteRes<[HWPort0, HWPort23]> {
1529 let NumMicroOps = 2;
1530 let ResourceCycles = [1, 1];
1532 def : InstRW<[WritePCMPGTQm, ReadAfterLd], (instregex "(V?)PCMPGTQ(Y?)rm")>;
1536 def WritePMULLDr : SchedWriteRes<[HWPort0]> {
1538 let NumMicroOps = 2;
1539 let ResourceCycles = [2];
1541 def : InstRW<[WritePMULLDr], (instregex "(V?)PMULLD(Y?)rr")>;
1544 def WritePMULLDm : SchedWriteRes<[HWPort0, HWPort23]> {
1546 let NumMicroOps = 3;
1547 let ResourceCycles = [2, 1];
1549 def : InstRW<[WritePMULLDm, ReadAfterLd], (instregex "(V?)PMULLD(Y?)rm")>;
1551 //-- Logic instructions --//
1555 def WritePTESTr : SchedWriteRes<[HWPort0, HWPort5]> {
1557 let NumMicroOps = 2;
1558 let ResourceCycles = [1, 1];
1560 def : InstRW<[WritePTESTr], (instregex "(V?)PTEST(Y?)rr")>;
1563 def WritePTESTm : SchedWriteRes<[HWPort0, HWPort5, HWPort23]> {
1565 let NumMicroOps = 3;
1566 let ResourceCycles = [1, 1, 1];
1568 def : InstRW<[WritePTESTr], (instregex "(V?)PTEST(Y?)rm")>;
1570 // PSLL,PSRL,PSRA W/D/Q.
1572 def WritePShift : SchedWriteRes<[HWPort0, HWPort5]> {
1574 let NumMicroOps = 2;
1575 let ResourceCycles = [1, 1];
1577 def : InstRW<[WritePShift], (instregex "(V?)PS(LL|RL|RA)(W|D|Q)(Y?)rr")>;
1580 def : InstRW<[WriteP5], (instregex "(V?)PS(R|L)LDQ(Y?)ri")>;
1585 def WriteEMMS : SchedWriteRes<[]> {
1587 let NumMicroOps = 31;
1589 def : InstRW<[WriteEMMS], (instregex "MMX_EMMS")>;
1591 //=== Floating Point XMM and YMM Instructions ===//
1592 //-- Move instructions --//
1596 def WriteMOVMSKPr : SchedWriteRes<[HWPort0]> {
1599 def : InstRW<[WriteMOVMSKPr], (instregex "(V?)MOVMSKP(S|D)rr")>;
1602 def WriteVMOVMSKPYr : SchedWriteRes<[HWPort0]> {
1605 def : InstRW<[WriteVMOVMSKPYr], (instregex "VMOVMSKP(S|D)Yrr")>;
1608 def : InstRW<[WriteFShuffle256], (instregex "VPERM2F128rr")>;
1609 def : InstRW<[WriteFShuffle256Ld, ReadAfterLd], (instregex "VPERM2F128rm")>;
1612 def : InstRW<[WriteFVarBlend], (instregex "BLENDVP(S|D)rr0")>;
1613 def : InstRW<[WriteFVarBlendLd, ReadAfterLd], (instregex "BLENDVP(S|D)rm0")>;
1616 def : InstRW<[WriteLoad], (instregex "VBROADCASTF128")>;
1620 def WriteEXTRACTPSr : SchedWriteRes<[HWPort0, HWPort5]> {
1621 let NumMicroOps = 2;
1622 let ResourceCycles = [1, 1];
1624 def : InstRW<[WriteEXTRACTPSr], (instregex "(V?)EXTRACTPSrr")>;
1627 def WriteEXTRACTPSm : SchedWriteRes<[HWPort0, HWPort5, HWPort23]> {
1629 let NumMicroOps = 3;
1630 let ResourceCycles = [1, 1, 1];
1632 def : InstRW<[WriteEXTRACTPSm], (instregex "(V?)EXTRACTPSmr")>;
1636 def : InstRW<[WriteFShuffle256], (instregex "VEXTRACTF128rr")>;
1639 def WriteVEXTRACTF128m : SchedWriteRes<[HWPort23, HWPort4]> {
1641 let NumMicroOps = 2;
1642 let ResourceCycles = [1, 1];
1644 def : InstRW<[WriteVEXTRACTF128m], (instregex "VEXTRACTF128mr")>;
1648 def : InstRW<[WriteFShuffle256], (instregex "VINSERTF128rr")>;
1651 def WriteVINSERTF128m : SchedWriteRes<[HWPort015, HWPort23]> {
1653 let NumMicroOps = 2;
1654 let ResourceCycles = [1, 1];
1656 def : InstRW<[WriteFShuffle256, ReadAfterLd], (instregex "VINSERTF128rm")>;
1660 def WriteVMASKMOVPrm : SchedWriteRes<[HWPort5, HWPort23]> {
1662 let NumMicroOps = 3;
1663 let ResourceCycles = [2, 1];
1665 def : InstRW<[WriteVMASKMOVPrm], (instregex "VMASKMOVP(S|D)(Y?)rm")>;
1668 def WriteVMASKMOVPmr : SchedWriteRes<[HWPort0, HWPort1, HWPort4, HWPort23]> {
1670 let NumMicroOps = 4;
1671 let ResourceCycles = [1, 1, 1, 1];
1673 def : InstRW<[WriteVMASKMOVPmr], (instregex "VMASKMOVP(S|D)mr")>;
1676 def WriteVMASKMOVPYmr : SchedWriteRes<[HWPort0, HWPort1, HWPort4, HWPort23]> {
1678 let NumMicroOps = 4;
1679 let ResourceCycles = [1, 1, 1, 1];
1681 def : InstRW<[WriteVMASKMOVPYmr], (instregex "VMASKMOVP(S|D)Ymr")>;
1685 def WriteVGATHERDPS128 : SchedWriteRes<[]> {
1686 let NumMicroOps = 20;
1688 def : InstRW<[WriteVGATHERDPS128, ReadAfterLd], (instregex "VGATHERDPSrm")>;
1691 def WriteVGATHERDPS256 : SchedWriteRes<[]> {
1692 let NumMicroOps = 34;
1694 def : InstRW<[WriteVGATHERDPS256, ReadAfterLd], (instregex "VGATHERDPSYrm")>;
1698 def WriteVGATHERQPS128 : SchedWriteRes<[]> {
1699 let NumMicroOps = 15;
1701 def : InstRW<[WriteVGATHERQPS128, ReadAfterLd], (instregex "VGATHERQPSrm")>;
1704 def WriteVGATHERQPS256 : SchedWriteRes<[]> {
1705 let NumMicroOps = 22;
1707 def : InstRW<[WriteVGATHERQPS256, ReadAfterLd], (instregex "VGATHERQPSYrm")>;
1711 def WriteVGATHERDPD128 : SchedWriteRes<[]> {
1712 let NumMicroOps = 12;
1714 def : InstRW<[WriteVGATHERDPD128, ReadAfterLd], (instregex "VGATHERDPDrm")>;
1717 def WriteVGATHERDPD256 : SchedWriteRes<[]> {
1718 let NumMicroOps = 20;
1720 def : InstRW<[WriteVGATHERDPD256, ReadAfterLd], (instregex "VGATHERDPDYrm")>;
1724 def WriteVGATHERQPD128 : SchedWriteRes<[]> {
1725 let NumMicroOps = 14;
1727 def : InstRW<[WriteVGATHERQPD128, ReadAfterLd], (instregex "VGATHERQPDrm")>;
1730 def WriteVGATHERQPD256 : SchedWriteRes<[]> {
1731 let NumMicroOps = 22;
1733 def : InstRW<[WriteVGATHERQPD256, ReadAfterLd], (instregex "VGATHERQPDYrm")>;
1735 //-- Conversion instructions --//
1739 def : InstRW<[WriteP1_P5_Lat4], (instregex "(V?)CVTPD2PSrr")>;
1742 def : InstRW<[WriteP1_P5_Lat4Ld], (instregex "(V?)CVTPD2PS(X?)rm")>;
1745 def WriteCVTPD2PSYrr : SchedWriteRes<[HWPort1, HWPort5]> {
1747 let NumMicroOps = 2;
1748 let ResourceCycles = [1, 1];
1750 def : InstRW<[WriteCVTPD2PSYrr], (instregex "(V?)CVTPD2PSYrr")>;
1753 def WriteCVTPD2PSYrm : SchedWriteRes<[HWPort1, HWPort5, HWPort23]> {
1755 let NumMicroOps = 3;
1756 let ResourceCycles = [1, 1, 1];
1758 def : InstRW<[WriteCVTPD2PSYrm], (instregex "(V?)CVTPD2PSYrm")>;
1762 def : InstRW<[WriteP1_P5_Lat4], (instregex "(Int_)?(V)?CVTSD2SSrr")>;
1765 def : InstRW<[WriteP1_P5_Lat4Ld], (instregex "(Int_)?(V)?CVTSD2SSrm")>;
1769 def WriteCVTPS2PDrr : SchedWriteRes<[HWPort0, HWPort5]> {
1771 let NumMicroOps = 2;
1772 let ResourceCycles = [1, 1];
1774 def : InstRW<[WriteCVTPS2PDrr], (instregex "(V?)CVTPS2PDrr")>;
1778 def WriteCVTPS2PDrm : SchedWriteRes<[HWPort0, HWPort23]> {
1780 let NumMicroOps = 2;
1781 let ResourceCycles = [1, 1];
1783 def : InstRW<[WriteCVTPS2PDrm], (instregex "(V?)CVTPS2PD(Y?)rm")>;
1786 def WriteVCVTPS2PDYrr : SchedWriteRes<[HWPort0, HWPort5]> {
1788 let NumMicroOps = 2;
1789 let ResourceCycles = [1, 1];
1791 def : InstRW<[WriteVCVTPS2PDYrr], (instregex "VCVTPS2PDYrr")>;
1795 def WriteCVTSS2SDrr : SchedWriteRes<[HWPort0, HWPort5]> {
1797 let NumMicroOps = 2;
1798 let ResourceCycles = [1, 1];
1800 def : InstRW<[WriteCVTSS2SDrr], (instregex "(Int_)?(V?)CVTSS2SDrr")>;
1803 def WriteCVTSS2SDrm : SchedWriteRes<[HWPort0, HWPort23]> {
1805 let NumMicroOps = 2;
1806 let ResourceCycles = [1, 1];
1808 def : InstRW<[WriteCVTSS2SDrm], (instregex "(Int_)?(V?)CVTSS2SDrm")>;
1812 def : InstRW<[WriteP1_P5_Lat4], (instregex "(V)?CVTDQ2PDrr")>;
1815 def : InstRW<[WriteP1_P5_Lat6], (instregex "VCVTDQ2PDYrr")>;
1819 def : InstRW<[WriteP1_P5_Lat4], (instregex "(V?)CVT(T?)PD2DQrr")>;
1821 def : InstRW<[WriteP1_P5_Lat4Ld], (instregex "(V?)CVT(T?)PD2DQrm")>;
1823 def : InstRW<[WriteP1_P5_Lat6], (instregex "VCVT(T?)PD2DQYrr")>;
1825 def : InstRW<[WriteP1_P5_Lat6Ld], (instregex "VCVT(T?)PD2DQYrm")>;
1829 def : InstRW<[WriteP1_P5_Lat4], (instregex "MMX_CVT(T?)PS2PIirr")>;
1833 def : InstRW<[WriteP1_P5_Lat4], (instregex "MMX_CVT(T?)PI2PDirr")>;
1837 def : InstRW<[WriteP1_P5_Lat4], (instregex "MMX_CVT(T?)PD2PIirr")>;
1841 def : InstRW<[WriteP1_P5_Lat4], (instregex "(Int_)?(V?)CVT(T?)SI2SS(64)?rr")>;
1845 def : InstRW<[WriteP0_P1_Lat4], (instregex "(Int_)?(V?)CVT(T?)SS2SI(64)?rr")>;
1847 def : InstRW<[WriteP0_P1_Lat4Ld], (instregex "(Int_)?(V?)CVT(T?)SS2SI(64)?rm")>;
1851 def : InstRW<[WriteP0_P1_Lat4], (instregex "(Int_)?(V?)CVTSI2SS(64)?rr")>;
1855 def : InstRW<[WriteP0_P1_Lat4], (instregex "(Int_)?(V?)CVT(T?)SD2SI(64)?rr")>;
1857 def : InstRW<[WriteP0_P1_Lat4Ld], (instregex "(Int_)?(V?)CVT(T?)SD2SI(64)?rm")>;
1861 def : InstRW<[WriteP1_P5_Lat4], (instregex "VCVTPS2PH(Y?)rr")>;
1863 def : InstRW<[WriteP1_P5_Lat4Ld, WriteRMW], (instregex "VCVTPS2PH(Y?)mr")>;
1867 def : InstRW<[WriteP1_P5_Lat4], (instregex "VCVTPH2PS(Y?)rr")>;
1869 //-- Arithmetic instructions --//
1873 def WriteHADDSUBPr : SchedWriteRes<[HWPort1, HWPort5]> {
1875 let NumMicroOps = 3;
1876 let ResourceCycles = [1, 2];
1878 def : InstRW<[WriteHADDSUBPr], (instregex "(V?)H(ADD|SUB)P(S|D)(Y?)rr")>;
1881 def WriteHADDSUBPm : SchedWriteRes<[HWPort1, HWPort5, HWPort23]> {
1883 let NumMicroOps = 4;
1884 let ResourceCycles = [1, 2, 1];
1886 def : InstRW<[WriteHADDSUBPm], (instregex "(V?)H(ADD|SUB)P(S|D)(Y?)rm")>;
1888 // MULL SS/SD PS/PD.
1890 def WriteMULr : SchedWriteRes<[HWPort01]> {
1893 def : InstRW<[WriteMULr], (instregex "(V?)MUL(P|S)(S|D)rr")>;
1896 def WriteMULm : SchedWriteRes<[HWPort01, HWPort23]> {
1898 let NumMicroOps = 2;
1899 let ResourceCycles = [1, 1];
1901 def : InstRW<[WriteMULm], (instregex "(V?)MUL(P|S)(S|D)rm")>;
1905 def WriteVDIVPSYrr : SchedWriteRes<[HWPort0, HWPort15]> {
1906 let Latency = 19; // 18-21 cycles.
1907 let NumMicroOps = 3;
1908 let ResourceCycles = [2, 1];
1910 def : InstRW<[WriteVDIVPSYrr], (instregex "VDIVPSYrr")>;
1913 def WriteVDIVPSYrm : SchedWriteRes<[HWPort0, HWPort15, HWPort23]> {
1914 let Latency = 23; // 18-21 + 4 cycles.
1915 let NumMicroOps = 4;
1916 let ResourceCycles = [2, 1, 1];
1918 def : InstRW<[WriteVDIVPSYrm, ReadAfterLd], (instregex "VDIVPSYrm")>;
1922 def WriteVDIVPDYrr : SchedWriteRes<[HWPort0, HWPort15]> {
1923 let Latency = 27; // 19-35 cycles.
1924 let NumMicroOps = 3;
1925 let ResourceCycles = [2, 1];
1927 def : InstRW<[WriteVDIVPDYrr], (instregex "VDIVPDYrr")>;
1930 def WriteVDIVPDYrm : SchedWriteRes<[HWPort0, HWPort15, HWPort23]> {
1931 let Latency = 31; // 19-35 + 4 cycles.
1932 let NumMicroOps = 4;
1933 let ResourceCycles = [2, 1, 1];
1935 def : InstRW<[WriteVDIVPDYrm, ReadAfterLd], (instregex "VDIVPDYrm")>;
1939 def WriteVRCPPSr : SchedWriteRes<[HWPort0, HWPort15]> {
1941 let NumMicroOps = 3;
1942 let ResourceCycles = [2, 1];
1944 def : InstRW<[WriteVRCPPSr], (instregex "VRCPPSYr(_Int)?")>;
1947 def WriteVRCPPSm : SchedWriteRes<[HWPort0, HWPort15, HWPort23]> {
1949 let NumMicroOps = 4;
1950 let ResourceCycles = [2, 1, 1];
1952 def : InstRW<[WriteVRCPPSm], (instregex "VRCPPSYm(_Int)?")>;
1954 // ROUND SS/SD PS/PD.
1956 def WriteROUNDr : SchedWriteRes<[HWPort1]> {
1958 let NumMicroOps = 2;
1959 let ResourceCycles = [2];
1961 def : InstRW<[WriteROUNDr], (instregex "(V?)ROUND(Y?)(S|P)(S|D)r(_Int)?")>;
1964 def WriteROUNDm : SchedWriteRes<[HWPort1, HWPort23]> {
1966 let NumMicroOps = 3;
1967 let ResourceCycles = [2, 1];
1969 def : InstRW<[WriteROUNDm], (instregex "(V?)ROUND(Y?)(S|P)(S|D)m(_Int)?")>;
1973 def WriteDPPSr : SchedWriteRes<[HWPort0, HWPort1, HWPort5]> {
1975 let NumMicroOps = 4;
1976 let ResourceCycles = [2, 1, 1];
1978 def : InstRW<[WriteDPPSr], (instregex "(V?)DPPS(Y?)rri")>;
1981 def WriteDPPSm : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort23, HWPort6]> {
1983 let NumMicroOps = 6;
1984 let ResourceCycles = [2, 1, 1, 1, 1];
1986 def : InstRW<[WriteDPPSm, ReadAfterLd], (instregex "(V?)DPPS(Y?)rmi")>;
1990 def WriteDPPDr : SchedWriteRes<[HWPort0, HWPort1, HWPort5]> {
1992 let NumMicroOps = 3;
1993 let ResourceCycles = [1, 1, 1];
1995 def : InstRW<[WriteDPPDr], (instregex "(V?)DPPDrri")>;
1998 def WriteDPPDm : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort23]> {
2000 let NumMicroOps = 4;
2001 let ResourceCycles = [1, 1, 1, 1];
2003 def : InstRW<[WriteDPPDm], (instregex "(V?)DPPDrmi")>;
2007 def WriteFMADDr : SchedWriteRes<[HWPort01]> {
2009 let NumMicroOps = 1;
2011 def : InstRW<[WriteFMADDr],
2014 "VF(N?)M(ADD|SUB|ADDSUB|SUBADD)P(S|D)(r213|r132|r231)r(Y)?",
2016 "VF(N?)M(ADD|SUB)S(S|D)(r132|231|213)r",
2018 "VF(N?)M(ADD|SUB)S(S|D)4rr(_REV|_Int)?",
2020 "VF(N?)M(ADD|SUB)P(S|D)4rr(Y)?(_REV)?")>;
2023 def WriteFMADDm : SchedWriteRes<[HWPort01, HWPort23]> {
2025 let NumMicroOps = 2;
2026 let ResourceCycles = [1, 1];
2028 def : InstRW<[WriteFMADDm],
2031 "VF(N?)M(ADD|SUB|ADDSUB|SUBADD)P(S|D)(r213|r132|r231)m(Y)?",
2033 "VF(N?)M(ADD|SUB)S(S|D)(r132|231|213)m",
2035 "VF(N?)M(ADD|SUB)S(S|D)4(rm|mr)(_Int)?",
2037 "VF(N?)M(ADD|SUB)P(S|D)4(rm|mr)(Y)?")>;
2039 //-- Math instructions --//
2043 def WriteVSQRTPSYr : SchedWriteRes<[HWPort0, HWPort15]> {
2045 let NumMicroOps = 3;
2046 let ResourceCycles = [2, 1];
2048 def : InstRW<[WriteVSQRTPSYr], (instregex "VSQRTPSYr")>;
2051 def WriteVSQRTPSYm : SchedWriteRes<[HWPort0, HWPort15, HWPort23]> {
2053 let NumMicroOps = 4;
2054 let ResourceCycles = [2, 1, 1];
2056 def : InstRW<[WriteVSQRTPSYm], (instregex "VSQRTPSYm")>;
2060 def WriteVSQRTPDYr : SchedWriteRes<[HWPort0, HWPort15]> {
2062 let NumMicroOps = 3;
2063 let ResourceCycles = [2, 1];
2065 def : InstRW<[WriteVSQRTPDYr], (instregex "VSQRTPDYr")>;
2068 def WriteVSQRTPDYm : SchedWriteRes<[HWPort0, HWPort15, HWPort23]> {
2070 let NumMicroOps = 4;
2071 let ResourceCycles = [2, 1, 1];
2073 def : InstRW<[WriteVSQRTPDYm], (instregex "VSQRTPDYm")>;
2077 def WriteRSQRTr : SchedWriteRes<[HWPort0]> {
2080 def : InstRW<[WriteRSQRTr], (instregex "(V?)RSQRT(SS|PS)r(_Int)?")>;
2083 def WriteRSQRTm : SchedWriteRes<[HWPort0, HWPort23]> {
2085 let NumMicroOps = 2;
2086 let ResourceCycles = [1, 1];
2088 def : InstRW<[WriteRSQRTm], (instregex "(V?)RSQRT(SS|PS)m(_Int)?")>;
2092 def WriteRSQRTPSYr : SchedWriteRes<[HWPort0, HWPort15]> {
2094 let NumMicroOps = 3;
2095 let ResourceCycles = [2, 1];
2097 def : InstRW<[WriteRSQRTPSYr], (instregex "VRSQRTPSYr(_Int)?")>;
2100 def WriteRSQRTPSYm : SchedWriteRes<[HWPort0, HWPort15, HWPort23]> {
2102 let NumMicroOps = 4;
2103 let ResourceCycles = [2, 1, 1];
2105 def : InstRW<[WriteRSQRTPSYm], (instregex "VRSQRTPSYm(_Int)?")>;
2107 //-- Logic instructions --//
2109 // AND, ANDN, OR, XOR PS/PD.
2111 def : InstRW<[WriteP5], (instregex "(V?)(AND|ANDN|OR|XOR)P(S|D)(Y?)rr")>;
2113 def : InstRW<[WriteP5Ld, ReadAfterLd],
2114 (instregex "(V?)(AND|ANDN|OR|XOR)P(S|D)(Y?)rm")>;
2116 //-- Other instructions --//
2119 def WriteVZEROUPPER : SchedWriteRes<[]> {
2120 let NumMicroOps = 4;
2122 def : InstRW<[WriteVZEROUPPER], (instregex "VZEROUPPER")>;
2125 def WriteVZEROALL : SchedWriteRes<[]> {
2126 let NumMicroOps = 12;
2128 def : InstRW<[WriteVZEROALL], (instregex "VZEROALL")>;
2131 def WriteLDMXCSR : SchedWriteRes<[HWPort0, HWPort6, HWPort23]> {
2133 let NumMicroOps = 3;
2134 let ResourceCycles = [1, 1, 1];
2136 def : InstRW<[WriteLDMXCSR], (instregex "(V)?LDMXCSR")>;
2139 def WriteSTMXCSR : SchedWriteRes<[HWPort0, HWPort4, HWPort6, HWPort237]> {
2141 let NumMicroOps = 4;
2142 let ResourceCycles = [1, 1, 1, 1];
2144 def : InstRW<[WriteSTMXCSR], (instregex "(V)?STMXCSR")>;