1 //=- X86SchedHaswell.td - X86 Haswell Scheduling -------------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the machine model for Haswell to support instruction
11 // scheduling and other instruction cost heuristics.
13 //===----------------------------------------------------------------------===//
15 def HaswellModel : SchedMachineModel {
16 // All x86 instructions are modeled as a single micro-op, and HW can decode 4
17 // instructions per cycle.
19 let MinLatency = 0; // 0 = Out-of-order execution.
22 let MispredictPenalty = 16;
25 let SchedModel = HaswellModel in {
27 // Haswell can issue micro-ops to 8 different ports in one cycle.
29 // Ports 0, 1, 5, 6 and 7 handle all computation.
30 // Port 4 gets the data half of stores. Store data can be available later than
31 // the store address, but since we don't model the latency of stores, we can
33 // Ports 2 and 3 are identical. They handle loads and the address half of
34 // stores. Port 7 can handle address calculations.
35 def HWPort0 : ProcResource<1>;
36 def HWPort1 : ProcResource<1>;
37 def HWPort2 : ProcResource<1>;
38 def HWPort3 : ProcResource<1>;
39 def HWPort4 : ProcResource<1>;
40 def HWPort5 : ProcResource<1>;
41 def HWPort6 : ProcResource<1>;
42 def HWPort7 : ProcResource<1>;
44 // Many micro-ops are capable of issuing on multiple ports.
45 def HWPort23 : ProcResGroup<[HWPort2, HWPort3]>;
46 def HWPort237 : ProcResGroup<[HWPort2, HWPort3, HWPort7]>;
47 def HWPort05 : ProcResGroup<[HWPort0, HWPort5]>;
48 def HWPort056 : ProcResGroup<[HWPort0, HWPort5, HWPort6]>;
49 def HWPort15 : ProcResGroup<[HWPort1, HWPort5]>;
50 def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>;
51 def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>;
53 // Integer division issued on port 0.
54 def HWDivider : ProcResource<1>;
56 // Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4
57 // cycles after the memory operand.
58 def : ReadAdvance<ReadAfterLd, 4>;
60 // Many SchedWrites are defined in pairs with and without a folded load.
61 // Instructions with folded loads are usually micro-fused, so they only appear
62 // as two micro-ops when queued in the reservation station.
63 // This multiclass defines the resource usage for variants with and without
65 multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW,
66 ProcResourceKind ExePort,
68 // Register variant is using a single cycle on ExePort.
69 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
71 // Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the
73 def : WriteRes<SchedRW.Folded, [HWPort23, ExePort]> {
74 let Latency = !add(Lat, 4);
78 // A folded store needs a cycle on port 4 for the store data, but it does not
79 // need an extra port 2/3 cycle to recompute the address.
80 def : WriteRes<WriteRMW, [HWPort4]>;
82 def : WriteRes<WriteStore, [HWPort237, HWPort4]>;
83 def : WriteRes<WriteLoad, [HWPort23]> { let Latency = 4; }
84 def : WriteRes<WriteMove, [HWPort0156]>;
85 def : WriteRes<WriteZero, []>;
87 defm : HWWriteResPair<WriteALU, HWPort0156, 1>;
88 defm : HWWriteResPair<WriteIMul, HWPort1, 3>;
89 defm : HWWriteResPair<WriteShift, HWPort056, 1>;
90 defm : HWWriteResPair<WriteJump, HWPort5, 1>;
92 // This is for simple LEAs with one or two input operands.
93 // The complex ones can only execute on port 1, and they require two cycles on
94 // the port to read all inputs. We don't model that.
95 def : WriteRes<WriteLEA, [HWPort15]>;
97 // This is quite rough, latency depends on the dividend.
98 def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> {
100 let ResourceCycles = [1, 10];
102 def : WriteRes<WriteIDivLd, [HWPort23, HWPort0, HWDivider]> {
104 let ResourceCycles = [1, 1, 10];
107 // Scalar and vector floating point.
108 defm : HWWriteResPair<WriteFAdd, HWPort1, 3>;
109 defm : HWWriteResPair<WriteFMul, HWPort0, 5>;
110 defm : HWWriteResPair<WriteFDiv, HWPort0, 12>; // 10-14 cycles.
111 defm : HWWriteResPair<WriteFRcp, HWPort0, 5>;
112 defm : HWWriteResPair<WriteFSqrt, HWPort0, 15>;
113 defm : HWWriteResPair<WriteCvtF2I, HWPort1, 3>;
114 defm : HWWriteResPair<WriteCvtI2F, HWPort1, 4>;
115 defm : HWWriteResPair<WriteCvtF2F, HWPort1, 3>;
117 // Vector integer operations.
118 defm : HWWriteResPair<WriteVecShift, HWPort05, 1>;
119 defm : HWWriteResPair<WriteVecLogic, HWPort015, 1>;
120 defm : HWWriteResPair<WriteVecALU, HWPort15, 1>;
121 defm : HWWriteResPair<WriteVecIMul, HWPort0, 5>;
122 defm : HWWriteResPair<WriteShuffle, HWPort15, 1>;
124 def : WriteRes<WriteSystem, [HWPort0156]> { let Latency = 100; }
125 def : WriteRes<WriteMicrocoded, [HWPort0156]> { let Latency = 100; }