1 //=- X86SchedHaswell.td - X86 Haswell Scheduling -------------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the machine model for Haswell to support instruction
11 // scheduling and other instruction cost heuristics.
13 //===----------------------------------------------------------------------===//
15 def HaswellModel : SchedMachineModel {
16 // All x86 instructions are modeled as a single micro-op, and HW can decode 4
17 // instructions per cycle.
19 let MicroOpBufferSize = 192; // Based on the reorder buffer.
21 let MispredictPenalty = 16;
23 // FIXME: SSE4 and AVX are unimplemented. This flag is set to allow
24 // the scheduler to assign a default model to unrecognized opcodes.
25 let CompleteModel = 0;
28 let SchedModel = HaswellModel in {
30 // Haswell can issue micro-ops to 8 different ports in one cycle.
32 // Ports 0, 1, 5, and 6 handle all computation.
33 // Port 4 gets the data half of stores. Store data can be available later than
34 // the store address, but since we don't model the latency of stores, we can
36 // Ports 2 and 3 are identical. They handle loads and the address half of
37 // stores. Port 7 can handle address calculations.
38 def HWPort0 : ProcResource<1>;
39 def HWPort1 : ProcResource<1>;
40 def HWPort2 : ProcResource<1>;
41 def HWPort3 : ProcResource<1>;
42 def HWPort4 : ProcResource<1>;
43 def HWPort5 : ProcResource<1>;
44 def HWPort6 : ProcResource<1>;
45 def HWPort7 : ProcResource<1>;
47 // Many micro-ops are capable of issuing on multiple ports.
48 def HWPort23 : ProcResGroup<[HWPort2, HWPort3]>;
49 def HWPort237 : ProcResGroup<[HWPort2, HWPort3, HWPort7]>;
50 def HWPort05 : ProcResGroup<[HWPort0, HWPort5]>;
51 def HWPort06 : ProcResGroup<[HWPort0, HWPort6]>;
52 def HWPort15 : ProcResGroup<[HWPort1, HWPort5]>;
53 def HWPort16 : ProcResGroup<[HWPort1, HWPort6]>;
54 def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>;
55 def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>;
57 // 60 Entry Unified Scheduler
58 def HWPortAny : ProcResGroup<[HWPort0, HWPort1, HWPort2, HWPort3, HWPort4,
59 HWPort5, HWPort6, HWPort7]> {
63 // Integer division issued on port 0.
64 def HWDivider : ProcResource<1>;
66 // Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4
67 // cycles after the memory operand.
68 def : ReadAdvance<ReadAfterLd, 4>;
70 // Many SchedWrites are defined in pairs with and without a folded load.
71 // Instructions with folded loads are usually micro-fused, so they only appear
72 // as two micro-ops when queued in the reservation station.
73 // This multiclass defines the resource usage for variants with and without
75 multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW,
76 ProcResourceKind ExePort,
78 // Register variant is using a single cycle on ExePort.
79 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
81 // Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the
83 def : WriteRes<SchedRW.Folded, [HWPort23, ExePort]> {
84 let Latency = !add(Lat, 4);
88 // A folded store needs a cycle on port 4 for the store data, but it does not
89 // need an extra port 2/3 cycle to recompute the address.
90 def : WriteRes<WriteRMW, [HWPort4]>;
94 def : WriteRes<WriteStore, [HWPort237, HWPort4]>;
95 def : WriteRes<WriteLoad, [HWPort23]> { let Latency = 4; }
96 def : WriteRes<WriteMove, [HWPort0156]>;
97 def : WriteRes<WriteZero, []>;
99 defm : HWWriteResPair<WriteALU, HWPort0156, 1>;
100 defm : HWWriteResPair<WriteIMul, HWPort1, 3>;
101 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
102 defm : HWWriteResPair<WriteShift, HWPort06, 1>;
103 defm : HWWriteResPair<WriteJump, HWPort06, 1>;
105 // This is for simple LEAs with one or two input operands.
106 // The complex ones can only execute on port 1, and they require two cycles on
107 // the port to read all inputs. We don't model that.
108 def : WriteRes<WriteLEA, [HWPort15]>;
110 // This is quite rough, latency depends on the dividend.
111 def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> {
113 let ResourceCycles = [1, 10];
115 def : WriteRes<WriteIDivLd, [HWPort23, HWPort0, HWDivider]> {
117 let ResourceCycles = [1, 1, 10];
120 // Scalar and vector floating point.
121 defm : HWWriteResPair<WriteFAdd, HWPort1, 3>;
122 defm : HWWriteResPair<WriteFMul, HWPort0, 5>;
123 defm : HWWriteResPair<WriteFDiv, HWPort0, 12>; // 10-14 cycles.
124 defm : HWWriteResPair<WriteFRcp, HWPort0, 5>;
125 defm : HWWriteResPair<WriteFSqrt, HWPort0, 15>;
126 defm : HWWriteResPair<WriteCvtF2I, HWPort1, 3>;
127 defm : HWWriteResPair<WriteCvtI2F, HWPort1, 4>;
128 defm : HWWriteResPair<WriteCvtF2F, HWPort1, 3>;
129 defm : HWWriteResPair<WriteFShuffle, HWPort5, 1>;
130 defm : HWWriteResPair<WriteFBlend, HWPort015, 1>;
131 defm : HWWriteResPair<WriteFShuffle256, HWPort5, 3>;
133 def : WriteRes<WriteFVarBlend, [HWPort5]> {
135 let ResourceCycles = [2];
137 def : WriteRes<WriteFVarBlendLd, [HWPort5, HWPort23]> {
139 let ResourceCycles = [2, 1];
142 // Vector integer operations.
143 defm : HWWriteResPair<WriteVecShift, HWPort0, 1>;
144 defm : HWWriteResPair<WriteVecLogic, HWPort015, 1>;
145 defm : HWWriteResPair<WriteVecALU, HWPort15, 1>;
146 defm : HWWriteResPair<WriteVecIMul, HWPort0, 5>;
147 defm : HWWriteResPair<WriteShuffle, HWPort5, 1>;
148 defm : HWWriteResPair<WriteBlend, HWPort15, 1>;
149 defm : HWWriteResPair<WriteShuffle256, HWPort5, 3>;
151 def : WriteRes<WriteVarBlend, [HWPort5]> {
153 let ResourceCycles = [2];
155 def : WriteRes<WriteVarBlendLd, [HWPort5, HWPort23]> {
157 let ResourceCycles = [2, 1];
160 def : WriteRes<WriteVarVecShift, [HWPort0, HWPort5]> {
162 let ResourceCycles = [2, 1];
164 def : WriteRes<WriteVarVecShiftLd, [HWPort0, HWPort5, HWPort23]> {
166 let ResourceCycles = [2, 1, 1];
169 def : WriteRes<WriteMPSAD, [HWPort0, HWPort5]> {
171 let ResourceCycles = [1, 2];
173 def : WriteRes<WriteMPSADLd, [HWPort23, HWPort0, HWPort5]> {
175 let ResourceCycles = [1, 1, 2];
178 // String instructions.
179 // Packed Compare Implicit Length Strings, Return Mask
180 def : WriteRes<WritePCmpIStrM, [HWPort0]> {
182 let ResourceCycles = [3];
184 def : WriteRes<WritePCmpIStrMLd, [HWPort0, HWPort23]> {
186 let ResourceCycles = [3, 1];
189 // Packed Compare Explicit Length Strings, Return Mask
190 def : WriteRes<WritePCmpEStrM, [HWPort0, HWPort16, HWPort5]> {
192 let ResourceCycles = [3, 2, 4];
194 def : WriteRes<WritePCmpEStrMLd, [HWPort05, HWPort16, HWPort23]> {
196 let ResourceCycles = [6, 2, 1];
199 // Packed Compare Implicit Length Strings, Return Index
200 def : WriteRes<WritePCmpIStrI, [HWPort0]> {
202 let ResourceCycles = [3];
204 def : WriteRes<WritePCmpIStrILd, [HWPort0, HWPort23]> {
206 let ResourceCycles = [3, 1];
209 // Packed Compare Explicit Length Strings, Return Index
210 def : WriteRes<WritePCmpEStrI, [HWPort05, HWPort16]> {
212 let ResourceCycles = [6, 2];
214 def : WriteRes<WritePCmpEStrILd, [HWPort0, HWPort16, HWPort5, HWPort23]> {
216 let ResourceCycles = [3, 2, 2, 1];
220 def : WriteRes<WriteAESDecEnc, [HWPort5]> {
222 let ResourceCycles = [1];
224 def : WriteRes<WriteAESDecEncLd, [HWPort5, HWPort23]> {
226 let ResourceCycles = [1, 1];
229 def : WriteRes<WriteAESIMC, [HWPort5]> {
231 let ResourceCycles = [2];
233 def : WriteRes<WriteAESIMCLd, [HWPort5, HWPort23]> {
235 let ResourceCycles = [2, 1];
238 def : WriteRes<WriteAESKeyGen, [HWPort0, HWPort5]> {
240 let ResourceCycles = [2, 8];
242 def : WriteRes<WriteAESKeyGenLd, [HWPort0, HWPort5, HWPort23]> {
244 let ResourceCycles = [2, 7, 1];
247 // Carry-less multiplication instructions.
248 def : WriteRes<WriteCLMul, [HWPort0, HWPort5]> {
250 let ResourceCycles = [2, 1];
252 def : WriteRes<WriteCLMulLd, [HWPort0, HWPort5, HWPort23]> {
254 let ResourceCycles = [2, 1, 1];
257 def : WriteRes<WriteSystem, [HWPort0156]> { let Latency = 100; }
258 def : WriteRes<WriteMicrocoded, [HWPort0156]> { let Latency = 100; }
259 def : WriteRes<WriteFence, [HWPort23, HWPort4]>;
260 def : WriteRes<WriteNop, []>;