1 //=- X86SchedHaswell.td - X86 Haswell Scheduling -------------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the machine model for Haswell to support instruction
11 // scheduling and other instruction cost heuristics.
13 //===----------------------------------------------------------------------===//
15 def HaswellModel : SchedMachineModel {
16 // All x86 instructions are modeled as a single micro-op, and HW can decode 4
17 // instructions per cycle.
19 let MicroOpBufferSize = 192; // Based on the reorder buffer.
21 let MispredictPenalty = 16;
23 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
24 let LoopMicroOpBufferSize = 50;
26 // FIXME: SSE4 and AVX are unimplemented. This flag is set to allow
27 // the scheduler to assign a default model to unrecognized opcodes.
28 let CompleteModel = 0;
31 let SchedModel = HaswellModel in {
33 // Haswell can issue micro-ops to 8 different ports in one cycle.
35 // Ports 0, 1, 5, and 6 handle all computation.
36 // Port 4 gets the data half of stores. Store data can be available later than
37 // the store address, but since we don't model the latency of stores, we can
39 // Ports 2 and 3 are identical. They handle loads and the address half of
40 // stores. Port 7 can handle address calculations.
41 def HWPort0 : ProcResource<1>;
42 def HWPort1 : ProcResource<1>;
43 def HWPort2 : ProcResource<1>;
44 def HWPort3 : ProcResource<1>;
45 def HWPort4 : ProcResource<1>;
46 def HWPort5 : ProcResource<1>;
47 def HWPort6 : ProcResource<1>;
48 def HWPort7 : ProcResource<1>;
50 // Many micro-ops are capable of issuing on multiple ports.
51 def HWPort01 : ProcResGroup<[HWPort0, HWPort1]>;
52 def HWPort23 : ProcResGroup<[HWPort2, HWPort3]>;
53 def HWPort237 : ProcResGroup<[HWPort2, HWPort3, HWPort7]>;
54 def HWPort04 : ProcResGroup<[HWPort0, HWPort4]>;
55 def HWPort05 : ProcResGroup<[HWPort0, HWPort5]>;
56 def HWPort06 : ProcResGroup<[HWPort0, HWPort6]>;
57 def HWPort15 : ProcResGroup<[HWPort1, HWPort5]>;
58 def HWPort16 : ProcResGroup<[HWPort1, HWPort6]>;
59 def HWPort56: ProcResGroup<[HWPort5, HWPort6]>;
60 def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>;
61 def HWPort056: ProcResGroup<[HWPort0, HWPort5, HWPort6]>;
62 def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>;
64 // 60 Entry Unified Scheduler
65 def HWPortAny : ProcResGroup<[HWPort0, HWPort1, HWPort2, HWPort3, HWPort4,
66 HWPort5, HWPort6, HWPort7]> {
70 // Integer division issued on port 0.
71 def HWDivider : ProcResource<1>;
73 // Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4
74 // cycles after the memory operand.
75 def : ReadAdvance<ReadAfterLd, 4>;
77 // Many SchedWrites are defined in pairs with and without a folded load.
78 // Instructions with folded loads are usually micro-fused, so they only appear
79 // as two micro-ops when queued in the reservation station.
80 // This multiclass defines the resource usage for variants with and without
82 multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW,
83 ProcResourceKind ExePort,
85 // Register variant is using a single cycle on ExePort.
86 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
88 // Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the
90 def : WriteRes<SchedRW.Folded, [HWPort23, ExePort]> {
91 let Latency = !add(Lat, 4);
95 // A folded store needs a cycle on port 4 for the store data, but it does not
96 // need an extra port 2/3 cycle to recompute the address.
97 def : WriteRes<WriteRMW, [HWPort4]>;
101 def : WriteRes<WriteStore, [HWPort237, HWPort4]>;
102 def : WriteRes<WriteLoad, [HWPort23]> { let Latency = 4; }
103 def : WriteRes<WriteMove, [HWPort0156]>;
104 def : WriteRes<WriteZero, []>;
106 defm : HWWriteResPair<WriteALU, HWPort0156, 1>;
107 defm : HWWriteResPair<WriteIMul, HWPort1, 3>;
108 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
109 defm : HWWriteResPair<WriteShift, HWPort06, 1>;
110 defm : HWWriteResPair<WriteJump, HWPort06, 1>;
112 // This is for simple LEAs with one or two input operands.
113 // The complex ones can only execute on port 1, and they require two cycles on
114 // the port to read all inputs. We don't model that.
115 def : WriteRes<WriteLEA, [HWPort15]>;
117 // This is quite rough, latency depends on the dividend.
118 def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> {
120 let ResourceCycles = [1, 10];
122 def : WriteRes<WriteIDivLd, [HWPort23, HWPort0, HWDivider]> {
124 let ResourceCycles = [1, 1, 10];
127 // Scalar and vector floating point.
128 defm : HWWriteResPair<WriteFAdd, HWPort1, 3>;
129 defm : HWWriteResPair<WriteFMul, HWPort0, 5>;
130 defm : HWWriteResPair<WriteFDiv, HWPort0, 12>; // 10-14 cycles.
131 defm : HWWriteResPair<WriteFRcp, HWPort0, 5>;
132 defm : HWWriteResPair<WriteFSqrt, HWPort0, 15>;
133 defm : HWWriteResPair<WriteCvtF2I, HWPort1, 3>;
134 defm : HWWriteResPair<WriteCvtI2F, HWPort1, 4>;
135 defm : HWWriteResPair<WriteCvtF2F, HWPort1, 3>;
136 defm : HWWriteResPair<WriteFShuffle, HWPort5, 1>;
137 defm : HWWriteResPair<WriteFBlend, HWPort015, 1>;
138 defm : HWWriteResPair<WriteFShuffle256, HWPort5, 3>;
140 def : WriteRes<WriteFVarBlend, [HWPort5]> {
142 let ResourceCycles = [2];
144 def : WriteRes<WriteFVarBlendLd, [HWPort5, HWPort23]> {
146 let ResourceCycles = [2, 1];
149 // Vector integer operations.
150 defm : HWWriteResPair<WriteVecShift, HWPort0, 1>;
151 defm : HWWriteResPair<WriteVecLogic, HWPort015, 1>;
152 defm : HWWriteResPair<WriteVecALU, HWPort15, 1>;
153 defm : HWWriteResPair<WriteVecIMul, HWPort0, 5>;
154 defm : HWWriteResPair<WriteShuffle, HWPort5, 1>;
155 defm : HWWriteResPair<WriteBlend, HWPort15, 1>;
156 defm : HWWriteResPair<WriteShuffle256, HWPort5, 3>;
158 def : WriteRes<WriteVarBlend, [HWPort5]> {
160 let ResourceCycles = [2];
162 def : WriteRes<WriteVarBlendLd, [HWPort5, HWPort23]> {
164 let ResourceCycles = [2, 1];
167 def : WriteRes<WriteVarVecShift, [HWPort0, HWPort5]> {
169 let ResourceCycles = [2, 1];
171 def : WriteRes<WriteVarVecShiftLd, [HWPort0, HWPort5, HWPort23]> {
173 let ResourceCycles = [2, 1, 1];
176 def : WriteRes<WriteMPSAD, [HWPort0, HWPort5]> {
178 let ResourceCycles = [1, 2];
180 def : WriteRes<WriteMPSADLd, [HWPort23, HWPort0, HWPort5]> {
182 let ResourceCycles = [1, 1, 2];
185 // String instructions.
186 // Packed Compare Implicit Length Strings, Return Mask
187 def : WriteRes<WritePCmpIStrM, [HWPort0]> {
189 let ResourceCycles = [3];
191 def : WriteRes<WritePCmpIStrMLd, [HWPort0, HWPort23]> {
193 let ResourceCycles = [3, 1];
196 // Packed Compare Explicit Length Strings, Return Mask
197 def : WriteRes<WritePCmpEStrM, [HWPort0, HWPort16, HWPort5]> {
199 let ResourceCycles = [3, 2, 4];
201 def : WriteRes<WritePCmpEStrMLd, [HWPort05, HWPort16, HWPort23]> {
203 let ResourceCycles = [6, 2, 1];
206 // Packed Compare Implicit Length Strings, Return Index
207 def : WriteRes<WritePCmpIStrI, [HWPort0]> {
209 let ResourceCycles = [3];
211 def : WriteRes<WritePCmpIStrILd, [HWPort0, HWPort23]> {
213 let ResourceCycles = [3, 1];
216 // Packed Compare Explicit Length Strings, Return Index
217 def : WriteRes<WritePCmpEStrI, [HWPort05, HWPort16]> {
219 let ResourceCycles = [6, 2];
221 def : WriteRes<WritePCmpEStrILd, [HWPort0, HWPort16, HWPort5, HWPort23]> {
223 let ResourceCycles = [3, 2, 2, 1];
227 def : WriteRes<WriteAESDecEnc, [HWPort5]> {
229 let ResourceCycles = [1];
231 def : WriteRes<WriteAESDecEncLd, [HWPort5, HWPort23]> {
233 let ResourceCycles = [1, 1];
236 def : WriteRes<WriteAESIMC, [HWPort5]> {
238 let ResourceCycles = [2];
240 def : WriteRes<WriteAESIMCLd, [HWPort5, HWPort23]> {
242 let ResourceCycles = [2, 1];
245 def : WriteRes<WriteAESKeyGen, [HWPort0, HWPort5]> {
247 let ResourceCycles = [2, 8];
249 def : WriteRes<WriteAESKeyGenLd, [HWPort0, HWPort5, HWPort23]> {
251 let ResourceCycles = [2, 7, 1];
254 // Carry-less multiplication instructions.
255 def : WriteRes<WriteCLMul, [HWPort0, HWPort5]> {
257 let ResourceCycles = [2, 1];
259 def : WriteRes<WriteCLMulLd, [HWPort0, HWPort5, HWPort23]> {
261 let ResourceCycles = [2, 1, 1];
264 def : WriteRes<WriteSystem, [HWPort0156]> { let Latency = 100; }
265 def : WriteRes<WriteMicrocoded, [HWPort0156]> { let Latency = 100; }
266 def : WriteRes<WriteFence, [HWPort23, HWPort4]>;
267 def : WriteRes<WriteNop, []>;
269 //================ Exceptions ================//
271 //-- Specific Scheduling Models --//
272 def WriteP0 : SchedWriteRes<[HWPort0]>;
273 def WriteP1 : SchedWriteRes<[HWPort1]>;
274 def WriteP1_P23 : SchedWriteRes<[HWPort1, HWPort23]> {
277 def WriteP1_Lat3 : SchedWriteRes<[HWPort1]> {
280 def WriteP1_Lat3Ld : SchedWriteRes<[HWPort1, HWPort23]> {
284 def Write2P0156_Lat2 : SchedWriteRes<[HWPort0156]> {
286 let ResourceCycles = [2];
288 def Write2P0156_Lat2Ld : SchedWriteRes<[HWPort0156, HWPort23]> {
290 let ResourceCycles = [2, 1];
293 def Write5P0156 : SchedWriteRes<[HWPort0156]> {
295 let ResourceCycles = [5];
298 def Write2P237_P4 : SchedWriteRes<[HWPort237, HWPort4]> {
300 let ResourceCycles = [2, 1];
303 def WriteP01 : SchedWriteRes<[HWPort01]>;
305 def Write2P01 : SchedWriteRes<[HWPort01]> {
308 def Write3P01 : SchedWriteRes<[HWPort01]> {
312 def WriteP015 : SchedWriteRes<[HWPort015]>;
314 def WriteP01_P5 : SchedWriteRes<[HWPort01, HWPort5]> {
317 def WriteP06 : SchedWriteRes<[HWPort06]>;
319 def Write2P06 : SchedWriteRes<[HWPort06]> {
322 let ResourceCycles = [2];
325 def Write2P1 : SchedWriteRes<[HWPort1]> {
327 let ResourceCycles = [2];
329 def Write2P1_P23 : SchedWriteRes<[HWPort1, HWPort23]> {
331 let ResourceCycles = [2, 1];
333 def WriteP15 : SchedWriteRes<[HWPort15]>;
334 def WriteP15Ld : SchedWriteRes<[HWPort15, HWPort23]> {
338 def Write3P06_Lat2 : SchedWriteRes<[HWPort06]> {
341 let ResourceCycles = [3];
344 def WriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
348 def WriteP0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
350 let ResourceCycles = [1, 2, 1];
353 def Write2P0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
355 let ResourceCycles = [2, 2, 1];
358 def Write2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
360 let ResourceCycles = [2, 1];
363 def Write3P0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
365 let ResourceCycles = [3, 2, 1];
368 def WriteP5 : SchedWriteRes<[HWPort5]>;
369 def WriteP5Ld : SchedWriteRes<[HWPort5, HWPort23]> {
372 let ResourceCycles = [1, 1];
377 // - mm: 64 bit mmx register.
378 // - x = 128 bit xmm register.
379 // - (x)mm = mmx or xmm register.
380 // - y = 256 bit ymm register.
381 // - v = any vector register.
384 //=== Integer Instructions ===//
385 //-- Move instructions --//
389 def : InstRW<[WriteALULd], (instregex "MOV16rm")>;
393 def : InstRW<[WriteLoad], (instregex "MOV(S|Z)X32rm(8|16)")>;
397 def : InstRW<[Write2P0156_Lat2],
398 (instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rr")>;
400 def : InstRW<[Write2P0156_Lat2Ld, ReadAfterLd],
401 (instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rm")>;
405 def WriteXCHG : SchedWriteRes<[HWPort0156]> {
407 let ResourceCycles = [3];
410 def : InstRW<[WriteXCHG], (instregex "XCHG(8|16|32|64)rr", "XCHG(16|32|64)ar")>;
413 def WriteXCHGrm : SchedWriteRes<[]> {
417 def : InstRW<[WriteXCHGrm], (instregex "XCHG(8|16|32|64)rm")>;
420 def WriteXLAT : SchedWriteRes<[]> {
424 def : InstRW<[WriteXLAT], (instregex "XLAT")>;
428 def : InstRW<[Write2P237_P4], (instregex "PUSH(16|32)rmm")>;
431 def WritePushF : SchedWriteRes<[HWPort1, HWPort4, HWPort237, HWPort06]> {
434 def : InstRW<[WritePushF], (instregex "PUSHF(16|32)")>;
437 def WritePushA : SchedWriteRes<[]> {
438 let NumMicroOps = 19;
440 def : InstRW<[WritePushA], (instregex "PUSHA(16|32)")>;
444 def : InstRW<[Write2P237_P4], (instregex "POP(16|32)rmm")>;
447 def WritePopF : SchedWriteRes<[]> {
450 def : InstRW<[WritePopF], (instregex "POPF(16|32)")>;
453 def WritePopA : SchedWriteRes<[]> {
454 let NumMicroOps = 18;
456 def : InstRW<[WritePopA], (instregex "POPA(16|32)")>;
459 def : InstRW<[WriteP06], (instregex "(S|L)AHF")>;
463 def WriteBSwap32 : SchedWriteRes<[HWPort15]>;
464 def : InstRW<[WriteBSwap32], (instregex "BSWAP32r")>;
467 def WriteBSwap64 : SchedWriteRes<[HWPort06, HWPort15]> {
470 def : InstRW<[WriteBSwap64], (instregex "BSWAP64r")>;
473 // r16,m16 / r64,m64.
474 def : InstRW<[Write2P0156_Lat2Ld], (instregex "MOVBE(16|64)rm")>;
477 def WriteMoveBE32rm : SchedWriteRes<[HWPort15, HWPort23]> {
480 def : InstRW<[WriteMoveBE32rm], (instregex "MOVBE32rm")>;
483 def WriteMoveBE16mr : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
486 def : InstRW<[WriteMoveBE16mr], (instregex "MOVBE16mr")>;
489 def WriteMoveBE32mr : SchedWriteRes<[HWPort15, HWPort237, HWPort4]> {
492 def : InstRW<[WriteMoveBE32mr], (instregex "MOVBE32mr")>;
495 def WriteMoveBE64mr : SchedWriteRes<[HWPort06, HWPort15, HWPort237, HWPort4]> {
498 def : InstRW<[WriteMoveBE64mr], (instregex "MOVBE64mr")>;
500 //-- Arithmetic instructions --//
504 def : InstRW<[Write2P0156_2P237_P4],
505 (instregex "(ADD|SUB)(8|16|32|64)m(r|i)",
506 "(ADD|SUB)(8|16|32|64)mi8", "(ADD|SUB)64mi32")>;
510 def : InstRW<[Write2P0156_Lat2], (instregex "(ADC|SBB)(8|16|32|64)r(r|i)",
511 "(ADC|SBB)(16|32|64)ri8",
513 "(ADC|SBB)(8|16|32|64)rr_REV")>;
516 def : InstRW<[Write2P0156_Lat2Ld, ReadAfterLd], (instregex "(ADC|SBB)(8|16|32|64)rm")>;
519 def : InstRW<[Write3P0156_2P237_P4],
520 (instregex "(ADC|SBB)(8|16|32|64)m(r|i)",
521 "(ADC|SBB)(16|32|64)mi8",
526 def : InstRW<[WriteP0156_2P237_P4],
527 (instregex "(INC|DEC|NOT|NEG)(8|16|32|64)m",
528 "(INC|DEC)64(16|32)m")>;
532 def WriteMul16 : SchedWriteRes<[HWPort1, HWPort0156]> {
536 def : InstRW<[WriteMul16], (instregex "IMUL16r", "MUL16r")>;
539 def WriteMul16Ld : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> {
543 def : InstRW<[WriteMul16Ld], (instregex "IMUL16m", "MUL16m")>;
546 def WriteMul32 : SchedWriteRes<[HWPort1, HWPort0156]> {
550 def : InstRW<[WriteMul32], (instregex "IMUL32r", "MUL32r")>;
553 def WriteMul32Ld : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> {
557 def : InstRW<[WriteMul32Ld], (instregex "IMUL32m", "MUL32m")>;
560 def WriteMul64 : SchedWriteRes<[HWPort1, HWPort6]> {
564 def : InstRW<[WriteMul64], (instregex "IMUL64r", "MUL64r")>;
567 def WriteMul64Ld : SchedWriteRes<[HWPort1, HWPort6, HWPort23]> {
571 def : InstRW<[WriteMul64Ld], (instregex "IMUL64m", "MUL64m")>;
574 def WriteMul16rri : SchedWriteRes<[HWPort1, HWPort0156]> {
578 def : InstRW<[WriteMul16rri], (instregex "IMUL16rri", "IMUL16rri8")>;
581 def WriteMul16rmi : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> {
585 def : InstRW<[WriteMul16rmi], (instregex "IMUL16rmi", "IMUL16rmi8")>;
589 def WriteMulX32 : SchedWriteRes<[HWPort1, HWPort056]> {
592 let ResourceCycles = [1, 2];
594 def : InstRW<[WriteMulX32], (instregex "MULX32rr")>;
597 def WriteMulX32Ld : SchedWriteRes<[HWPort1, HWPort056, HWPort23]> {
600 let ResourceCycles = [1, 2, 1];
602 def : InstRW<[WriteMulX32Ld], (instregex "MULX32rm")>;
605 def WriteMulX64 : SchedWriteRes<[HWPort1, HWPort6]> {
609 def : InstRW<[WriteMulX64], (instregex "MULX64rr")>;
612 def WriteMulX64Ld : SchedWriteRes<[HWPort1, HWPort6, HWPort23]> {
616 def : InstRW<[WriteMulX64Ld], (instregex "MULX64rm")>;
620 def WriteDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
624 def : InstRW<[WriteDiv8], (instregex "DIV8r")>;
627 def WriteDiv16 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
629 let NumMicroOps = 10;
631 def : InstRW<[WriteDiv16], (instregex "DIV16r")>;
634 def WriteDiv32 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
636 let NumMicroOps = 10;
638 def : InstRW<[WriteDiv32], (instregex "DIV32r")>;
641 def WriteDiv64 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
643 let NumMicroOps = 36;
645 def : InstRW<[WriteDiv64], (instregex "DIV64r")>;
649 def WriteIDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
653 def : InstRW<[WriteIDiv8], (instregex "IDIV8r")>;
656 def WriteIDiv16 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
658 let NumMicroOps = 10;
660 def : InstRW<[WriteIDiv16], (instregex "IDIV16r")>;
663 def WriteIDiv32 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
667 def : InstRW<[WriteIDiv32], (instregex "IDIV32r")>;
670 def WriteIDiv64 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
672 let NumMicroOps = 59;
674 def : InstRW<[WriteIDiv64], (instregex "IDIV64r")>;
676 //-- Logic instructions --//
680 def : InstRW<[Write2P0156_2P237_P4],
681 (instregex "(AND|OR|XOR)(8|16|32|64)m(r|i)",
682 "(AND|OR|XOR)(8|16|32|64)mi8", "(AND|OR|XOR)64mi32")>;
686 def WriteShiftRMW : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
688 let ResourceCycles = [2, 1, 1];
690 def : InstRW<[WriteShiftRMW], (instregex "S(A|H)(R|L)(8|16|32|64)m(i|1)")>;
693 def : InstRW<[Write3P06_Lat2], (instregex "S(A|H)(R|L)(8|16|32|64)rCL")>;
696 def WriteShiftClLdRMW : SchedWriteRes<[HWPort06, HWPort23, HWPort4]> {
698 let ResourceCycles = [3, 2, 1];
700 def : InstRW<[WriteShiftClLdRMW], (instregex "S(A|H)(R|L)(8|16|32|64)mCL")>;
704 def : InstRW<[Write2P06], (instregex "RO(R|L)(8|16|32|64)r1")>;
707 def WriteRotateRMW : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
709 let ResourceCycles = [2, 2, 1];
711 def : InstRW<[WriteRotateRMW], (instregex "RO(R|L)(8|16|32|64)mi")>;
714 def : InstRW<[Write3P06_Lat2], (instregex "RO(R|L)(8|16|32|64)rCL")>;
717 def WriteRotateRMWCL : SchedWriteRes<[]> {
720 def : InstRW<[WriteRotateRMWCL], (instregex "RO(R|L)(8|16|32|64)mCL")>;
724 def WriteRCr1 : SchedWriteRes<[HWPort06, HWPort0156]> {
727 let ResourceCycles = [2, 1];
729 def : InstRW<[WriteRCr1], (instregex "RC(R|L)(8|16|32|64)r1")>;
732 def WriteRCm1 : SchedWriteRes<[]> {
735 def : InstRW<[WriteRCm1], (instregex "RC(R|L)(8|16|32|64)m1")>;
738 def WriteRCri : SchedWriteRes<[HWPort0156]> {
742 def : InstRW<[WriteRCri], (instregex "RC(R|L)(8|16|32|64)r(i|CL)")>;
745 def WriteRCmi : SchedWriteRes<[]> {
746 let NumMicroOps = 11;
748 def : InstRW<[WriteRCmi], (instregex "RC(R|L)(8|16|32|64)m(i|CL)")>;
752 def WriteShDrr : SchedWriteRes<[HWPort1]> {
755 def : InstRW<[WriteShDrr], (instregex "SH(R|L)D(16|32|64)rri8")>;
758 def WriteShDmr : SchedWriteRes<[]> {
761 def : InstRW<[WriteShDmr], (instregex "SH(R|L)D(16|32|64)mri8")>;
764 def WriteShlDCL : SchedWriteRes<[HWPort0156]> {
768 def : InstRW<[WriteShlDCL], (instregex "SHLD(16|32|64)rrCL")>;
771 def WriteShrDCL : SchedWriteRes<[HWPort0156]> {
775 def : InstRW<[WriteShrDCL], (instregex "SHRD(16|32|64)rrCL")>;
778 def WriteShDmrCL : SchedWriteRes<[]> {
781 def : InstRW<[WriteShDmrCL], (instregex "SH(R|L)D(16|32|64)mrCL")>;
785 def : InstRW<[WriteShift], (instregex "BT(16|32|64)r(r|i8)")>;
788 def WriteBTmr : SchedWriteRes<[]> {
789 let NumMicroOps = 10;
791 def : InstRW<[WriteBTmr], (instregex "BT(16|32|64)mr")>;
794 def : InstRW<[WriteShiftLd], (instregex "BT(16|32|64)mi8")>;
798 def : InstRW<[WriteShift], (instregex "BT(R|S|C)(16|32|64)r(r|i8)")>;
801 def WriteBTRSCmr : SchedWriteRes<[]> {
802 let NumMicroOps = 11;
804 def : InstRW<[WriteBTRSCmr], (instregex "BT(R|S|C)(16|32|64)mr")>;
807 def : InstRW<[WriteShiftLd], (instregex "BT(R|S|C)(16|32|64)mi8")>;
811 def : InstRW<[WriteP1_Lat3], (instregex "BS(R|F)(16|32|64)rr")>;
813 def : InstRW<[WriteP1_Lat3Ld], (instregex "BS(R|F)(16|32|64)rm")>;
817 def : InstRW<[WriteShift],
818 (instregex "SET(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)r")>;
820 def WriteSetCCm : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
823 def : InstRW<[WriteSetCCm],
824 (instregex "SET(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)m")>;
827 def WriteCldStd : SchedWriteRes<[HWPort15, HWPort6]> {
830 def : InstRW<[WriteCldStd], (instregex "STD", "CLD")>;
834 def : InstRW<[WriteP1_Lat3], (instregex "(L|TZCNT)(16|32|64)rr")>;
836 def : InstRW<[WriteP1_Lat3Ld], (instregex "(L|TZCNT)(16|32|64)rm")>;
840 def : InstRW<[WriteP15], (instregex "ANDN(32|64)rr")>;
842 def : InstRW<[WriteP15Ld], (instregex "ANDN(32|64)rm")>;
846 def : InstRW<[WriteP15], (instregex "BLS(I|MSK|R)(32|64)rr")>;
848 def : InstRW<[WriteP15Ld], (instregex "BLS(I|MSK|R)(32|64)rm")>;
852 def : InstRW<[Write2P0156_Lat2], (instregex "BEXTR(32|64)rr")>;
854 def : InstRW<[Write2P0156_Lat2Ld], (instregex "BEXTR(32|64)rm")>;
858 def : InstRW<[WriteP15], (instregex "BZHI(32|64)rr")>;
860 def : InstRW<[WriteP15Ld], (instregex "BZHI(32|64)rm")>;
864 def : InstRW<[WriteP1_Lat3], (instregex "PDEP(32|64)rr", "PEXT(32|64)rr")>;
866 def : InstRW<[WriteP1_Lat3Ld], (instregex "PDEP(32|64)rm", "PEXT(32|64)rm")>;
868 //-- Control transfer instructions --//
871 def WriteJCXZ : SchedWriteRes<[HWPort0156, HWPort6]> {
874 def : InstRW<[WriteJCXZ], (instregex "JCXZ", "JECXZ_(32|64)", "JRCXZ")>;
877 def WriteLOOP : SchedWriteRes<[]> {
880 def : InstRW<[WriteLOOP], (instregex "LOOP")>;
883 def WriteLOOPE : SchedWriteRes<[]> {
884 let NumMicroOps = 11;
886 def : InstRW<[WriteLOOPE], (instregex "LOOPE", "LOOPNE")>;
890 def WriteCALLr : SchedWriteRes<[HWPort237, HWPort4, HWPort6]> {
893 def : InstRW<[WriteCALLr], (instregex "CALL(16|32)r")>;
896 def WriteCALLm : SchedWriteRes<[HWPort237, HWPort4, HWPort6]> {
898 let ResourceCycles = [2, 1, 1];
900 def : InstRW<[WriteCALLm], (instregex "CALL(16|32)m")>;
903 def WriteRET : SchedWriteRes<[HWPort237, HWPort6]> {
906 def : InstRW<[WriteRET], (instregex "RET(L|Q|W)", "LRET(L|Q|W)")>;
909 def WriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> {
911 let ResourceCycles = [1, 2, 1];
913 def : InstRW<[WriteRETI], (instregex "RETI(L|Q|W)", "LRETI(L|Q|W)")>;
917 def WriteBOUND : SchedWriteRes<[]> {
918 let NumMicroOps = 15;
920 def : InstRW<[WriteBOUND], (instregex "BOUNDS(16|32)rm")>;
923 def WriteINTO : SchedWriteRes<[]> {
926 def : InstRW<[WriteINTO], (instregex "INTO")>;
928 //-- String instructions --//
931 def : InstRW<[Write2P0156_P23], (instregex "LODS(B|W)")>;
934 def : InstRW<[WriteP0156_P23], (instregex "LODS(L|Q)")>;
937 def WriteSTOS : SchedWriteRes<[HWPort23, HWPort0156, HWPort4]> {
940 def : InstRW<[WriteSTOS], (instregex "STOS(B|L|Q|W)")>;
943 def WriteMOVS : SchedWriteRes<[HWPort23, HWPort4, HWPort0156]> {
946 let ResourceCycles = [2, 1, 2];
948 def : InstRW<[WriteMOVS], (instregex "MOVS(B|L|Q|W)")>;
951 def : InstRW<[Write2P0156_P23], (instregex "SCAS(B|W|L|Q)")>;
954 def WriteCMPS : SchedWriteRes<[HWPort23, HWPort0156]> {
957 let ResourceCycles = [2, 3];
959 def : InstRW<[WriteCMPS], (instregex "CMPS(B|L|Q|W)")>;
961 //-- Synchronization instructions --//
964 def WriteXADD : SchedWriteRes<[]> {
967 def : InstRW<[WriteXADD], (instregex "XADD(8|16|32|64)rm")>;
970 def WriteCMPXCHG : SchedWriteRes<[]> {
973 def : InstRW<[WriteCMPXCHG], (instregex "CMPXCHG(8|16|32|64)rm")>;
976 def WriteCMPXCHG8B : SchedWriteRes<[]> {
977 let NumMicroOps = 15;
979 def : InstRW<[WriteCMPXCHG8B], (instregex "CMPXCHG8B")>;
982 def WriteCMPXCHG16B : SchedWriteRes<[]> {
983 let NumMicroOps = 22;
985 def : InstRW<[WriteCMPXCHG16B], (instregex "CMPXCHG16B")>;
990 def WritePAUSE : SchedWriteRes<[HWPort05, HWPort6]> {
992 let ResourceCycles = [1, 3];
994 def : InstRW<[WritePAUSE], (instregex "PAUSE")>;
997 def : InstRW<[Write2P0156_P23], (instregex "LEAVE")>;
1000 def WriteXGETBV : SchedWriteRes<[]> {
1001 let NumMicroOps = 8;
1003 def : InstRW<[WriteXGETBV], (instregex "XGETBV")>;
1006 def WriteRDTSC : SchedWriteRes<[]> {
1007 let NumMicroOps = 15;
1009 def : InstRW<[WriteRDTSC], (instregex "RDTSC")>;
1012 def WriteRDPMC : SchedWriteRes<[]> {
1013 let NumMicroOps = 34;
1015 def : InstRW<[WriteRDPMC], (instregex "RDPMC")>;
1018 def WriteRDRAND : SchedWriteRes<[HWPort23, HWPort015]> {
1019 let NumMicroOps = 17;
1020 let ResourceCycles = [1, 16];
1022 def : InstRW<[WriteRDRAND], (instregex "RDRAND(16|32|64)r")>;
1024 //=== Floating Point x87 Instructions ===//
1025 //-- Move instructions --//
1029 def : InstRW<[WriteP01], (instregex "LD_Frr")>;
1031 def WriteLD_F80m : SchedWriteRes<[HWPort01, HWPort23]> {
1033 let NumMicroOps = 4;
1034 let ResourceCycles = [2, 2];
1036 def : InstRW<[WriteLD_F80m], (instregex "LD_F80m")>;
1040 def WriteFBLD : SchedWriteRes<[]> {
1042 let NumMicroOps = 43;
1044 def : InstRW<[WriteFBLD], (instregex "FBLDm")>;
1048 def : InstRW<[WriteP01], (instregex "ST_(F|FP)rr")>;
1051 def WriteST_FP80m : SchedWriteRes<[HWPort0156, HWPort23, HWPort4]> {
1052 let NumMicroOps = 7;
1053 let ResourceCycles = [3, 2, 2];
1055 def : InstRW<[WriteST_FP80m], (instregex "ST_FP80m")>;
1059 def WriteFBSTP : SchedWriteRes<[]> {
1060 let NumMicroOps = 226;
1062 def : InstRW<[WriteFBSTP], (instregex "FBSTPm")>;
1065 def : InstRW<[WriteNop], (instregex "XCH_F")>;
1068 def WriteFILD : SchedWriteRes<[HWPort01, HWPort23]> {
1070 let NumMicroOps = 2;
1072 def : InstRW<[WriteFILD], (instregex "ILD_F(16|32|64)m")>;
1075 def WriteFIST : SchedWriteRes<[HWPort1, HWPort23, HWPort4]> {
1077 let NumMicroOps = 3;
1079 def : InstRW<[WriteFIST], (instregex "IST_(F|FP)(16|32)m")>;
1082 def : InstRW<[WriteP01], (instregex "LD_F0")>;
1085 def : InstRW<[Write2P01], (instregex "LD_F1")>;
1087 // FLDPI FLDL2E etc.
1088 def : InstRW<[Write2P01], (instregex "FLDPI", "FLDL2(T|E)" "FLDL(G|N)2")>;
1091 def WriteFCMOVcc : SchedWriteRes<[HWPort0, HWPort5]> {
1093 let NumMicroOps = 3;
1094 let ResourceCycles = [2, 1];
1096 def : InstRW<[WriteFCMOVcc], (instregex "CMOV(B|BE|P|NB|NBE|NE|NP)_F")>;
1100 def WriteFNSTSW : SchedWriteRes<[HWPort0, HWPort0156]> {
1101 let NumMicroOps = 2;
1103 def : InstRW<[WriteFNSTSW], (instregex "FNSTSW16r")>;
1106 def WriteFNSTSWm : SchedWriteRes<[HWPort0, HWPort4, HWPort237]> {
1108 let NumMicroOps = 3;
1110 def : InstRW<[WriteFNSTSWm], (instregex "FNSTSWm")>;
1113 def WriteFLDCW : SchedWriteRes<[HWPort01, HWPort23, HWPort6]> {
1115 let NumMicroOps = 3;
1117 def : InstRW<[WriteFLDCW], (instregex "FLDCW16m")>;
1120 def WriteFNSTCW : SchedWriteRes<[HWPort237, HWPort4, HWPort6]> {
1121 let NumMicroOps = 3;
1123 def : InstRW<[WriteFNSTCW], (instregex "FNSTCW16m")>;
1126 def : InstRW<[WriteP01], (instregex "FINCSTP", "FDECSTP")>;
1129 def : InstRW<[WriteP01], (instregex "FFREE")>;
1132 def WriteFNSAVE : SchedWriteRes<[]> {
1133 let NumMicroOps = 147;
1135 def : InstRW<[WriteFNSAVE], (instregex "FSAVEm")>;
1138 def WriteFRSTOR : SchedWriteRes<[]> {
1139 let NumMicroOps = 90;
1141 def : InstRW<[WriteFRSTOR], (instregex "FRSTORm")>;
1143 //-- Arithmetic instructions --//
1146 def : InstRW<[WriteP0], (instregex "ABS_F")>;
1149 def : InstRW<[WriteP0], (instregex "CHS_F")>;
1151 // FCOM(P) FUCOM(P).
1153 def : InstRW<[WriteP1], (instregex "COM_FST0r", "COMP_FST0r", "UCOM_Fr",
1156 def : InstRW<[WriteP1_P23], (instregex "FCOM(32|64)m", "FCOMP(32|64)m")>;
1160 def : InstRW<[Write2P01], (instregex "FCOMPP", "UCOM_FPPr")>;
1162 // FCOMI(P) FUCOMI(P).
1164 def : InstRW<[Write3P01], (instregex "COM_FIr", "COM_FIPr", "UCOM_FIr",
1168 def : InstRW<[Write2P1_P23], (instregex "FICOM(16|32)m", "FICOMP(16|32)m")>;
1171 def : InstRW<[WriteP1], (instregex "TST_F")>;
1174 def : InstRW<[Write2P1], (instregex "FXAM")>;
1177 def WriteFPREM : SchedWriteRes<[]> {
1179 let NumMicroOps = 28;
1181 def : InstRW<[WriteFPREM], (instregex "FPREM")>;
1184 def WriteFPREM1 : SchedWriteRes<[]> {
1186 let NumMicroOps = 41;
1188 def : InstRW<[WriteFPREM1], (instregex "FPREM1")>;
1191 def WriteFRNDINT : SchedWriteRes<[]> {
1193 let NumMicroOps = 17;
1195 def : InstRW<[WriteFRNDINT], (instregex "FRNDINT")>;
1197 //-- Math instructions --//
1200 def WriteFSCALE : SchedWriteRes<[]> {
1201 let Latency = 75; // 49-125
1202 let NumMicroOps = 50; // 25-75
1204 def : InstRW<[WriteFSCALE], (instregex "FSCALE")>;
1207 def WriteFXTRACT : SchedWriteRes<[]> {
1209 let NumMicroOps = 17;
1211 def : InstRW<[WriteFXTRACT], (instregex "FXTRACT")>;
1213 //-- Other instructions --//
1216 def : InstRW<[WriteP01], (instregex "FNOP")>;
1219 def : InstRW<[Write2P01], (instregex "WAIT")>;
1222 def : InstRW<[Write5P0156], (instregex "FNCLEX")>;
1225 def WriteFNINIT : SchedWriteRes<[]> {
1226 let NumMicroOps = 26;
1228 def : InstRW<[WriteFNINIT], (instregex "FNINIT")>;
1230 //=== Integer MMX and XMM Instructions ===//
1231 //-- Move instructions --//
1235 def : InstRW<[WriteP0], (instregex "MMX_MOVD64grr", "MMX_MOVD64from64rr",
1236 "VMOVPDI2DIrr", "MOVPDI2DIrr")>;
1239 def : InstRW<[WriteP5], (instregex "MMX_MOVD64rr", "MMX_MOVD64to64rr",
1240 "VMOVDI2PDIrr", "MOVDI2PDIrr")>;
1244 def : InstRW<[WriteP0], (instregex "VMOVPQIto64rr")>;
1247 def : InstRW<[WriteP5], (instregex "VMOV64toPQIrr", "VMOVZQI2PQIrr")>;
1250 def : InstRW<[WriteP015], (instregex "MMX_MOVQ64rr")>;
1254 def : InstRW<[WriteP015], (instregex "MOVDQ(A|U)rr", "VMOVDQ(A|U)rr",
1255 "MOVDQ(A|U)rr_REV", "VMOVDQ(A|U)rr_REV",
1256 "VMOVDQ(A|U)Yrr", "VMOVDQ(A|U)Yrr_REV")>;
1259 def : InstRW<[WriteP01_P5], (instregex "MMX_MOVDQ2Qrr")>;
1262 def : InstRW<[WriteP015], (instregex "MMX_MOVQ2DQrr")>;
1267 def WriteMMXPACKSSrr : SchedWriteRes<[HWPort5]> {
1269 let NumMicroOps = 3;
1270 let ResourceCycles = [3];
1272 def : InstRW<[WriteMMXPACKSSrr], (instregex "MMX_PACKSSDWirr",
1273 "MMX_PACKSSWBirr", "MMX_PACKUSWBirr")>;
1276 def WriteMMXPACKSSrm : SchedWriteRes<[HWPort23, HWPort5]> {
1278 let NumMicroOps = 3;
1279 let ResourceCycles = [1, 3];
1281 def : InstRW<[WriteMMXPACKSSrm], (instregex "MMX_PACKSSDWirm",
1282 "MMX_PACKSSWBirm", "MMX_PACKUSWBirm")>;
1284 // VPMOVSX/ZX BW BD BQ DW DQ.
1286 def WriteVPMOVSX : SchedWriteRes<[HWPort5]> {
1288 let NumMicroOps = 1;
1290 def : InstRW<[WriteVPMOVSX], (instregex "VPMOV(SX|ZX)(BW|BQ|DW|DQ)Yrr")>;
1294 def WritePBLENDWr : SchedWriteRes<[HWPort5]>;
1295 def : InstRW<[WritePBLENDWr], (instregex "(V?)PBLENDW(Y?)rri")>;
1298 def WritePBLENDWm : SchedWriteRes<[HWPort5, HWPort23]> {
1299 let NumMicroOps = 2;
1301 let ResourceCycles = [1, 1];
1303 def : InstRW<[WritePBLENDWm, ReadAfterLd], (instregex "(V?)PBLENDW(Y?)rmi")>;
1307 def WriteVPBLENDDr : SchedWriteRes<[HWPort015]>;
1308 def : InstRW<[WriteVPBLENDDr], (instregex "VPBLENDD(Y?)rri")>;
1311 def WriteVPBLENDDm : SchedWriteRes<[HWPort015, HWPort23]> {
1312 let NumMicroOps = 2;
1314 let ResourceCycles = [1, 1];
1316 def : InstRW<[WriteVPBLENDDm, ReadAfterLd], (instregex "VPBLENDD(Y?)rmi")>;
1319 def WriteMASKMOVQ : SchedWriteRes<[HWPort0, HWPort4, HWPort23]> {
1321 let NumMicroOps = 4;
1322 let ResourceCycles = [1, 1, 2];
1324 def : InstRW<[WriteMASKMOVQ], (instregex "MMX_MASKMOVQ(64)?")>;
1327 def WriteMASKMOVDQU : SchedWriteRes<[HWPort04, HWPort56, HWPort23]> {
1329 let NumMicroOps = 10;
1330 let ResourceCycles = [4, 2, 4];
1332 def : InstRW<[WriteMASKMOVDQU], (instregex "(V?)MASKMOVDQU(64)?")>;
1336 def WriteVPMASKMOVr : SchedWriteRes<[HWPort5, HWPort23]> {
1338 let NumMicroOps = 3;
1339 let ResourceCycles = [2, 1];
1341 def : InstRW<[WriteVPMASKMOVr, ReadAfterLd],
1342 (instregex "VPMASKMOV(D|Q)(Y?)rm")>;
1345 def WriteVPMASKMOVm : SchedWriteRes<[HWPort0, HWPort1, HWPort4, HWPort23]> {
1347 let NumMicroOps = 4;
1348 let ResourceCycles = [1, 1, 1, 1];
1350 def : InstRW<[WriteVPMASKMOVm], (instregex "VPMASKMOV(D|Q)(Y?)mr")>;
1353 def WritePMOVMSKB : SchedWriteRes<[HWPort0]> {
1356 def : InstRW<[WritePMOVMSKB], (instregex "(V|MMX_)?PMOVMSKB(Y?)rr")>;
1360 def WritePEXTRr : SchedWriteRes<[HWPort0, HWPort5]> {
1362 let NumMicroOps = 2;
1363 let ResourceCycles = [1, 1];
1365 def : InstRW<[WritePEXTRr], (instregex "PEXTR(B|W|D|Q)rr", "MMX_PEXTRWirri")>;
1368 def WritePEXTRm : SchedWriteRes<[HWPort23, HWPort4, HWPort5]> {
1369 let NumMicroOps = 3;
1370 let ResourceCycles = [1, 1, 1];
1372 def : InstRW<[WritePEXTRm], (instregex "PEXTR(B|W|D|Q)mr")>;
1376 def WriteVPBROADCAST128Ld : SchedWriteRes<[HWPort01, HWPort23, HWPort5]> {
1378 let NumMicroOps = 3;
1379 let ResourceCycles = [1, 1, 1];
1381 def : InstRW<[WriteVPBROADCAST128Ld, ReadAfterLd],
1382 (instregex "VPBROADCAST(B|W)rm")>;
1385 def WriteVPBROADCAST256Ld : SchedWriteRes<[HWPort01, HWPort23, HWPort5]> {
1387 let NumMicroOps = 3;
1388 let ResourceCycles = [1, 1, 1];
1390 def : InstRW<[WriteVPBROADCAST256Ld, ReadAfterLd],
1391 (instregex "VPBROADCAST(B|W)Yrm")>;
1395 def WriteVPGATHERDD128 : SchedWriteRes<[]> {
1396 let NumMicroOps = 20;
1398 def : InstRW<[WriteVPGATHERDD128, ReadAfterLd], (instregex "VPGATHERDDrm")>;
1401 def WriteVPGATHERDD256 : SchedWriteRes<[]> {
1402 let NumMicroOps = 34;
1404 def : InstRW<[WriteVPGATHERDD256, ReadAfterLd], (instregex "VPGATHERDDYrm")>;
1408 def WriteVPGATHERQD128 : SchedWriteRes<[]> {
1409 let NumMicroOps = 15;
1411 def : InstRW<[WriteVPGATHERQD128, ReadAfterLd], (instregex "VPGATHERQDrm")>;
1414 def WriteVPGATHERQD256 : SchedWriteRes<[]> {
1415 let NumMicroOps = 22;
1417 def : InstRW<[WriteVPGATHERQD256, ReadAfterLd], (instregex "VPGATHERQDYrm")>;
1421 def WriteVPGATHERDQ128 : SchedWriteRes<[]> {
1422 let NumMicroOps = 12;
1424 def : InstRW<[WriteVPGATHERDQ128, ReadAfterLd], (instregex "VPGATHERDQrm")>;
1427 def WriteVPGATHERDQ256 : SchedWriteRes<[]> {
1428 let NumMicroOps = 20;
1430 def : InstRW<[WriteVPGATHERDQ256, ReadAfterLd], (instregex "VPGATHERDQYrm")>;
1434 def WriteVPGATHERQQ128 : SchedWriteRes<[]> {
1435 let NumMicroOps = 14;
1437 def : InstRW<[WriteVPGATHERQQ128, ReadAfterLd], (instregex "VPGATHERQQrm")>;
1440 def WriteVPGATHERQQ256 : SchedWriteRes<[]> {
1441 let NumMicroOps = 22;
1443 def : InstRW<[WriteVPGATHERQQ256, ReadAfterLd], (instregex "VPGATHERQQYrm")>;
1445 //-- Arithmetic instructions --//
1447 // PHADD|PHSUB (S) W/D.
1449 def WritePHADDSUBr : SchedWriteRes<[HWPort1, HWPort5]> {
1451 let NumMicroOps = 3;
1452 let ResourceCycles = [1, 2];
1454 def : InstRW<[WritePHADDSUBr], (instregex "MMX_PHADD(W?)rr64",
1456 "MMX_PHSUB(W|D)rr64",
1458 "(V?)PH(ADD|SUB)(W|D)(Y?)rr",
1459 "(V?)PH(ADD|SUB)SWrr(256)?")>;
1462 def WritePHADDSUBm : SchedWriteRes<[HWPort1, HWPort5, HWPort23]> {
1464 let NumMicroOps = 3;
1465 let ResourceCycles = [1, 2, 1];
1467 def : InstRW<[WritePHADDSUBm, ReadAfterLd],
1468 (instregex "MMX_PHADD(W?)rm64",
1470 "MMX_PHSUB(W|D)rm64",
1472 "(V?)PH(ADD|SUB)(W|D)(Y?)rm",
1473 "(V?)PH(ADD|SUB)SWrm(128|256)?")>;
1477 def WritePCMPGTQr : SchedWriteRes<[HWPort0]> {
1479 let NumMicroOps = 1;
1481 def : InstRW<[WritePCMPGTQr], (instregex "(V?)PCMPGTQ(Y?)rr")>;
1484 def WritePCMPGTQm : SchedWriteRes<[HWPort0, HWPort23]> {
1486 let NumMicroOps = 2;
1487 let ResourceCycles = [1, 1];
1489 def : InstRW<[WritePCMPGTQm, ReadAfterLd], (instregex "(V?)PCMPGTQ(Y?)rm")>;
1493 def WritePMULLDr : SchedWriteRes<[HWPort0]> {
1495 let NumMicroOps = 2;
1496 let ResourceCycles = [2];
1498 def : InstRW<[WritePMULLDr], (instregex "(V?)PMULLD(Y?)rr")>;
1501 def WritePMULLDm : SchedWriteRes<[HWPort0, HWPort23]> {
1503 let NumMicroOps = 3;
1504 let ResourceCycles = [2, 1];
1506 def : InstRW<[WritePMULLDm, ReadAfterLd], (instregex "(V?)PMULLD(Y?)rm")>;