1 //=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the machine model for Sandy Bridge to support instruction
11 // scheduling and other instruction cost heuristics.
13 //===----------------------------------------------------------------------===//
15 def SandyBridgeModel : SchedMachineModel {
16 // All x86 instructions are modeled as a single micro-op, and SB can decode 4
17 // instructions per cycle.
18 // FIXME: Identify instructions that aren't a single fused micro-op.
20 let MicroOpBufferSize = 168; // Based on the reorder buffer.
22 let MispredictPenalty = 16;
24 // Based on the LSD (loop-stream detector) queue size.
25 let LoopMicroOpBufferSize = 28;
27 // FIXME: SSE4 and AVX are unimplemented. This flag is set to allow
28 // the scheduler to assign a default model to unrecognized opcodes.
29 let CompleteModel = 0;
32 let SchedModel = SandyBridgeModel in {
34 // Sandy Bridge can issue micro-ops to 6 different ports in one cycle.
36 // Ports 0, 1, and 5 handle all computation.
37 def SBPort0 : ProcResource<1>;
38 def SBPort1 : ProcResource<1>;
39 def SBPort5 : ProcResource<1>;
41 // Ports 2 and 3 are identical. They handle loads and the address half of
43 def SBPort23 : ProcResource<2>;
45 // Port 4 gets the data half of stores. Store data can be available later than
46 // the store address, but since we don't model the latency of stores, we can
48 def SBPort4 : ProcResource<1>;
50 // Many micro-ops are capable of issuing on multiple ports.
51 def SBPort05 : ProcResGroup<[SBPort0, SBPort5]>;
52 def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>;
53 def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>;
55 // 54 Entry Unified Scheduler
56 def SBPortAny : ProcResGroup<[SBPort0, SBPort1, SBPort23, SBPort4, SBPort5]> {
60 // Integer division issued on port 0.
61 def SBDivider : ProcResource<1>;
63 // Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4
64 // cycles after the memory operand.
65 def : ReadAdvance<ReadAfterLd, 4>;
67 // Many SchedWrites are defined in pairs with and without a folded load.
68 // Instructions with folded loads are usually micro-fused, so they only appear
69 // as two micro-ops when queued in the reservation station.
70 // This multiclass defines the resource usage for variants with and without
72 multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW,
73 ProcResourceKind ExePort,
75 // Register variant is using a single cycle on ExePort.
76 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
78 // Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the
80 def : WriteRes<SchedRW.Folded, [SBPort23, ExePort]> {
81 let Latency = !add(Lat, 4);
85 // A folded store needs a cycle on port 4 for the store data, but it does not
86 // need an extra port 2/3 cycle to recompute the address.
87 def : WriteRes<WriteRMW, [SBPort4]>;
89 def : WriteRes<WriteStore, [SBPort23, SBPort4]>;
90 def : WriteRes<WriteLoad, [SBPort23]> { let Latency = 4; }
91 def : WriteRes<WriteMove, [SBPort015]>;
92 def : WriteRes<WriteZero, []>;
94 defm : SBWriteResPair<WriteALU, SBPort015, 1>;
95 defm : SBWriteResPair<WriteIMul, SBPort1, 3>;
96 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
97 defm : SBWriteResPair<WriteShift, SBPort05, 1>;
98 defm : SBWriteResPair<WriteJump, SBPort5, 1>;
100 // This is for simple LEAs with one or two input operands.
101 // The complex ones can only execute on port 1, and they require two cycles on
102 // the port to read all inputs. We don't model that.
103 def : WriteRes<WriteLEA, [SBPort15]>;
105 // This is quite rough, latency depends on the dividend.
106 def : WriteRes<WriteIDiv, [SBPort0, SBDivider]> {
108 let ResourceCycles = [1, 10];
110 def : WriteRes<WriteIDivLd, [SBPort23, SBPort0, SBDivider]> {
112 let ResourceCycles = [1, 1, 10];
115 // Scalar and vector floating point.
116 defm : SBWriteResPair<WriteFAdd, SBPort1, 3>;
117 defm : SBWriteResPair<WriteFMul, SBPort0, 5>;
118 defm : SBWriteResPair<WriteFDiv, SBPort0, 12>; // 10-14 cycles.
119 defm : SBWriteResPair<WriteFRcp, SBPort0, 5>;
120 defm : SBWriteResPair<WriteFSqrt, SBPort0, 15>;
121 defm : SBWriteResPair<WriteCvtF2I, SBPort1, 3>;
122 defm : SBWriteResPair<WriteCvtI2F, SBPort1, 4>;
123 defm : SBWriteResPair<WriteCvtF2F, SBPort1, 3>;
124 defm : SBWriteResPair<WriteFShuffle, SBPort5, 1>;
125 defm : SBWriteResPair<WriteFBlend, SBPort05, 1>;
126 def : WriteRes<WriteFVarBlend, [SBPort0, SBPort5]> {
128 let ResourceCycles = [1, 1];
130 def : WriteRes<WriteFVarBlendLd, [SBPort0, SBPort5, SBPort23]> {
132 let ResourceCycles = [1, 1, 1];
135 // Vector integer operations.
136 defm : SBWriteResPair<WriteVecShift, SBPort05, 1>;
137 defm : SBWriteResPair<WriteVecLogic, SBPort015, 1>;
138 defm : SBWriteResPair<WriteVecALU, SBPort15, 1>;
139 defm : SBWriteResPair<WriteVecIMul, SBPort0, 5>;
140 defm : SBWriteResPair<WriteShuffle, SBPort15, 1>;
141 defm : SBWriteResPair<WriteBlend, SBPort15, 1>;
142 def : WriteRes<WriteVarBlend, [SBPort1, SBPort5]> {
144 let ResourceCycles = [1, 1];
146 def : WriteRes<WriteVarBlendLd, [SBPort1, SBPort5, SBPort23]> {
148 let ResourceCycles = [1, 1, 1];
150 def : WriteRes<WriteMPSAD, [SBPort0, SBPort1, SBPort5]> {
152 let ResourceCycles = [1, 1, 1];
154 def : WriteRes<WriteMPSADLd, [SBPort0, SBPort1, SBPort5, SBPort23]> {
156 let ResourceCycles = [1, 1, 1, 1];
159 // String instructions.
160 // Packed Compare Implicit Length Strings, Return Mask
161 def : WriteRes<WritePCmpIStrM, [SBPort015]> {
163 let ResourceCycles = [3];
165 def : WriteRes<WritePCmpIStrMLd, [SBPort015, SBPort23]> {
167 let ResourceCycles = [3, 1];
170 // Packed Compare Explicit Length Strings, Return Mask
171 def : WriteRes<WritePCmpEStrM, [SBPort015]> {
173 let ResourceCycles = [8];
175 def : WriteRes<WritePCmpEStrMLd, [SBPort015, SBPort23]> {
177 let ResourceCycles = [7, 1];
180 // Packed Compare Implicit Length Strings, Return Index
181 def : WriteRes<WritePCmpIStrI, [SBPort015]> {
183 let ResourceCycles = [3];
185 def : WriteRes<WritePCmpIStrILd, [SBPort015, SBPort23]> {
187 let ResourceCycles = [3, 1];
190 // Packed Compare Explicit Length Strings, Return Index
191 def : WriteRes<WritePCmpEStrI, [SBPort015]> {
193 let ResourceCycles = [8];
195 def : WriteRes<WritePCmpEStrILd, [SBPort015, SBPort23]> {
197 let ResourceCycles = [7, 1];
201 def : WriteRes<WriteAESDecEnc, [SBPort015]> {
203 let ResourceCycles = [2];
205 def : WriteRes<WriteAESDecEncLd, [SBPort015, SBPort23]> {
207 let ResourceCycles = [2, 1];
210 def : WriteRes<WriteAESIMC, [SBPort015]> {
212 let ResourceCycles = [2];
214 def : WriteRes<WriteAESIMCLd, [SBPort015, SBPort23]> {
216 let ResourceCycles = [2, 1];
219 def : WriteRes<WriteAESKeyGen, [SBPort015]> {
221 let ResourceCycles = [11];
223 def : WriteRes<WriteAESKeyGenLd, [SBPort015, SBPort23]> {
225 let ResourceCycles = [10, 1];
228 // Carry-less multiplication instructions.
229 def : WriteRes<WriteCLMul, [SBPort015]> {
231 let ResourceCycles = [18];
233 def : WriteRes<WriteCLMulLd, [SBPort015, SBPort23]> {
235 let ResourceCycles = [17, 1];
239 def : WriteRes<WriteSystem, [SBPort015]> { let Latency = 100; }
240 def : WriteRes<WriteMicrocoded, [SBPort015]> { let Latency = 100; }
241 def : WriteRes<WriteFence, [SBPort23, SBPort4]>;
242 def : WriteRes<WriteNop, []>;
244 // AVX2 is not supported on that architecture, but we should define the basic
245 // scheduling resources anyway.
246 defm : SBWriteResPair<WriteFShuffle256, SBPort0, 1>;
247 defm : SBWriteResPair<WriteShuffle256, SBPort0, 1>;
248 defm : SBWriteResPair<WriteVarVecShift, SBPort0, 1>;