1 //=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the machine model for Sandy Bridge to support instruction
11 // scheduling and other instruction cost heuristics.
13 //===----------------------------------------------------------------------===//
15 def SandyBridgeModel : SchedMachineModel {
16 // All x86 instructions are modeled as a single micro-op, and SB can decode 4
17 // instructions per cycle.
18 // FIXME: Identify instructions that aren't a single fused micro-op.
20 let MicroOpBufferSize = 168; // Based on the reorder buffer.
22 let MispredictPenalty = 16;
24 // FIXME: SSE4 and AVX are unimplemented. This flag is set to allow
25 // the scheduler to assign a default model to unrecognized opcodes.
26 let CompleteModel = 0;
29 let SchedModel = SandyBridgeModel in {
31 // Sandy Bridge can issue micro-ops to 6 different ports in one cycle.
33 // Ports 0, 1, and 5 handle all computation.
34 def SBPort0 : ProcResource<1>;
35 def SBPort1 : ProcResource<1>;
36 def SBPort5 : ProcResource<1>;
38 // Ports 2 and 3 are identical. They handle loads and the address half of
40 def SBPort23 : ProcResource<2>;
42 // Port 4 gets the data half of stores. Store data can be available later than
43 // the store address, but since we don't model the latency of stores, we can
45 def SBPort4 : ProcResource<1>;
47 // Many micro-ops are capable of issuing on multiple ports.
48 def SBPort05 : ProcResGroup<[SBPort0, SBPort5]>;
49 def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>;
50 def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>;
52 // 54 Entry Unified Scheduler
53 def SBPortAny : ProcResGroup<[SBPort0, SBPort1, SBPort23, SBPort4, SBPort5]> {
57 // Integer division issued on port 0.
58 def SBDivider : ProcResource<1>;
60 // Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4
61 // cycles after the memory operand.
62 def : ReadAdvance<ReadAfterLd, 4>;
64 // Many SchedWrites are defined in pairs with and without a folded load.
65 // Instructions with folded loads are usually micro-fused, so they only appear
66 // as two micro-ops when queued in the reservation station.
67 // This multiclass defines the resource usage for variants with and without
69 multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW,
70 ProcResourceKind ExePort,
72 // Register variant is using a single cycle on ExePort.
73 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
75 // Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the
77 def : WriteRes<SchedRW.Folded, [SBPort23, ExePort]> {
78 let Latency = !add(Lat, 4);
82 // A folded store needs a cycle on port 4 for the store data, but it does not
83 // need an extra port 2/3 cycle to recompute the address.
84 def : WriteRes<WriteRMW, [SBPort4]>;
86 def : WriteRes<WriteStore, [SBPort23, SBPort4]>;
87 def : WriteRes<WriteLoad, [SBPort23]> { let Latency = 4; }
88 def : WriteRes<WriteMove, [SBPort015]>;
89 def : WriteRes<WriteZero, []>;
91 defm : SBWriteResPair<WriteALU, SBPort015, 1>;
92 defm : SBWriteResPair<WriteIMul, SBPort1, 3>;
93 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
94 defm : SBWriteResPair<WriteShift, SBPort05, 1>;
95 defm : SBWriteResPair<WriteJump, SBPort5, 1>;
97 // This is for simple LEAs with one or two input operands.
98 // The complex ones can only execute on port 1, and they require two cycles on
99 // the port to read all inputs. We don't model that.
100 def : WriteRes<WriteLEA, [SBPort15]>;
102 // This is quite rough, latency depends on the dividend.
103 def : WriteRes<WriteIDiv, [SBPort0, SBDivider]> {
105 let ResourceCycles = [1, 10];
107 def : WriteRes<WriteIDivLd, [SBPort23, SBPort0, SBDivider]> {
109 let ResourceCycles = [1, 1, 10];
112 // Scalar and vector floating point.
113 defm : SBWriteResPair<WriteFAdd, SBPort1, 3>;
114 defm : SBWriteResPair<WriteFMul, SBPort0, 5>;
115 defm : SBWriteResPair<WriteFDiv, SBPort0, 12>; // 10-14 cycles.
116 defm : SBWriteResPair<WriteFRcp, SBPort0, 5>;
117 defm : SBWriteResPair<WriteFSqrt, SBPort0, 15>;
118 defm : SBWriteResPair<WriteCvtF2I, SBPort1, 3>;
119 defm : SBWriteResPair<WriteCvtI2F, SBPort1, 4>;
120 defm : SBWriteResPair<WriteCvtF2F, SBPort1, 3>;
121 defm : SBWriteResPair<WriteFShuffle, SBPort5, 1>;
122 defm : SBWriteResPair<WriteFBlend, SBPort05, 1>;
123 def : WriteRes<WriteFVarBlend, [SBPort0, SBPort5]> {
125 let ResourceCycles = [1, 1];
127 def : WriteRes<WriteFVarBlendLd, [SBPort0, SBPort5, SBPort23]> {
129 let ResourceCycles = [1, 1, 1];
132 // Vector integer operations.
133 defm : SBWriteResPair<WriteVecShift, SBPort05, 1>;
134 defm : SBWriteResPair<WriteVecLogic, SBPort015, 1>;
135 defm : SBWriteResPair<WriteVecALU, SBPort15, 1>;
136 defm : SBWriteResPair<WriteVecIMul, SBPort0, 5>;
137 defm : SBWriteResPair<WriteShuffle, SBPort15, 1>;
138 defm : SBWriteResPair<WriteBlend, SBPort15, 1>;
139 def : WriteRes<WriteVarBlend, [SBPort1, SBPort5]> {
141 let ResourceCycles = [1, 1];
143 def : WriteRes<WriteVarBlendLd, [SBPort1, SBPort5, SBPort23]> {
145 let ResourceCycles = [1, 1, 1];
147 def : WriteRes<WriteMPSAD, [SBPort0, SBPort1, SBPort5]> {
149 let ResourceCycles = [1, 1, 1];
151 def : WriteRes<WriteMPSADLd, [SBPort0, SBPort1, SBPort5, SBPort23]> {
153 let ResourceCycles = [1, 1, 1, 1];
156 // String instructions.
157 // Packed Compare Implicit Length Strings, Return Mask
158 def : WriteRes<WritePCmpIStrM, [SBPort015]> {
160 let ResourceCycles = [3];
162 def : WriteRes<WritePCmpIStrMLd, [SBPort015, SBPort23]> {
164 let ResourceCycles = [3, 1];
167 // Packed Compare Explicit Length Strings, Return Mask
168 def : WriteRes<WritePCmpEStrM, [SBPort015]> {
170 let ResourceCycles = [8];
172 def : WriteRes<WritePCmpEStrMLd, [SBPort015, SBPort23]> {
174 let ResourceCycles = [7, 1];
177 // Packed Compare Implicit Length Strings, Return Index
178 def : WriteRes<WritePCmpIStrI, [SBPort015]> {
180 let ResourceCycles = [3];
182 def : WriteRes<WritePCmpIStrILd, [SBPort015, SBPort23]> {
184 let ResourceCycles = [3, 1];
187 // Packed Compare Explicit Length Strings, Return Index
188 def : WriteRes<WritePCmpEStrI, [SBPort015]> {
190 let ResourceCycles = [8];
192 def : WriteRes<WritePCmpEStrILd, [SBPort015, SBPort23]> {
194 let ResourceCycles = [7, 1];
198 def : WriteRes<WriteAESDecEnc, [SBPort015]> {
200 let ResourceCycles = [2];
202 def : WriteRes<WriteAESDecEncLd, [SBPort015, SBPort23]> {
204 let ResourceCycles = [2, 1];
207 def : WriteRes<WriteAESIMC, [SBPort015]> {
209 let ResourceCycles = [2];
211 def : WriteRes<WriteAESIMCLd, [SBPort015, SBPort23]> {
213 let ResourceCycles = [2, 1];
216 def : WriteRes<WriteAESKeyGen, [SBPort015]> {
218 let ResourceCycles = [11];
220 def : WriteRes<WriteAESKeyGenLd, [SBPort015, SBPort23]> {
222 let ResourceCycles = [10, 1];
225 // Carry-less multiplication instructions.
226 def : WriteRes<WriteCLMul, [SBPort015]> {
228 let ResourceCycles = [18];
230 def : WriteRes<WriteCLMulLd, [SBPort015, SBPort23]> {
232 let ResourceCycles = [17, 1];
236 def : WriteRes<WriteSystem, [SBPort015]> { let Latency = 100; }
237 def : WriteRes<WriteMicrocoded, [SBPort015]> { let Latency = 100; }
238 def : WriteRes<WriteFence, [SBPort23, SBPort4]>;
239 def : WriteRes<WriteNop, []>;
241 // AVX2 is not supported on that architecture, but we should define the basic
242 // scheduling resources anyway.
243 defm : SBWriteResPair<WriteFShuffle256, SBPort0, 1>;
244 defm : SBWriteResPair<WriteShuffle256, SBPort0, 1>;
245 defm : SBWriteResPair<WriteVarVecShift, SBPort0, 1>;