1 //===- X86ScheduleAtom.td - X86 Atom Scheduling Definitions -*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the itinerary class data for the Intel Atom (Bonnell)
13 //===----------------------------------------------------------------------===//
16 // Scheduling information derived from the "Intel 64 and IA32 Architectures
17 // Optimization Reference Manual", Chapter 13, Section 4.
20 def Port0 : FuncUnit; // ALU: ALU0, shift/rotate, load/store
21 // SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide
22 def Port1 : FuncUnit; // ALU: ALU1, bit processing, jump, and LEA
23 // SIMD/FP: SIMD ALU, FP Adder
25 def AtomItineraries : ProcessorItineraries<
29 // InstrItinData<class, [InstrStage<N, [P0]>] >,
31 // InstrItinData<class, [InstrStage<N, [P0, P1]>] >,
33 // InstrItinData<class, [InstrStage<N, [P0], 0>, InstrStage<N, [P1]>] >,
35 // Default is 1 cycle, port0 or port1
36 InstrItinData<IIC_DEFAULT, [InstrStage<1, [Port0, Port1]>] >,
37 InstrItinData<IIC_ALU_MEM, [InstrStage<1, [Port0]>] >,
38 InstrItinData<IIC_ALU_NONMEM, [InstrStage<1, [Port0, Port1]>] >,
39 InstrItinData<IIC_LEA, [InstrStage<1, [Port1]>] >,
40 InstrItinData<IIC_LEA_16, [InstrStage<2, [Port0, Port1]>] >,
42 InstrItinData<IIC_MUL8, [InstrStage<7, [Port0, Port1]>] >,
43 InstrItinData<IIC_MUL16_MEM, [InstrStage<8, [Port0, Port1]>] >,
44 InstrItinData<IIC_MUL16_REG, [InstrStage<7, [Port0, Port1]>] >,
45 InstrItinData<IIC_MUL32_MEM, [InstrStage<7, [Port0, Port1]>] >,
46 InstrItinData<IIC_MUL32_REG, [InstrStage<6, [Port0, Port1]>] >,
47 InstrItinData<IIC_MUL64, [InstrStage<12, [Port0, Port1]>] >,
48 // imul by al, ax, eax, rax
49 InstrItinData<IIC_IMUL8, [InstrStage<7, [Port0, Port1]>] >,
50 InstrItinData<IIC_IMUL16_MEM, [InstrStage<8, [Port0, Port1]>] >,
51 InstrItinData<IIC_IMUL16_REG, [InstrStage<7, [Port0, Port1]>] >,
52 InstrItinData<IIC_IMUL32_MEM, [InstrStage<7, [Port0, Port1]>] >,
53 InstrItinData<IIC_IMUL32_REG, [InstrStage<6, [Port0, Port1]>] >,
54 InstrItinData<IIC_IMUL64, [InstrStage<12, [Port0, Port1]>] >,
55 // imul reg by reg|mem
56 InstrItinData<IIC_IMUL16_RM, [InstrStage<7, [Port0, Port1]>] >,
57 InstrItinData<IIC_IMUL16_RR, [InstrStage<6, [Port0, Port1]>] >,
58 InstrItinData<IIC_IMUL32_RM, [InstrStage<5, [Port0]>] >,
59 InstrItinData<IIC_IMUL32_RR, [InstrStage<5, [Port0]>] >,
60 InstrItinData<IIC_IMUL64_RM, [InstrStage<12, [Port0, Port1]>] >,
61 InstrItinData<IIC_IMUL64_RR, [InstrStage<12, [Port0, Port1]>] >,
62 // imul reg = reg/mem * imm
63 InstrItinData<IIC_IMUL16_RRI, [InstrStage<6, [Port0, Port1]>] >,
64 InstrItinData<IIC_IMUL32_RRI, [InstrStage<5, [Port0]>] >,
65 InstrItinData<IIC_IMUL64_RRI, [InstrStage<14, [Port0, Port1]>] >,
66 InstrItinData<IIC_IMUL16_RMI, [InstrStage<7, [Port0, Port1]>] >,
67 InstrItinData<IIC_IMUL32_RMI, [InstrStage<5, [Port0]>] >,
68 InstrItinData<IIC_IMUL64_RMI, [InstrStage<14, [Port0, Port1]>] >,
70 InstrItinData<IIC_IDIV8, [InstrStage<62, [Port0, Port1]>] >,
71 InstrItinData<IIC_IDIV16, [InstrStage<62, [Port0, Port1]>] >,
72 InstrItinData<IIC_IDIV32, [InstrStage<62, [Port0, Port1]>] >,
73 InstrItinData<IIC_IDIV64, [InstrStage<130, [Port0, Port1]>] >,
75 InstrItinData<IIC_DIV8_REG, [InstrStage<50, [Port0, Port1]>] >,
76 InstrItinData<IIC_DIV8_MEM, [InstrStage<68, [Port0, Port1]>] >,
77 InstrItinData<IIC_DIV16, [InstrStage<50, [Port0, Port1]>] >,
78 InstrItinData<IIC_DIV32, [InstrStage<50, [Port0, Port1]>] >,
79 InstrItinData<IIC_DIV64, [InstrStage<130, [Port0, Port1]>] >,
81 InstrItinData<IIC_UNARY_REG, [InstrStage<1, [Port0, Port1]>] >,
82 InstrItinData<IIC_UNARY_MEM, [InstrStage<1, [Port0]>] >,
83 // add/sub/and/or/xor/adc/sbc/cmp/test
84 InstrItinData<IIC_BIN_NONMEM, [InstrStage<1, [Port0, Port1]>] >,
85 InstrItinData<IIC_BIN_MEM, [InstrStage<1, [Port0]>] >,
87 InstrItinData<IIC_SR, [InstrStage<1, [Port0]>] >,
89 InstrItinData<IIC_SHD16_REG_IM, [InstrStage<6, [Port0, Port1]>] >,
90 InstrItinData<IIC_SHD16_REG_CL, [InstrStage<6, [Port0, Port1]>] >,
91 InstrItinData<IIC_SHD16_MEM_IM, [InstrStage<6, [Port0, Port1]>] >,
92 InstrItinData<IIC_SHD16_MEM_CL, [InstrStage<6, [Port0, Port1]>] >,
93 InstrItinData<IIC_SHD32_REG_IM, [InstrStage<2, [Port0, Port1]>] >,
94 InstrItinData<IIC_SHD32_REG_CL, [InstrStage<2, [Port0, Port1]>] >,
95 InstrItinData<IIC_SHD32_MEM_IM, [InstrStage<4, [Port0, Port1]>] >,
96 InstrItinData<IIC_SHD32_MEM_CL, [InstrStage<4, [Port0, Port1]>] >,
97 InstrItinData<IIC_SHD64_REG_IM, [InstrStage<9, [Port0, Port1]>] >,
98 InstrItinData<IIC_SHD64_REG_CL, [InstrStage<8, [Port0, Port1]>] >,
99 InstrItinData<IIC_SHD64_MEM_IM, [InstrStage<9, [Port0, Port1]>] >,
100 InstrItinData<IIC_SHD64_MEM_CL, [InstrStage<9, [Port0, Port1]>] >,
102 InstrItinData<IIC_CMOV16_RM, [InstrStage<1, [Port0]>] >,
103 InstrItinData<IIC_CMOV16_RR, [InstrStage<1, [Port0, Port1]>] >,
104 InstrItinData<IIC_CMOV32_RM, [InstrStage<1, [Port0]>] >,
105 InstrItinData<IIC_CMOV32_RR, [InstrStage<1, [Port0, Port1]>] >,
106 InstrItinData<IIC_CMOV64_RM, [InstrStage<1, [Port0]>] >,
107 InstrItinData<IIC_CMOV64_RR, [InstrStage<1, [Port0, Port1]>] >,
109 InstrItinData<IIC_SET_M, [InstrStage<2, [Port0, Port1]>] >,
110 InstrItinData<IIC_SET_R, [InstrStage<1, [Port0, Port1]>] >,
112 InstrItinData<IIC_Jcc, [InstrStage<1, [Port1]>] >,
114 InstrItinData<IIC_JCXZ, [InstrStage<4, [Port0, Port1]>] >,
116 InstrItinData<IIC_JMP_REL, [InstrStage<1, [Port1]>] >,
118 InstrItinData<IIC_JMP_REG, [InstrStage<1, [Port1]>] >,
119 InstrItinData<IIC_JMP_MEM, [InstrStage<2, [Port0, Port1]>] >,
121 InstrItinData<IIC_JMP_FAR_MEM, [InstrStage<32, [Port0, Port1]>] >,
122 InstrItinData<IIC_JMP_FAR_PTR, [InstrStage<31, [Port0, Port1]>] >,
124 InstrItinData<IIC_LOOP, [InstrStage<18, [Port0, Port1]>] >,
125 InstrItinData<IIC_LOOPE, [InstrStage<8, [Port0, Port1]>] >,
126 InstrItinData<IIC_LOOPNE, [InstrStage<17, [Port0, Port1]>] >,
127 // call - all but reg/imm
128 InstrItinData<IIC_CALL_RI, [InstrStage<1, [Port0], 0>, InstrStage<1, [Port1]>] >,
129 InstrItinData<IIC_CALL_MEM, [InstrStage<15, [Port0, Port1]>] >,
130 InstrItinData<IIC_CALL_FAR_MEM, [InstrStage<40, [Port0, Port1]>] >,
131 InstrItinData<IIC_CALL_FAR_PTR, [InstrStage<39, [Port0, Port1]>] >,
133 InstrItinData<IIC_RET, [InstrStage<79, [Port0, Port1]>] >,
134 InstrItinData<IIC_RET_IMM, [InstrStage<1, [Port0], 0>, InstrStage<1, [Port1]>] >