1 //===- X86ScheduleAtom.td - X86 Atom Scheduling Definitions -*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the itinerary class data for the Intel Atom (Bonnell)
13 //===----------------------------------------------------------------------===//
16 // Scheduling information derived from the "Intel 64 and IA32 Architectures
17 // Optimization Reference Manual", Chapter 13, Section 4.
20 def Port0 : FuncUnit; // ALU: ALU0, shift/rotate, load/store
21 // SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide
22 def Port1 : FuncUnit; // ALU: ALU1, bit processing, jump, and LEA
23 // SIMD/FP: SIMD ALU, FP Adder
25 def AtomItineraries : ProcessorItineraries<
29 // InstrItinData<class, [InstrStage<N, [P0]>] >,
31 // InstrItinData<class, [InstrStage<N, [P0, P1]>] >,
33 // InstrItinData<class, [InstrStage<N, [P0], 0>, InstrStage<N, [P1]>] >,
35 // Default is 1 cycle, port0 or port1
36 InstrItinData<IIC_DEFAULT, [InstrStage<1, [Port0, Port1]>] >,
37 InstrItinData<IIC_ALU_MEM, [InstrStage<1, [Port0]>] >,
38 InstrItinData<IIC_ALU_NONMEM, [InstrStage<1, [Port0, Port1]>] >,
39 InstrItinData<IIC_LEA, [InstrStage<1, [Port1]>] >,
40 InstrItinData<IIC_LEA_16, [InstrStage<2, [Port0, Port1]>] >,
42 InstrItinData<IIC_MUL8, [InstrStage<7, [Port0, Port1]>] >,
43 InstrItinData<IIC_MUL16_MEM, [InstrStage<8, [Port0, Port1]>] >,
44 InstrItinData<IIC_MUL16_REG, [InstrStage<7, [Port0, Port1]>] >,
45 InstrItinData<IIC_MUL32_MEM, [InstrStage<7, [Port0, Port1]>] >,
46 InstrItinData<IIC_MUL32_REG, [InstrStage<6, [Port0, Port1]>] >,
47 InstrItinData<IIC_MUL64, [InstrStage<12, [Port0, Port1]>] >,
48 // imul by al, ax, eax, rax
49 InstrItinData<IIC_IMUL8, [InstrStage<7, [Port0, Port1]>] >,
50 InstrItinData<IIC_IMUL16_MEM, [InstrStage<8, [Port0, Port1]>] >,
51 InstrItinData<IIC_IMUL16_REG, [InstrStage<7, [Port0, Port1]>] >,
52 InstrItinData<IIC_IMUL32_MEM, [InstrStage<7, [Port0, Port1]>] >,
53 InstrItinData<IIC_IMUL32_REG, [InstrStage<6, [Port0, Port1]>] >,
54 InstrItinData<IIC_IMUL64, [InstrStage<12, [Port0, Port1]>] >,
55 // imul reg by reg|mem
56 InstrItinData<IIC_IMUL16_RM, [InstrStage<7, [Port0, Port1]>] >,
57 InstrItinData<IIC_IMUL16_RR, [InstrStage<6, [Port0, Port1]>] >,
58 InstrItinData<IIC_IMUL32_RM, [InstrStage<5, [Port0]>] >,
59 InstrItinData<IIC_IMUL32_RR, [InstrStage<5, [Port0]>] >,
60 InstrItinData<IIC_IMUL64_RM, [InstrStage<12, [Port0, Port1]>] >,
61 InstrItinData<IIC_IMUL64_RR, [InstrStage<12, [Port0, Port1]>] >,
62 // imul reg = reg/mem * imm
63 InstrItinData<IIC_IMUL16_RRI, [InstrStage<6, [Port0, Port1]>] >,
64 InstrItinData<IIC_IMUL32_RRI, [InstrStage<5, [Port0]>] >,
65 InstrItinData<IIC_IMUL64_RRI, [InstrStage<14, [Port0, Port1]>] >,
66 InstrItinData<IIC_IMUL16_RMI, [InstrStage<7, [Port0, Port1]>] >,
67 InstrItinData<IIC_IMUL32_RMI, [InstrStage<5, [Port0]>] >,
68 InstrItinData<IIC_IMUL64_RMI, [InstrStage<14, [Port0, Port1]>] >,
70 InstrItinData<IIC_IDIV8, [InstrStage<62, [Port0, Port1]>] >,
71 InstrItinData<IIC_IDIV16, [InstrStage<62, [Port0, Port1]>] >,
72 InstrItinData<IIC_IDIV32, [InstrStage<62, [Port0, Port1]>] >,
73 InstrItinData<IIC_IDIV64, [InstrStage<130, [Port0, Port1]>] >,
75 InstrItinData<IIC_DIV8_REG, [InstrStage<50, [Port0, Port1]>] >,
76 InstrItinData<IIC_DIV8_MEM, [InstrStage<68, [Port0, Port1]>] >,
77 InstrItinData<IIC_DIV16, [InstrStage<50, [Port0, Port1]>] >,
78 InstrItinData<IIC_DIV32, [InstrStage<50, [Port0, Port1]>] >,
79 InstrItinData<IIC_DIV64, [InstrStage<130, [Port0, Port1]>] >,
81 InstrItinData<IIC_UNARY_REG, [InstrStage<1, [Port0, Port1]>] >,
82 InstrItinData<IIC_UNARY_MEM, [InstrStage<1, [Port0]>] >,
83 // add/sub/and/or/xor/adc/sbc/cmp/test
84 InstrItinData<IIC_BIN_NONMEM, [InstrStage<1, [Port0, Port1]>] >,
85 InstrItinData<IIC_BIN_MEM, [InstrStage<1, [Port0]>] >,
87 InstrItinData<IIC_SR, [InstrStage<1, [Port0]>] >,
89 InstrItinData<IIC_SHD16_REG_IM, [InstrStage<6, [Port0, Port1]>] >,
90 InstrItinData<IIC_SHD16_REG_CL, [InstrStage<6, [Port0, Port1]>] >,
91 InstrItinData<IIC_SHD16_MEM_IM, [InstrStage<6, [Port0, Port1]>] >,
92 InstrItinData<IIC_SHD16_MEM_CL, [InstrStage<6, [Port0, Port1]>] >,
93 InstrItinData<IIC_SHD32_REG_IM, [InstrStage<2, [Port0, Port1]>] >,
94 InstrItinData<IIC_SHD32_REG_CL, [InstrStage<2, [Port0, Port1]>] >,
95 InstrItinData<IIC_SHD32_MEM_IM, [InstrStage<4, [Port0, Port1]>] >,
96 InstrItinData<IIC_SHD32_MEM_CL, [InstrStage<4, [Port0, Port1]>] >,
97 InstrItinData<IIC_SHD64_REG_IM, [InstrStage<9, [Port0, Port1]>] >,
98 InstrItinData<IIC_SHD64_REG_CL, [InstrStage<8, [Port0, Port1]>] >,
99 InstrItinData<IIC_SHD64_MEM_IM, [InstrStage<9, [Port0, Port1]>] >,
100 InstrItinData<IIC_SHD64_MEM_CL, [InstrStage<9, [Port0, Port1]>] >,
102 InstrItinData<IIC_CMOV16_RM, [InstrStage<1, [Port0]>] >,
103 InstrItinData<IIC_CMOV16_RR, [InstrStage<1, [Port0, Port1]>] >,
104 InstrItinData<IIC_CMOV32_RM, [InstrStage<1, [Port0]>] >,
105 InstrItinData<IIC_CMOV32_RR, [InstrStage<1, [Port0, Port1]>] >,
106 InstrItinData<IIC_CMOV64_RM, [InstrStage<1, [Port0]>] >,
107 InstrItinData<IIC_CMOV64_RR, [InstrStage<1, [Port0, Port1]>] >,
109 InstrItinData<IIC_SET_M, [InstrStage<2, [Port0, Port1]>] >,
110 InstrItinData<IIC_SET_R, [InstrStage<1, [Port0, Port1]>] >,
112 InstrItinData<IIC_Jcc, [InstrStage<1, [Port1]>] >,
114 InstrItinData<IIC_JCXZ, [InstrStage<4, [Port0, Port1]>] >,
116 InstrItinData<IIC_JMP_REL, [InstrStage<1, [Port1]>] >,
118 InstrItinData<IIC_JMP_REG, [InstrStage<1, [Port1]>] >,
119 InstrItinData<IIC_JMP_MEM, [InstrStage<2, [Port0, Port1]>] >,
121 InstrItinData<IIC_JMP_FAR_MEM, [InstrStage<32, [Port0, Port1]>] >,
122 InstrItinData<IIC_JMP_FAR_PTR, [InstrStage<31, [Port0, Port1]>] >,
124 InstrItinData<IIC_LOOP, [InstrStage<18, [Port0, Port1]>] >,
125 InstrItinData<IIC_LOOPE, [InstrStage<8, [Port0, Port1]>] >,
126 InstrItinData<IIC_LOOPNE, [InstrStage<17, [Port0, Port1]>] >,
127 // call - all but reg/imm
128 InstrItinData<IIC_CALL_RI, [InstrStage<1, [Port0], 0>,
129 InstrStage<1, [Port1]>] >,
130 InstrItinData<IIC_CALL_MEM, [InstrStage<15, [Port0, Port1]>] >,
131 InstrItinData<IIC_CALL_FAR_MEM, [InstrStage<40, [Port0, Port1]>] >,
132 InstrItinData<IIC_CALL_FAR_PTR, [InstrStage<39, [Port0, Port1]>] >,
134 InstrItinData<IIC_RET, [InstrStage<79, [Port0, Port1]>] >,
135 InstrItinData<IIC_RET_IMM, [InstrStage<1, [Port0], 0>, InstrStage<1, [Port1]>] >,
136 //sign extension movs
137 InstrItinData<IIC_MOVSX,[InstrStage<1, [Port0] >] >,
138 InstrItinData<IIC_MOVSX_R16_R8, [InstrStage<2, [Port0, Port1]>] >,
139 InstrItinData<IIC_MOVSX_R16_M8, [InstrStage<3, [Port0, Port1]>] >,
140 InstrItinData<IIC_MOVSX_R16_R16, [InstrStage<1, [Port0, Port1]>] >,
141 InstrItinData<IIC_MOVSX_R32_R32, [InstrStage<1, [Port0, Port1]>] >,
142 //zero extension movs
143 InstrItinData<IIC_MOVZX,[InstrStage<1, [Port0]>] >,
144 InstrItinData<IIC_MOVZX_R16_R8, [InstrStage<2, [Port0, Port1]>] >,
145 InstrItinData<IIC_MOVZX_R16_M8, [InstrStage<3, [Port0, Port1]>] >,
147 // SSE binary operations
148 // arithmetic fp scalar
149 InstrItinData<IIC_SSE_ALU_F32S_RR, [InstrStage<5, [Port1]>] >,
150 InstrItinData<IIC_SSE_ALU_F32S_RM, [InstrStage<5, [Port0], 0>,
151 InstrStage<5, [Port1]>] >,
152 InstrItinData<IIC_SSE_ALU_F64S_RR, [InstrStage<5, [Port1]>] >,
153 InstrItinData<IIC_SSE_ALU_F64S_RM, [InstrStage<5, [Port0], 0>,
154 InstrStage<5, [Port1]>] >,
155 InstrItinData<IIC_SSE_MUL_F32S_RR, [InstrStage<4, [Port0]>] >,
156 InstrItinData<IIC_SSE_MUL_F32S_RM, [InstrStage<4, [Port0]>] >,
157 InstrItinData<IIC_SSE_MUL_F64S_RR, [InstrStage<5, [Port0]>] >,
158 InstrItinData<IIC_SSE_MUL_F64S_RM, [InstrStage<5, [Port0]>] >,
159 InstrItinData<IIC_SSE_DIV_F32S_RR, [InstrStage<34, [Port0, Port1]>] >,
160 InstrItinData<IIC_SSE_DIV_F32S_RM, [InstrStage<34, [Port0, Port1]>] >,
161 InstrItinData<IIC_SSE_DIV_F64S_RR, [InstrStage<62, [Port0, Port1]>] >,
162 InstrItinData<IIC_SSE_DIV_F64S_RM, [InstrStage<62, [Port0, Port1]>] >,
164 InstrItinData<IIC_SSE_COMIS_RR, [InstrStage<9, [Port0, Port1]>] >,
165 InstrItinData<IIC_SSE_COMIS_RM, [InstrStage<10, [Port0, Port1]>] >,
167 InstrItinData<IIC_SSE_HADDSUB_RR, [InstrStage<8, [Port0, Port1]>] >,
168 InstrItinData<IIC_SSE_HADDSUB_RM, [InstrStage<9, [Port0, Port1]>] >,
170 // arithmetic fp parallel
171 InstrItinData<IIC_SSE_ALU_F32P_RR, [InstrStage<5, [Port1]>] >,
172 InstrItinData<IIC_SSE_ALU_F32P_RM, [InstrStage<5, [Port0], 0>,
173 InstrStage<5, [Port1]>] >,
174 InstrItinData<IIC_SSE_ALU_F64P_RR, [InstrStage<6, [Port0, Port1]>] >,
175 InstrItinData<IIC_SSE_ALU_F64P_RM, [InstrStage<7, [Port0, Port1]>] >,
176 InstrItinData<IIC_SSE_MUL_F32P_RR, [InstrStage<5, [Port0]>] >,
177 InstrItinData<IIC_SSE_MUL_F32P_RM, [InstrStage<5, [Port0]>] >,
178 InstrItinData<IIC_SSE_MUL_F64P_RR, [InstrStage<9, [Port0, Port1]>] >,
179 InstrItinData<IIC_SSE_MUL_F64P_RM, [InstrStage<10, [Port0, Port1]>] >,
180 InstrItinData<IIC_SSE_DIV_F32P_RR, [InstrStage<70, [Port0, Port1]>] >,
181 InstrItinData<IIC_SSE_DIV_F32P_RM, [InstrStage<70, [Port0, Port1]>] >,
182 InstrItinData<IIC_SSE_DIV_F64P_RR, [InstrStage<125, [Port0, Port1]>] >,
183 InstrItinData<IIC_SSE_DIV_F64P_RM, [InstrStage<125, [Port0, Port1]>] >,
186 InstrItinData<IIC_SSE_BIT_P_RR, [InstrStage<1, [Port0, Port1]>] >,
187 InstrItinData<IIC_SSE_BIT_P_RM, [InstrStage<1, [Port0]>] >,
189 // arithmetic int parallel
190 InstrItinData<IIC_SSE_INTALU_P_RR, [InstrStage<1, [Port0, Port1]>] >,
191 InstrItinData<IIC_SSE_INTALU_P_RM, [InstrStage<1, [Port0]>] >,
192 InstrItinData<IIC_SSE_INTALUQ_P_RR, [InstrStage<2, [Port0, Port1]>] >,
193 InstrItinData<IIC_SSE_INTALUQ_P_RM, [InstrStage<3, [Port0, Port1]>] >,
195 // multiply int parallel
196 InstrItinData<IIC_SSE_INTMUL_P_RR, [InstrStage<5, [Port0]>] >,
197 InstrItinData<IIC_SSE_INTMUL_P_RM, [InstrStage<5, [Port0]>] >,
200 InstrItinData<IIC_SSE_INTSH_P_RR, [InstrStage<2, [Port0, Port1]>] >,
201 InstrItinData<IIC_SSE_INTSH_P_RM, [InstrStage<3, [Port0, Port1]>] >,
202 InstrItinData<IIC_SSE_INTSH_P_RI, [InstrStage<1, [Port0, Port1]>] >,
204 InstrItinData<IIC_SSE_CMPP_RR, [InstrStage<6, [Port0, Port1]>] >,
205 InstrItinData<IIC_SSE_CMPP_RM, [InstrStage<7, [Port0, Port1]>] >,
207 InstrItinData<IIC_SSE_SHUFP, [InstrStage<1, [Port0]>] >,
208 InstrItinData<IIC_SSE_PSHUF, [InstrStage<1, [Port0]>] >,
210 InstrItinData<IIC_SSE_UNPCK, [InstrStage<1, [Port0]>] >,
212 InstrItinData<IIC_SSE_SQRTP_RR, [InstrStage<13, [Port0, Port1]>] >,
213 InstrItinData<IIC_SSE_SQRTP_RM, [InstrStage<14, [Port0, Port1]>] >,
214 InstrItinData<IIC_SSE_SQRTS_RR, [InstrStage<11, [Port0, Port1]>] >,
215 InstrItinData<IIC_SSE_SQRTS_RM, [InstrStage<12, [Port0, Port1]>] >,
217 InstrItinData<IIC_SSE_RCPP_RR, [InstrStage<9, [Port0, Port1]>] >,
218 InstrItinData<IIC_SSE_RCPP_RM, [InstrStage<10, [Port0, Port1]>] >,
219 InstrItinData<IIC_SSE_RCPS_RR, [InstrStage<4, [Port0]>] >,
220 InstrItinData<IIC_SSE_RCPS_RM, [InstrStage<4, [Port0]>] >,
222 InstrItinData<IIC_SSE_MOVMSK, [InstrStage<3, [Port0]>] >,
223 InstrItinData<IIC_SSE_MASKMOV, [InstrStage<2, [Port0, Port1]>] >,
225 InstrItinData<IIC_SSE_PEXTRW, [InstrStage<4, [Port0, Port1]>] >,
226 InstrItinData<IIC_SSE_PINSRW, [InstrStage<1, [Port0]>] >,
228 InstrItinData<IIC_SSE_PABS_RR, [InstrStage<1, [Port0, Port1]>] >,
229 InstrItinData<IIC_SSE_PABS_RM, [InstrStage<1, [Port0]>] >,
231 InstrItinData<IIC_SSE_MOV_S_RR, [InstrStage<1, [Port0, Port1]>] >,
232 InstrItinData<IIC_SSE_MOV_S_RM, [InstrStage<1, [Port0]>] >,
233 InstrItinData<IIC_SSE_MOV_S_MR, [InstrStage<1, [Port0]>] >,
235 InstrItinData<IIC_SSE_MOVA_P_RR, [InstrStage<1, [Port0, Port1]>] >,
236 InstrItinData<IIC_SSE_MOVA_P_RM, [InstrStage<1, [Port0]>] >,
237 InstrItinData<IIC_SSE_MOVA_P_MR, [InstrStage<1, [Port0]>] >,
239 InstrItinData<IIC_SSE_MOVU_P_RR, [InstrStage<1, [Port0, Port1]>] >,
240 InstrItinData<IIC_SSE_MOVU_P_RM, [InstrStage<3, [Port0, Port1]>] >,
241 InstrItinData<IIC_SSE_MOVU_P_MR, [InstrStage<2, [Port0, Port1]>] >,
243 InstrItinData<IIC_SSE_MOV_LH, [InstrStage<1, [Port0]>] >,
245 InstrItinData<IIC_SSE_LDDQU, [InstrStage<3, [Port0, Port1]>] >,
247 InstrItinData<IIC_SSE_MOVDQ, [InstrStage<1, [Port0]>] >,
248 InstrItinData<IIC_SSE_MOVD_ToGP, [InstrStage<3, [Port0]>] >,
249 InstrItinData<IIC_SSE_MOVQ_RR, [InstrStage<1, [Port0, Port1]>] >,
251 InstrItinData<IIC_SSE_MOVNT, [InstrStage<1, [Port0]>] >,
253 InstrItinData<IIC_SSE_PREFETCH, [InstrStage<1, [Port0]>] >,
254 InstrItinData<IIC_SSE_PAUSE, [InstrStage<17, [Port0, Port1]>] >,
255 InstrItinData<IIC_SSE_LFENCE, [InstrStage<1, [Port0, Port1]>] >,
256 InstrItinData<IIC_SSE_MFENCE, [InstrStage<1, [Port0]>] >,
257 InstrItinData<IIC_SSE_SFENCE, [InstrStage<1, [Port0]>] >,
258 InstrItinData<IIC_SSE_LDMXCSR, [InstrStage<5, [Port0, Port1]>] >,
259 InstrItinData<IIC_SSE_STMXCSR, [InstrStage<15, [Port0, Port1]>] >,
261 InstrItinData<IIC_SSE_PHADDSUBD_RR, [InstrStage<3, [Port0, Port1]>] >,
262 InstrItinData<IIC_SSE_PHADDSUBD_RM, [InstrStage<4, [Port0, Port1]>] >,
263 InstrItinData<IIC_SSE_PHADDSUBSW_RR, [InstrStage<7, [Port0, Port1]>] >,
264 InstrItinData<IIC_SSE_PHADDSUBSW_RM, [InstrStage<8, [Port0, Port1]>] >,
265 InstrItinData<IIC_SSE_PHADDSUBW_RR, [InstrStage<7, [Port0, Port1]>] >,
266 InstrItinData<IIC_SSE_PHADDSUBW_RM, [InstrStage<8, [Port0, Port1]>] >,
267 InstrItinData<IIC_SSE_PSHUFB_RR, [InstrStage<4, [Port0, Port1]>] >,
268 InstrItinData<IIC_SSE_PSHUFB_RM, [InstrStage<5, [Port0, Port1]>] >,
269 InstrItinData<IIC_SSE_PSIGN_RR, [InstrStage<1, [Port0, Port1]>] >,
270 InstrItinData<IIC_SSE_PSIGN_RM, [InstrStage<1, [Port0]>] >,
272 InstrItinData<IIC_SSE_PMADD, [InstrStage<5, [Port0]>] >,
273 InstrItinData<IIC_SSE_PMULHRSW, [InstrStage<5, [Port0]>] >,
274 InstrItinData<IIC_SSE_PALIGNR, [InstrStage<1, [Port0]>] >,
275 InstrItinData<IIC_SSE_MWAIT, [InstrStage<46, [Port0, Port1]>] >,
276 InstrItinData<IIC_SSE_MONITOR, [InstrStage<45, [Port0, Port1]>] >,
280 InstrItinData<IIC_SSE_CVT_PD_RR, [InstrStage<7, [Port0, Port1]>] >,
281 InstrItinData<IIC_SSE_CVT_PD_RM, [InstrStage<8, [Port0, Port1]>] >,
282 // to/from PS except to/from PD and PS2PI
283 InstrItinData<IIC_SSE_CVT_PS_RR, [InstrStage<6, [Port0, Port1]>] >,
284 InstrItinData<IIC_SSE_CVT_PS_RM, [InstrStage<7, [Port0, Port1]>] >,
285 InstrItinData<IIC_SSE_CVT_Scalar_RR, [InstrStage<6, [Port0, Port1]>] >,
286 InstrItinData<IIC_SSE_CVT_Scalar_RM, [InstrStage<7, [Port0, Port1]>] >,
287 InstrItinData<IIC_SSE_CVT_SS2SI32_RR, [InstrStage<8, [Port0, Port1]>] >,
288 InstrItinData<IIC_SSE_CVT_SS2SI32_RM, [InstrStage<9, [Port0, Port1]>] >,
289 InstrItinData<IIC_SSE_CVT_SS2SI64_RR, [InstrStage<9, [Port0, Port1]>] >,
290 InstrItinData<IIC_SSE_CVT_SS2SI64_RM, [InstrStage<10, [Port0, Port1]>] >,
291 InstrItinData<IIC_SSE_CVT_SD2SI_RR, [InstrStage<8, [Port0, Port1]>] >,
292 InstrItinData<IIC_SSE_CVT_SD2SI_RM, [InstrStage<9, [Port0, Port1]>] >