1 //=- X86ScheduleSLM.td - X86 Silvermont Scheduling -----------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the machine model for Intel Silvermont to support
11 // instruction scheduling and other instruction cost heuristics.
13 //===----------------------------------------------------------------------===//
15 def SLMModel : SchedMachineModel {
16 // All x86 instructions are modeled as a single micro-op, and SLM can decode 2
17 // instructions per cycle.
19 let MicroOpBufferSize = 32; // Based on the reorder buffer.
21 let MispredictPenalty = 10;
23 // FIXME: SSE4 is unimplemented. This flag is set to allow
24 // the scheduler to assign a default model to unrecognized opcodes.
25 let CompleteModel = 0;
28 let SchedModel = SLMModel in {
30 // Silvermont has 5 reservation stations for micro-ops
32 def IEC_RSV0 : ProcResource<1>;
33 def IEC_RSV1 : ProcResource<1>;
34 def FPC_RSV0 : ProcResource<1> { let BufferSize = 1; }
35 def FPC_RSV1 : ProcResource<1> { let BufferSize = 1; }
36 def MEC_RSV : ProcResource<1>;
38 // Many micro-ops are capable of issuing on multiple ports.
39 def IEC_RSV01 : ProcResGroup<[IEC_RSV0, IEC_RSV1]>;
40 def FPC_RSV01 : ProcResGroup<[FPC_RSV0, FPC_RSV1]>;
42 def SMDivider : ProcResource<1>;
43 def SMFPMultiplier : ProcResource<1>;
44 def SMFPDivider : ProcResource<1>;
46 // Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3
47 // cycles after the memory operand.
48 def : ReadAdvance<ReadAfterLd, 3>;
50 // Many SchedWrites are defined in pairs with and without a folded load.
51 // Instructions with folded loads are usually micro-fused, so they only appear
52 // as two micro-ops when queued in the reservation station.
53 // This multiclass defines the resource usage for variants with and without
55 multiclass SMWriteResPair<X86FoldableSchedWrite SchedRW,
56 ProcResourceKind ExePort,
58 // Register variant is using a single cycle on ExePort.
59 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
61 // Memory variant also uses a cycle on MEC_RSV and adds 3 cycles to the
63 def : WriteRes<SchedRW.Folded, [MEC_RSV, ExePort]> {
64 let Latency = !add(Lat, 3);
68 // A folded store needs a cycle on MEC_RSV for the store data, but it does not
69 // need an extra port cycle to recompute the address.
70 def : WriteRes<WriteRMW, [MEC_RSV]>;
72 def : WriteRes<WriteStore, [IEC_RSV01, MEC_RSV]>;
73 def : WriteRes<WriteLoad, [MEC_RSV]> { let Latency = 3; }
74 def : WriteRes<WriteMove, [IEC_RSV01]>;
75 def : WriteRes<WriteZero, []>;
77 defm : SMWriteResPair<WriteALU, IEC_RSV01, 1>;
78 defm : SMWriteResPair<WriteIMul, IEC_RSV1, 3>;
79 defm : SMWriteResPair<WriteShift, IEC_RSV0, 1>;
80 defm : SMWriteResPair<WriteJump, IEC_RSV1, 1>;
82 // This is for simple LEAs with one or two input operands.
83 // The complex ones can only execute on port 1, and they require two cycles on
84 // the port to read all inputs. We don't model that.
85 def : WriteRes<WriteLEA, [IEC_RSV1]>;
87 // This is quite rough, latency depends on the dividend.
88 def : WriteRes<WriteIDiv, [IEC_RSV01, SMDivider]> {
90 let ResourceCycles = [1, 25];
92 def : WriteRes<WriteIDivLd, [MEC_RSV, IEC_RSV01, SMDivider]> {
94 let ResourceCycles = [1, 1, 25];
97 // Scalar and vector floating point.
98 defm : SMWriteResPair<WriteFAdd, FPC_RSV1, 3>;
99 defm : SMWriteResPair<WriteFRcp, FPC_RSV0, 5>;
100 defm : SMWriteResPair<WriteFSqrt, FPC_RSV0, 15>;
101 defm : SMWriteResPair<WriteCvtF2I, FPC_RSV01, 4>;
102 defm : SMWriteResPair<WriteCvtI2F, FPC_RSV01, 4>;
103 defm : SMWriteResPair<WriteCvtF2F, FPC_RSV01, 4>;
104 defm : SMWriteResPair<WriteFShuffle, FPC_RSV0, 1>;
105 defm : SMWriteResPair<WriteFBlend, FPC_RSV0, 1>;
107 // This is quite rough, latency depends on precision
108 def : WriteRes<WriteFMul, [FPC_RSV0, SMFPMultiplier]> {
110 let ResourceCycles = [1, 2];
112 def : WriteRes<WriteFMulLd, [MEC_RSV, FPC_RSV0, SMFPMultiplier]> {
114 let ResourceCycles = [1, 1, 2];
117 def : WriteRes<WriteFDiv, [FPC_RSV0, SMFPDivider]> {
119 let ResourceCycles = [1, 34];
121 def : WriteRes<WriteFDivLd, [MEC_RSV, FPC_RSV0, SMFPDivider]> {
123 let ResourceCycles = [1, 1, 34];
126 // Vector integer operations.
127 defm : SMWriteResPair<WriteVecShift, FPC_RSV0, 1>;
128 defm : SMWriteResPair<WriteVecLogic, FPC_RSV01, 1>;
129 defm : SMWriteResPair<WriteVecALU, FPC_RSV01, 1>;
130 defm : SMWriteResPair<WriteVecIMul, FPC_RSV0, 4>;
131 defm : SMWriteResPair<WriteShuffle, FPC_RSV0, 1>;
132 defm : SMWriteResPair<WriteBlend, FPC_RSV0, 1>;
133 defm : SMWriteResPair<WriteMPSAD, FPC_RSV0, 7>;
135 // String instructions.
136 // Packed Compare Implicit Length Strings, Return Mask
137 def : WriteRes<WritePCmpIStrM, [FPC_RSV0]> {
139 let ResourceCycles = [13];
141 def : WriteRes<WritePCmpIStrMLd, [FPC_RSV0, MEC_RSV]> {
143 let ResourceCycles = [13, 1];
146 // Packed Compare Explicit Length Strings, Return Mask
147 def : WriteRes<WritePCmpEStrM, [FPC_RSV0]> {
149 let ResourceCycles = [17];
151 def : WriteRes<WritePCmpEStrMLd, [FPC_RSV0, MEC_RSV]> {
153 let ResourceCycles = [17, 1];
156 // Packed Compare Implicit Length Strings, Return Index
157 def : WriteRes<WritePCmpIStrI, [FPC_RSV0]> {
159 let ResourceCycles = [17];
161 def : WriteRes<WritePCmpIStrILd, [FPC_RSV0, MEC_RSV]> {
163 let ResourceCycles = [17, 1];
166 // Packed Compare Explicit Length Strings, Return Index
167 def : WriteRes<WritePCmpEStrI, [FPC_RSV0]> {
169 let ResourceCycles = [21];
171 def : WriteRes<WritePCmpEStrILd, [FPC_RSV0, MEC_RSV]> {
173 let ResourceCycles = [21, 1];
177 def : WriteRes<WriteAESDecEnc, [FPC_RSV0]> {
179 let ResourceCycles = [5];
181 def : WriteRes<WriteAESDecEncLd, [FPC_RSV0, MEC_RSV]> {
183 let ResourceCycles = [5, 1];
186 def : WriteRes<WriteAESIMC, [FPC_RSV0]> {
188 let ResourceCycles = [5];
190 def : WriteRes<WriteAESIMCLd, [FPC_RSV0, MEC_RSV]> {
192 let ResourceCycles = [5, 1];
195 def : WriteRes<WriteAESKeyGen, [FPC_RSV0]> {
197 let ResourceCycles = [5];
199 def : WriteRes<WriteAESKeyGenLd, [FPC_RSV0, MEC_RSV]> {
201 let ResourceCycles = [5, 1];
204 // Carry-less multiplication instructions.
205 def : WriteRes<WriteCLMul, [FPC_RSV0]> {
207 let ResourceCycles = [10];
209 def : WriteRes<WriteCLMulLd, [FPC_RSV0, MEC_RSV]> {
211 let ResourceCycles = [10, 1];
215 def : WriteRes<WriteSystem, [FPC_RSV0]> { let Latency = 100; }
216 def : WriteRes<WriteMicrocoded, [FPC_RSV0]> { let Latency = 100; }
217 def : WriteRes<WriteFence, [MEC_RSV]>;
218 def : WriteRes<WriteNop, []>;
220 // AVX is not supported on that architecture, but we should define the basic
221 // scheduling resources anyway.
222 def : WriteRes<WriteIMulH, [FPC_RSV0]>;
223 defm : SMWriteResPair<WriteVarBlend, FPC_RSV0, 1>;
224 defm : SMWriteResPair<WriteFVarBlend, FPC_RSV0, 1>;
225 defm : SMWriteResPair<WriteFShuffle256, FPC_RSV0, 1>;
226 defm : SMWriteResPair<WriteShuffle256, FPC_RSV0, 1>;
227 defm : SMWriteResPair<WriteVarVecShift, FPC_RSV0, 1>;