1 //===-- X86Subtarget.cpp - X86 Subtarget Information ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86 specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "subtarget"
15 #include "X86Subtarget.h"
16 #include "X86InstrInfo.h"
17 #include "X86GenSubtarget.inc"
18 #include "llvm/GlobalValue.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/raw_ostream.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Target/TargetOptions.h"
29 /// ClassifyGlobalReference - Classify a global variable reference for the
30 /// current subtarget according to how we should reference it in a non-pcrel
32 unsigned char X86Subtarget::
33 ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
34 // DLLImport only exists on windows, it is implemented as a load from a
36 if (GV->hasDLLImportLinkage())
37 return X86II::MO_DLLIMPORT;
39 // GV with ghost linkage (in JIT lazy compilation mode) do not require an
40 // extra load from stub.
41 bool isDecl = GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode();
43 // X86-64 in PIC mode.
44 if (isPICStyleRIPRel()) {
45 // Large model never uses stubs.
46 if (TM.getCodeModel() == CodeModel::Large)
47 return X86II::MO_NO_FLAG;
49 if (isTargetDarwin()) {
50 // If symbol visibility is hidden, the extra load is not needed if
51 // target is x86-64 or the symbol is definitely defined in the current
53 if (GV->hasDefaultVisibility() &&
54 (isDecl || GV->isWeakForLinker()))
55 return X86II::MO_GOTPCREL;
57 assert(isTargetELF() && "Unknown rip-relative target");
59 // Extra load is needed for all externally visible.
60 if (!GV->hasLocalLinkage() && GV->hasDefaultVisibility())
61 return X86II::MO_GOTPCREL;
64 return X86II::MO_NO_FLAG;
67 if (isPICStyleGOT()) { // 32-bit ELF targets.
68 // Extra load is needed for all externally visible.
69 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
70 return X86II::MO_GOTOFF;
74 if (isPICStyleStubPIC()) { // Darwin/32 in PIC mode.
75 // Determine whether we have a stub reference and/or whether the reference
76 // is relative to the PIC base or not.
78 // If this is a strong reference to a definition, it is definitely not
80 if (!isDecl && !GV->isWeakForLinker())
81 return X86II::MO_PIC_BASE_OFFSET;
83 // Unless we have a symbol with hidden visibility, we have to go through a
84 // normal $non_lazy_ptr stub because this symbol might be resolved late.
85 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
86 return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
88 // If symbol visibility is hidden, we have a stub for common symbol
89 // references and external declarations.
90 if (isDecl || GV->hasCommonLinkage()) {
91 // Hidden $non_lazy_ptr reference.
92 return X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE;
95 // Otherwise, no stub.
96 return X86II::MO_PIC_BASE_OFFSET;
99 if (isPICStyleStubNoDynamic()) { // Darwin/32 in -mdynamic-no-pic mode.
100 // Determine whether we have a stub reference.
102 // If this is a strong reference to a definition, it is definitely not
104 if (!isDecl && !GV->isWeakForLinker())
105 return X86II::MO_NO_FLAG;
107 // Unless we have a symbol with hidden visibility, we have to go through a
108 // normal $non_lazy_ptr stub because this symbol might be resolved late.
109 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
110 return X86II::MO_DARWIN_NONLAZY;
112 // If symbol visibility is hidden, we have a stub for common symbol
113 // references and external declarations.
114 if (isDecl || GV->hasCommonLinkage()) {
115 // Hidden $non_lazy_ptr reference.
116 return X86II::MO_DARWIN_HIDDEN_NONLAZY;
119 // Otherwise, no stub.
120 return X86II::MO_NO_FLAG;
123 // Direct static reference to global.
124 return X86II::MO_NO_FLAG;
128 /// getBZeroEntry - This function returns the name of a function which has an
129 /// interface like the non-standard bzero function, if such a function exists on
130 /// the current subtarget and it is considered prefereable over memset with zero
131 /// passed as the second argument. Otherwise it returns null.
132 const char *X86Subtarget::getBZeroEntry() const {
133 // Darwin 10 has a __bzero entry point for this purpose.
134 if (getDarwinVers() >= 10)
140 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
141 /// to immediate address.
142 bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
145 return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
148 /// getSpecialAddressLatency - For targets where it is beneficial to
149 /// backschedule instructions that compute addresses, return a value
150 /// indicating the number of scheduling cycles of backscheduling that
151 /// should be attempted.
152 unsigned X86Subtarget::getSpecialAddressLatency() const {
153 // For x86 out-of-order targets, back-schedule address computations so
154 // that loads and stores aren't blocked.
155 // This value was chosen arbitrarily.
159 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
160 /// specified arguments. If we can't run cpuid on the host, return true.
161 bool X86::GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
162 unsigned *rECX, unsigned *rEDX) {
163 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
164 #if defined(__GNUC__)
165 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
166 asm ("movq\t%%rbx, %%rsi\n\t"
168 "xchgq\t%%rbx, %%rsi\n\t"
175 #elif defined(_MSC_VER)
177 __cpuid(registers, value);
178 *rEAX = registers[0];
179 *rEBX = registers[1];
180 *rECX = registers[2];
181 *rEDX = registers[3];
184 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
185 #if defined(__GNUC__)
186 asm ("movl\t%%ebx, %%esi\n\t"
188 "xchgl\t%%ebx, %%esi\n\t"
195 #elif defined(_MSC_VER)
200 mov dword ptr [esi],eax
202 mov dword ptr [esi],ebx
204 mov dword ptr [esi],ecx
206 mov dword ptr [esi],edx
214 static void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model) {
215 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
216 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
217 if (Family == 6 || Family == 0xf) {
219 // Examine extended family ID if family ID is F.
220 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
221 // Examine extended model ID if family ID is 6 or F.
222 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
226 void X86Subtarget::AutoDetectSubtargetFeatures() {
227 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
233 if (X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
236 X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
238 if ((EDX >> 15) & 1) HasCMov = true;
239 if ((EDX >> 23) & 1) X86SSELevel = MMX;
240 if ((EDX >> 25) & 1) X86SSELevel = SSE1;
241 if ((EDX >> 26) & 1) X86SSELevel = SSE2;
242 if (ECX & 0x1) X86SSELevel = SSE3;
243 if ((ECX >> 9) & 1) X86SSELevel = SSSE3;
244 if ((ECX >> 19) & 1) X86SSELevel = SSE41;
245 if ((ECX >> 20) & 1) X86SSELevel = SSE42;
247 bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
248 bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
250 HasFMA3 = IsIntel && ((ECX >> 12) & 0x1);
251 HasAVX = ((ECX >> 28) & 0x1);
253 if (IsIntel || IsAMD) {
254 // Determine if bit test memory instructions are slow.
257 DetectFamilyModel(EAX, Family, Model);
258 IsBTMemSlow = IsAMD || (Family == 6 && Model >= 13);
260 X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
261 HasX86_64 = (EDX >> 29) & 0x1;
262 HasSSE4A = IsAMD && ((ECX >> 6) & 0x1);
263 HasFMA4 = IsAMD && ((ECX >> 16) & 0x1);
267 static const char *GetCurrentX86CPU() {
268 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
269 if (X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
273 DetectFamilyModel(EAX, Family, Model);
275 X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
276 bool Em64T = (EDX >> 29) & 0x1;
277 bool HasSSE3 = (ECX & 0x1);
284 X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
285 if (memcmp(text.c, "GenuineIntel", 12) == 0) {
293 case 4: return "pentium-mmx";
294 default: return "pentium";
298 case 1: return "pentiumpro";
301 case 6: return "pentium2";
305 case 11: return "pentium3";
307 case 13: return "pentium-m";
308 case 14: return "yonah";
310 case 22: // Celeron M 540
312 case 23: // 45nm: Penryn , Wolfdale, Yorkfield (XE)
314 default: return "i686";
320 case 6: // same as 4, but 65nm
321 return (Em64T) ? "nocona" : "prescott";
327 return (Em64T) ? "x86-64" : "pentium4";
334 } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
335 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
336 // appears to be no way to generate the wide variety of AMD-specific targets
337 // from the information returned from CPUID.
345 case 8: return "k6-2";
347 case 13: return "k6-3";
348 default: return "pentium";
352 case 4: return "athlon-tbird";
355 case 8: return "athlon-mp";
356 case 10: return "athlon-xp";
357 default: return "athlon";
364 case 1: return "opteron";
365 case 5: return "athlon-fx"; // also opteron
366 default: return "athlon64";
379 X86Subtarget::X86Subtarget(const std::string &TT, const std::string &FS,
381 : PICStyle(PICStyles::None)
382 , X86SSELevel(NoMMXSSE)
383 , X863DNowLevel(NoThreeDNow)
394 // FIXME: this is a known good value for Yonah. How about others?
395 , MaxInlineSizeThreshold(128)
397 , TargetType(isELF) { // Default to ELF unless otherwise specified.
399 // default to hard float ABI
400 if (FloatABIType == FloatABI::Default)
401 FloatABIType = FloatABI::Hard;
403 // Determine default and user specified characteristics
405 // If feature string is not empty, parse features string.
406 std::string CPU = GetCurrentX86CPU();
407 ParseSubtargetFeatures(FS, CPU);
408 // All X86-64 CPUs also have SSE2, however user might request no SSE via
409 // -mattr, so don't force SSELevel here.
411 // Otherwise, use CPUID to auto-detect feature set.
412 AutoDetectSubtargetFeatures();
413 // Make sure SSE2 is enabled; it is available on all X86-64 CPUs.
414 if (Is64Bit && X86SSELevel < SSE2)
418 // If requesting codegen for X86-64, make sure that 64-bit features
423 DEBUG(errs() << "Subtarget features: SSELevel " << X86SSELevel
424 << ", 3DNowLevel " << X863DNowLevel
425 << ", 64bit " << HasX86_64 << "\n");
426 assert((!Is64Bit || HasX86_64) &&
427 "64-bit code requested on a subtarget that doesn't support it!");
429 // Set the boolean corresponding to the current target triple, or the default
430 // if one cannot be determined, to true.
431 if (TT.length() > 5) {
433 if ((Pos = TT.find("-darwin")) != std::string::npos) {
434 TargetType = isDarwin;
436 // Compute the darwin version number.
437 if (isdigit(TT[Pos+7]))
438 DarwinVers = atoi(&TT[Pos+7]);
440 DarwinVers = 8; // Minimum supported darwin is Tiger.
441 } else if (TT.find("linux") != std::string::npos) {
442 // Linux doesn't imply ELF, but we don't currently support anything else.
445 } else if (TT.find("cygwin") != std::string::npos) {
446 TargetType = isCygwin;
447 } else if (TT.find("mingw") != std::string::npos) {
448 TargetType = isMingw;
449 } else if (TT.find("win32") != std::string::npos) {
450 TargetType = isWindows;
451 } else if (TT.find("windows") != std::string::npos) {
452 TargetType = isWindows;
453 } else if (TT.find("-cl") != std::string::npos) {
454 TargetType = isDarwin;
459 // Stack alignment is 16 bytes on Darwin (both 32 and 64 bit) and for all 64
461 if (TargetType == isDarwin || Is64Bit)
465 stackAlignment = StackAlignment;