1 //===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "subtarget"
15 #include "X86Subtarget.h"
16 #include "X86InstrInfo.h"
17 #include "llvm/IR/Attributes.h"
18 #include "llvm/IR/Function.h"
19 #include "llvm/IR/GlobalValue.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/Host.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetOptions.h"
27 #define GET_SUBTARGETINFO_TARGET_DESC
28 #define GET_SUBTARGETINFO_CTOR
29 #include "X86GenSubtargetInfo.inc"
37 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
38 /// current subtarget according to how we should reference it in a non-pcrel
40 unsigned char X86Subtarget::ClassifyBlockAddressReference() const {
41 if (isPICStyleGOT()) // 32-bit ELF targets.
42 return X86II::MO_GOTOFF;
44 if (isPICStyleStubPIC()) // Darwin/32 in PIC mode.
45 return X86II::MO_PIC_BASE_OFFSET;
47 // Direct static reference to label.
48 return X86II::MO_NO_FLAG;
51 /// ClassifyGlobalReference - Classify a global variable reference for the
52 /// current subtarget according to how we should reference it in a non-pcrel
54 unsigned char X86Subtarget::
55 ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
56 // DLLImport only exists on windows, it is implemented as a load from a
58 if (GV->hasDLLImportStorageClass())
59 return X86II::MO_DLLIMPORT;
61 // Determine whether this is a reference to a definition or a declaration.
62 // Materializable GVs (in JIT lazy compilation mode) do not require an extra
64 bool isDecl = GV->hasAvailableExternallyLinkage();
65 if (GV->isDeclaration() && !GV->isMaterializable())
68 // X86-64 in PIC mode.
69 if (isPICStyleRIPRel()) {
70 // Large model never uses stubs.
71 if (TM.getCodeModel() == CodeModel::Large)
72 return X86II::MO_NO_FLAG;
74 if (isTargetDarwin()) {
75 // If symbol visibility is hidden, the extra load is not needed if
76 // target is x86-64 or the symbol is definitely defined in the current
78 if (GV->hasDefaultVisibility() &&
79 (isDecl || GV->isWeakForLinker()))
80 return X86II::MO_GOTPCREL;
81 } else if (!isTargetWin64()) {
82 assert(isTargetELF() && "Unknown rip-relative target");
84 // Extra load is needed for all externally visible.
85 if (!GV->hasLocalLinkage() && GV->hasDefaultVisibility())
86 return X86II::MO_GOTPCREL;
89 return X86II::MO_NO_FLAG;
92 if (isPICStyleGOT()) { // 32-bit ELF targets.
93 // Extra load is needed for all externally visible.
94 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
95 return X86II::MO_GOTOFF;
99 if (isPICStyleStubPIC()) { // Darwin/32 in PIC mode.
100 // Determine whether we have a stub reference and/or whether the reference
101 // is relative to the PIC base or not.
103 // If this is a strong reference to a definition, it is definitely not
105 if (!isDecl && !GV->isWeakForLinker())
106 return X86II::MO_PIC_BASE_OFFSET;
108 // Unless we have a symbol with hidden visibility, we have to go through a
109 // normal $non_lazy_ptr stub because this symbol might be resolved late.
110 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
111 return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
113 // If symbol visibility is hidden, we have a stub for common symbol
114 // references and external declarations.
115 if (isDecl || GV->hasCommonLinkage()) {
116 // Hidden $non_lazy_ptr reference.
117 return X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE;
120 // Otherwise, no stub.
121 return X86II::MO_PIC_BASE_OFFSET;
124 if (isPICStyleStubNoDynamic()) { // Darwin/32 in -mdynamic-no-pic mode.
125 // Determine whether we have a stub reference.
127 // If this is a strong reference to a definition, it is definitely not
129 if (!isDecl && !GV->isWeakForLinker())
130 return X86II::MO_NO_FLAG;
132 // Unless we have a symbol with hidden visibility, we have to go through a
133 // normal $non_lazy_ptr stub because this symbol might be resolved late.
134 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
135 return X86II::MO_DARWIN_NONLAZY;
137 // Otherwise, no stub.
138 return X86II::MO_NO_FLAG;
141 // Direct static reference to global.
142 return X86II::MO_NO_FLAG;
146 /// getBZeroEntry - This function returns the name of a function which has an
147 /// interface like the non-standard bzero function, if such a function exists on
148 /// the current subtarget and it is considered prefereable over memset with zero
149 /// passed as the second argument. Otherwise it returns null.
150 const char *X86Subtarget::getBZeroEntry() const {
151 // Darwin 10 has a __bzero entry point for this purpose.
152 if (getTargetTriple().isMacOSX() &&
153 !getTargetTriple().isMacOSXVersionLT(10, 6))
159 bool X86Subtarget::hasSinCos() const {
160 return getTargetTriple().isMacOSX() &&
161 !getTargetTriple().isMacOSXVersionLT(10, 9) &&
165 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
166 /// to immediate address.
167 bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
170 return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
173 static bool OSHasAVXSupport() {
174 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
175 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
176 #if defined(__GNUC__)
177 // Check xgetbv; this uses a .byte sequence instead of the instruction
178 // directly because older assemblers do not include support for xgetbv and
179 // there is no easy way to conditionally compile based on the assembler used.
181 __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
182 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
183 unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
185 int rEAX = 0; // Ensures we return false
187 return (rEAX & 6) == 6;
193 void X86Subtarget::AutoDetectSubtargetFeatures() {
194 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
201 if (X86_MC::GetCpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) ||
205 X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
207 if ((EDX >> 15) & 1) { HasCMov = true; ToggleFeature(X86::FeatureCMOV); }
208 if ((EDX >> 23) & 1) { X86SSELevel = MMX; ToggleFeature(X86::FeatureMMX); }
209 if ((EDX >> 25) & 1) { X86SSELevel = SSE1; ToggleFeature(X86::FeatureSSE1); }
210 if ((EDX >> 26) & 1) { X86SSELevel = SSE2; ToggleFeature(X86::FeatureSSE2); }
211 if (ECX & 0x1) { X86SSELevel = SSE3; ToggleFeature(X86::FeatureSSE3); }
212 if ((ECX >> 9) & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);}
213 if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);}
214 if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);}
215 if (((ECX >> 27) & 1) && ((ECX >> 28) & 1) && OSHasAVXSupport()) {
216 X86SSELevel = AVX; ToggleFeature(X86::FeatureAVX);
219 bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
220 bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
222 if ((ECX >> 1) & 0x1) {
224 ToggleFeature(X86::FeaturePCLMUL);
226 if ((ECX >> 12) & 0x1) {
228 ToggleFeature(X86::FeatureFMA);
230 if (IsIntel && ((ECX >> 22) & 0x1)) {
232 ToggleFeature(X86::FeatureMOVBE);
234 if ((ECX >> 23) & 0x1) {
236 ToggleFeature(X86::FeaturePOPCNT);
238 if ((ECX >> 25) & 0x1) {
240 ToggleFeature(X86::FeatureAES);
242 if ((ECX >> 29) & 0x1) {
244 ToggleFeature(X86::FeatureF16C);
246 if (IsIntel && ((ECX >> 30) & 0x1)) {
248 ToggleFeature(X86::FeatureRDRAND);
251 if ((ECX >> 13) & 0x1) {
252 HasCmpxchg16b = true;
253 ToggleFeature(X86::FeatureCMPXCHG16B);
256 if (IsIntel || IsAMD) {
257 // Determine if bit test memory instructions are slow.
260 X86_MC::DetectFamilyModel(EAX, Family, Model);
261 if (IsAMD || (Family == 6 && Model >= 13)) {
263 ToggleFeature(X86::FeatureSlowBTMem);
266 // Determine if SHLD/SHRD instructions have higher latency then the
267 // equivalent series of shifts/or instructions.
268 // FIXME: Add Intel's processors that have SHLD instructions with very
272 ToggleFeature(X86::FeatureSlowSHLD);
275 // If it's an Intel chip since Nehalem and not an Atom chip, unaligned
276 // memory access is fast. We hard code model numbers here because they
277 // aren't strictly increasing for Intel chips it seems.
279 ((Family == 6 && Model == 0x1E) || // Nehalem: Clarksfield, Lynnfield,
281 (Family == 6 && Model == 0x1A) || // Nehalem: Bloomfield, Nehalem-EP
282 (Family == 6 && Model == 0x2E) || // Nehalem: Nehalem-EX
283 (Family == 6 && Model == 0x25) || // Westmere: Arrandale, Clarksdale
284 (Family == 6 && Model == 0x2C) || // Westmere: Gulftown, Westmere-EP
285 (Family == 6 && Model == 0x2F) || // Westmere: Westmere-EX
286 (Family == 6 && Model == 0x2A) || // SandyBridge
287 (Family == 6 && Model == 0x2D) || // SandyBridge: SandyBridge-E*
288 (Family == 6 && Model == 0x3A) || // IvyBridge
289 (Family == 6 && Model == 0x3E) || // IvyBridge EP
290 (Family == 6 && Model == 0x3C) || // Haswell
291 (Family == 6 && Model == 0x3F) || // ...
292 (Family == 6 && Model == 0x45) || // ...
293 (Family == 6 && Model == 0x46))) { // ...
295 ToggleFeature(X86::FeatureFastUAMem);
298 // Set processor type. Currently only Atom or Silvermont (SLM) is detected.
300 (Model == 28 || Model == 38 || Model == 39 ||
301 Model == 53 || Model == 54)) {
302 X86ProcFamily = IntelAtom;
305 ToggleFeature(X86::FeatureLeaForSP);
307 else if (Family == 6 &&
308 (Model == 55 || Model == 74 || Model == 77)) {
309 X86ProcFamily = IntelSLM;
312 unsigned MaxExtLevel;
313 X86_MC::GetCpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
315 if (MaxExtLevel >= 0x80000001) {
316 X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
317 if ((EDX >> 29) & 0x1) {
319 ToggleFeature(X86::Feature64Bit);
321 if ((ECX >> 5) & 0x1) {
323 ToggleFeature(X86::FeatureLZCNT);
325 if (IsIntel && ((ECX >> 8) & 0x1)) {
327 ToggleFeature(X86::FeaturePRFCHW);
330 if ((ECX >> 6) & 0x1) {
332 ToggleFeature(X86::FeatureSSE4A);
334 if ((ECX >> 11) & 0x1) {
336 ToggleFeature(X86::FeatureXOP);
338 if ((ECX >> 16) & 0x1) {
340 ToggleFeature(X86::FeatureFMA4);
347 if (!X86_MC::GetCpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX)) {
348 if (IsIntel && (EBX & 0x1)) {
350 ToggleFeature(X86::FeatureFSGSBase);
352 if ((EBX >> 3) & 0x1) {
354 ToggleFeature(X86::FeatureBMI);
356 if ((EBX >> 4) & 0x1) {
358 ToggleFeature(X86::FeatureHLE);
360 if (IsIntel && ((EBX >> 5) & 0x1)) {
362 ToggleFeature(X86::FeatureAVX2);
364 if (IsIntel && ((EBX >> 8) & 0x1)) {
366 ToggleFeature(X86::FeatureBMI2);
368 if (IsIntel && ((EBX >> 11) & 0x1)) {
370 ToggleFeature(X86::FeatureRTM);
372 if (IsIntel && ((EBX >> 16) & 0x1)) {
373 X86SSELevel = AVX512F;
374 ToggleFeature(X86::FeatureAVX512);
376 if (IsIntel && ((EBX >> 18) & 0x1)) {
378 ToggleFeature(X86::FeatureRDSEED);
380 if (IsIntel && ((EBX >> 19) & 0x1)) {
382 ToggleFeature(X86::FeatureADX);
384 if (IsIntel && ((EBX >> 26) & 0x1)) {
386 ToggleFeature(X86::FeaturePFI);
388 if (IsIntel && ((EBX >> 27) & 0x1)) {
390 ToggleFeature(X86::FeatureERI);
392 if (IsIntel && ((EBX >> 28) & 0x1)) {
394 ToggleFeature(X86::FeatureCDI);
396 if (IsIntel && ((EBX >> 29) & 0x1)) {
398 ToggleFeature(X86::FeatureSHA);
401 if (IsAMD && ((ECX >> 21) & 0x1)) {
403 ToggleFeature(X86::FeatureTBM);
408 void X86Subtarget::resetSubtargetFeatures(const MachineFunction *MF) {
409 AttributeSet FnAttrs = MF->getFunction()->getAttributes();
410 Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
412 Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
415 !CPUAttr.hasAttribute(Attribute::None) ?CPUAttr.getValueAsString() : "";
417 !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
419 initializeEnvironment();
420 resetSubtargetFeatures(CPU, FS);
424 void X86Subtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
425 std::string CPUName = CPU;
426 if (!FS.empty() || !CPU.empty()) {
427 if (CPUName.empty()) {
428 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
429 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
430 CPUName = sys::getHostCPUName();
436 // Make sure 64-bit features are available in 64-bit mode. (But make sure
437 // SSE2 can be turned off explicitly.)
438 std::string FullFS = FS;
441 FullFS = "+64bit,+sse2," + FullFS;
443 FullFS = "+64bit,+sse2";
446 // If feature string is not empty, parse features string.
447 ParseSubtargetFeatures(CPUName, FullFS);
449 if (CPUName.empty()) {
450 #if defined (__x86_64__) || defined(__i386__)
451 CPUName = sys::getHostCPUName();
456 // Otherwise, use CPUID to auto-detect feature set.
457 AutoDetectSubtargetFeatures();
459 // Make sure 64-bit features are available in 64-bit mode.
461 if (!HasX86_64) { HasX86_64 = true; ToggleFeature(X86::Feature64Bit); }
462 if (!HasCMov) { HasCMov = true; ToggleFeature(X86::FeatureCMOV); }
464 if (X86SSELevel < SSE2) {
466 ToggleFeature(X86::FeatureSSE1);
467 ToggleFeature(X86::FeatureSSE2);
472 // CPUName may have been set by the CPU detection code. Make sure the
473 // new MCSchedModel is used.
474 InitCPUSchedModel(CPUName);
476 if (X86ProcFamily == IntelAtom || X86ProcFamily == IntelSLM)
477 PostRAScheduler = true;
479 InstrItins = getInstrItineraryForCPU(CPUName);
481 // It's important to keep the MCSubtargetInfo feature bits in sync with
482 // target data structure which is shared with MC code emitter, etc.
484 ToggleFeature(X86::Mode64Bit);
485 else if (In32BitMode)
486 ToggleFeature(X86::Mode32Bit);
487 else if (In16BitMode)
488 ToggleFeature(X86::Mode16Bit);
490 llvm_unreachable("Not 16-bit, 32-bit or 64-bit mode!");
492 DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
493 << ", 3DNowLevel " << X863DNowLevel
494 << ", 64bit " << HasX86_64 << "\n");
495 assert((!In64BitMode || HasX86_64) &&
496 "64-bit code requested on a subtarget that doesn't support it!");
498 // Stack alignment is 16 bytes on Darwin, Linux and Solaris (both
499 // 32 and 64 bit) and for all 64-bit targets.
500 if (StackAlignOverride)
501 stackAlignment = StackAlignOverride;
502 else if (isTargetDarwin() || isTargetLinux() || isTargetSolaris() ||
507 void X86Subtarget::initializeEnvironment() {
508 X86SSELevel = NoMMXSSE;
509 X863DNowLevel = NoThreeDNow;
539 HasVectorUAMem = false;
540 HasCmpxchg16b = false;
542 HasSlowDivide = false;
543 PostRAScheduler = false;
544 PadShortFunctions = false;
545 CallRegIndirect = false;
548 // FIXME: this is a known good value for Yonah. How about others?
549 MaxInlineSizeThreshold = 128;
552 X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
553 const std::string &FS,
554 unsigned StackAlignOverride)
555 : X86GenSubtargetInfo(TT, CPU, FS)
556 , X86ProcFamily(Others)
557 , PICStyle(PICStyles::None)
559 , StackAlignOverride(StackAlignOverride)
560 , In64BitMode(TargetTriple.getArch() == Triple::x86_64)
561 , In32BitMode(TargetTriple.getArch() == Triple::x86 &&
562 TargetTriple.getEnvironment() != Triple::CODE16)
563 , In16BitMode(TargetTriple.getArch() == Triple::x86 &&
564 TargetTriple.getEnvironment() == Triple::CODE16) {
565 initializeEnvironment();
566 resetSubtargetFeatures(CPU, FS);
569 bool X86Subtarget::enablePostRAScheduler(
570 CodeGenOpt::Level OptLevel,
571 TargetSubtargetInfo::AntiDepBreakMode& Mode,
572 RegClassVector& CriticalPathRCs) const {
573 Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
574 CriticalPathRCs.clear();
575 return PostRAScheduler && OptLevel >= CodeGenOpt::Default;