1 //===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "subtarget"
15 #include "X86Subtarget.h"
16 #include "X86InstrInfo.h"
17 #include "llvm/IR/Attributes.h"
18 #include "llvm/IR/Function.h"
19 #include "llvm/IR/GlobalValue.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/Host.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetOptions.h"
27 #define GET_SUBTARGETINFO_TARGET_DESC
28 #define GET_SUBTARGETINFO_CTOR
29 #include "X86GenSubtargetInfo.inc"
37 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
38 /// current subtarget according to how we should reference it in a non-pcrel
40 unsigned char X86Subtarget::ClassifyBlockAddressReference() const {
41 if (isPICStyleGOT()) // 32-bit ELF targets.
42 return X86II::MO_GOTOFF;
44 if (isPICStyleStubPIC()) // Darwin/32 in PIC mode.
45 return X86II::MO_PIC_BASE_OFFSET;
47 // Direct static reference to label.
48 return X86II::MO_NO_FLAG;
51 /// ClassifyGlobalReference - Classify a global variable reference for the
52 /// current subtarget according to how we should reference it in a non-pcrel
54 unsigned char X86Subtarget::
55 ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
56 // DLLImport only exists on windows, it is implemented as a load from a
58 if (GV->hasDLLImportStorageClass())
59 return X86II::MO_DLLIMPORT;
61 // Determine whether this is a reference to a definition or a declaration.
62 // Materializable GVs (in JIT lazy compilation mode) do not require an extra
64 bool isDecl = GV->hasAvailableExternallyLinkage();
65 if (GV->isDeclaration() && !GV->isMaterializable())
68 // X86-64 in PIC mode.
69 if (isPICStyleRIPRel()) {
70 // Large model never uses stubs.
71 if (TM.getCodeModel() == CodeModel::Large)
72 return X86II::MO_NO_FLAG;
74 if (isTargetDarwin()) {
75 // If symbol visibility is hidden, the extra load is not needed if
76 // target is x86-64 or the symbol is definitely defined in the current
78 if (GV->hasDefaultVisibility() &&
79 (isDecl || GV->isWeakForLinker()))
80 return X86II::MO_GOTPCREL;
81 } else if (!isTargetWin64()) {
82 assert(isTargetELF() && "Unknown rip-relative target");
84 // Extra load is needed for all externally visible.
85 if (!GV->hasLocalLinkage() && GV->hasDefaultVisibility())
86 return X86II::MO_GOTPCREL;
89 return X86II::MO_NO_FLAG;
92 if (isPICStyleGOT()) { // 32-bit ELF targets.
93 // Extra load is needed for all externally visible.
94 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
95 return X86II::MO_GOTOFF;
99 if (isPICStyleStubPIC()) { // Darwin/32 in PIC mode.
100 // Determine whether we have a stub reference and/or whether the reference
101 // is relative to the PIC base or not.
103 // If this is a strong reference to a definition, it is definitely not
105 if (!isDecl && !GV->isWeakForLinker())
106 return X86II::MO_PIC_BASE_OFFSET;
108 // Unless we have a symbol with hidden visibility, we have to go through a
109 // normal $non_lazy_ptr stub because this symbol might be resolved late.
110 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
111 return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
113 // If symbol visibility is hidden, we have a stub for common symbol
114 // references and external declarations.
115 if (isDecl || GV->hasCommonLinkage()) {
116 // Hidden $non_lazy_ptr reference.
117 return X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE;
120 // Otherwise, no stub.
121 return X86II::MO_PIC_BASE_OFFSET;
124 if (isPICStyleStubNoDynamic()) { // Darwin/32 in -mdynamic-no-pic mode.
125 // Determine whether we have a stub reference.
127 // If this is a strong reference to a definition, it is definitely not
129 if (!isDecl && !GV->isWeakForLinker())
130 return X86II::MO_NO_FLAG;
132 // Unless we have a symbol with hidden visibility, we have to go through a
133 // normal $non_lazy_ptr stub because this symbol might be resolved late.
134 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
135 return X86II::MO_DARWIN_NONLAZY;
137 // Otherwise, no stub.
138 return X86II::MO_NO_FLAG;
141 // Direct static reference to global.
142 return X86II::MO_NO_FLAG;
146 /// getBZeroEntry - This function returns the name of a function which has an
147 /// interface like the non-standard bzero function, if such a function exists on
148 /// the current subtarget and it is considered prefereable over memset with zero
149 /// passed as the second argument. Otherwise it returns null.
150 const char *X86Subtarget::getBZeroEntry() const {
151 // Darwin 10 has a __bzero entry point for this purpose.
152 if (getTargetTriple().isMacOSX() &&
153 !getTargetTriple().isMacOSXVersionLT(10, 6))
159 bool X86Subtarget::hasSinCos() const {
160 return getTargetTriple().isMacOSX() &&
161 !getTargetTriple().isMacOSXVersionLT(10, 9) &&
165 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
166 /// to immediate address.
167 bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
168 // FIXME: I386 PE/COFF supports PC relative calls using IMAGE_REL_I386_REL32
169 // but WinCOFFObjectWriter::RecordRelocation cannot emit them. Once it does,
170 // the following check for Win32 should be removed.
171 if (In64BitMode || isTargetWin32())
173 return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
176 static bool OSHasAVXSupport() {
177 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
178 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
179 #if defined(__GNUC__)
180 // Check xgetbv; this uses a .byte sequence instead of the instruction
181 // directly because older assemblers do not include support for xgetbv and
182 // there is no easy way to conditionally compile based on the assembler used.
184 __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
185 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
186 unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
188 int rEAX = 0; // Ensures we return false
190 return (rEAX & 6) == 6;
196 void X86Subtarget::AutoDetectSubtargetFeatures() {
197 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
204 if (X86_MC::GetCpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) ||
208 X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
210 if ((EDX >> 15) & 1) { HasCMov = true; ToggleFeature(X86::FeatureCMOV); }
211 if ((EDX >> 23) & 1) { X86SSELevel = MMX; ToggleFeature(X86::FeatureMMX); }
212 if ((EDX >> 25) & 1) { X86SSELevel = SSE1; ToggleFeature(X86::FeatureSSE1); }
213 if ((EDX >> 26) & 1) { X86SSELevel = SSE2; ToggleFeature(X86::FeatureSSE2); }
214 if (ECX & 0x1) { X86SSELevel = SSE3; ToggleFeature(X86::FeatureSSE3); }
215 if ((ECX >> 9) & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);}
216 if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);}
217 if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);}
218 if (((ECX >> 27) & 1) && ((ECX >> 28) & 1) && OSHasAVXSupport()) {
219 X86SSELevel = AVX; ToggleFeature(X86::FeatureAVX);
222 bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
223 bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
225 if ((ECX >> 1) & 0x1) {
227 ToggleFeature(X86::FeaturePCLMUL);
229 if ((ECX >> 12) & 0x1) {
231 ToggleFeature(X86::FeatureFMA);
233 if (IsIntel && ((ECX >> 22) & 0x1)) {
235 ToggleFeature(X86::FeatureMOVBE);
237 if ((ECX >> 23) & 0x1) {
239 ToggleFeature(X86::FeaturePOPCNT);
241 if ((ECX >> 25) & 0x1) {
243 ToggleFeature(X86::FeatureAES);
245 if ((ECX >> 29) & 0x1) {
247 ToggleFeature(X86::FeatureF16C);
249 if (IsIntel && ((ECX >> 30) & 0x1)) {
251 ToggleFeature(X86::FeatureRDRAND);
254 if ((ECX >> 13) & 0x1) {
255 HasCmpxchg16b = true;
256 ToggleFeature(X86::FeatureCMPXCHG16B);
259 if (IsIntel || IsAMD) {
260 // Determine if bit test memory instructions are slow.
263 X86_MC::DetectFamilyModel(EAX, Family, Model);
264 if (IsAMD || (Family == 6 && Model >= 13)) {
266 ToggleFeature(X86::FeatureSlowBTMem);
269 // Determine if SHLD/SHRD instructions have higher latency then the
270 // equivalent series of shifts/or instructions.
271 // FIXME: Add Intel's processors that have SHLD instructions with very
275 ToggleFeature(X86::FeatureSlowSHLD);
278 // If it's an Intel chip since Nehalem and not an Atom chip, unaligned
279 // memory access is fast. We hard code model numbers here because they
280 // aren't strictly increasing for Intel chips it seems.
282 ((Family == 6 && Model == 0x1E) || // Nehalem: Clarksfield, Lynnfield,
284 (Family == 6 && Model == 0x1A) || // Nehalem: Bloomfield, Nehalem-EP
285 (Family == 6 && Model == 0x2E) || // Nehalem: Nehalem-EX
286 (Family == 6 && Model == 0x25) || // Westmere: Arrandale, Clarksdale
287 (Family == 6 && Model == 0x2C) || // Westmere: Gulftown, Westmere-EP
288 (Family == 6 && Model == 0x2F) || // Westmere: Westmere-EX
289 (Family == 6 && Model == 0x2A) || // SandyBridge
290 (Family == 6 && Model == 0x2D) || // SandyBridge: SandyBridge-E*
291 (Family == 6 && Model == 0x3A) || // IvyBridge
292 (Family == 6 && Model == 0x3E) || // IvyBridge EP
293 (Family == 6 && Model == 0x3C) || // Haswell
294 (Family == 6 && Model == 0x3F) || // ...
295 (Family == 6 && Model == 0x45) || // ...
296 (Family == 6 && Model == 0x46))) { // ...
298 ToggleFeature(X86::FeatureFastUAMem);
301 // Set processor type. Currently only Atom or Silvermont (SLM) is detected.
303 (Model == 28 || Model == 38 || Model == 39 ||
304 Model == 53 || Model == 54)) {
305 X86ProcFamily = IntelAtom;
308 ToggleFeature(X86::FeatureLeaForSP);
310 else if (Family == 6 &&
311 (Model == 55 || Model == 74 || Model == 77)) {
312 X86ProcFamily = IntelSLM;
315 unsigned MaxExtLevel;
316 X86_MC::GetCpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
318 if (MaxExtLevel >= 0x80000001) {
319 X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
320 if ((EDX >> 29) & 0x1) {
322 ToggleFeature(X86::Feature64Bit);
324 if ((ECX >> 5) & 0x1) {
326 ToggleFeature(X86::FeatureLZCNT);
328 if (IsIntel && ((ECX >> 8) & 0x1)) {
330 ToggleFeature(X86::FeaturePRFCHW);
333 if ((ECX >> 6) & 0x1) {
335 ToggleFeature(X86::FeatureSSE4A);
337 if ((ECX >> 11) & 0x1) {
339 ToggleFeature(X86::FeatureXOP);
341 if ((ECX >> 16) & 0x1) {
343 ToggleFeature(X86::FeatureFMA4);
350 if (!X86_MC::GetCpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX)) {
351 if (IsIntel && (EBX & 0x1)) {
353 ToggleFeature(X86::FeatureFSGSBase);
355 if ((EBX >> 3) & 0x1) {
357 ToggleFeature(X86::FeatureBMI);
359 if ((EBX >> 4) & 0x1) {
361 ToggleFeature(X86::FeatureHLE);
363 if (IsIntel && ((EBX >> 5) & 0x1)) {
365 ToggleFeature(X86::FeatureAVX2);
367 if (IsIntel && ((EBX >> 8) & 0x1)) {
369 ToggleFeature(X86::FeatureBMI2);
371 if (IsIntel && ((EBX >> 11) & 0x1)) {
373 ToggleFeature(X86::FeatureRTM);
375 if (IsIntel && ((EBX >> 16) & 0x1)) {
376 X86SSELevel = AVX512F;
377 ToggleFeature(X86::FeatureAVX512);
379 if (IsIntel && ((EBX >> 18) & 0x1)) {
381 ToggleFeature(X86::FeatureRDSEED);
383 if (IsIntel && ((EBX >> 19) & 0x1)) {
385 ToggleFeature(X86::FeatureADX);
387 if (IsIntel && ((EBX >> 26) & 0x1)) {
389 ToggleFeature(X86::FeaturePFI);
391 if (IsIntel && ((EBX >> 27) & 0x1)) {
393 ToggleFeature(X86::FeatureERI);
395 if (IsIntel && ((EBX >> 28) & 0x1)) {
397 ToggleFeature(X86::FeatureCDI);
399 if (IsIntel && ((EBX >> 29) & 0x1)) {
401 ToggleFeature(X86::FeatureSHA);
404 if (IsAMD && ((ECX >> 21) & 0x1)) {
406 ToggleFeature(X86::FeatureTBM);
411 void X86Subtarget::resetSubtargetFeatures(const MachineFunction *MF) {
412 AttributeSet FnAttrs = MF->getFunction()->getAttributes();
413 Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
415 Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
418 !CPUAttr.hasAttribute(Attribute::None) ?CPUAttr.getValueAsString() : "";
420 !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
422 initializeEnvironment();
423 resetSubtargetFeatures(CPU, FS);
427 void X86Subtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
428 std::string CPUName = CPU;
429 if (!FS.empty() || !CPU.empty()) {
430 if (CPUName.empty()) {
431 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
432 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
433 CPUName = sys::getHostCPUName();
439 // Make sure 64-bit features are available in 64-bit mode. (But make sure
440 // SSE2 can be turned off explicitly.)
441 std::string FullFS = FS;
444 FullFS = "+64bit,+sse2," + FullFS;
446 FullFS = "+64bit,+sse2";
449 // If feature string is not empty, parse features string.
450 ParseSubtargetFeatures(CPUName, FullFS);
452 if (CPUName.empty()) {
453 #if defined (__x86_64__) || defined(__i386__)
454 CPUName = sys::getHostCPUName();
459 // Otherwise, use CPUID to auto-detect feature set.
460 AutoDetectSubtargetFeatures();
462 // Make sure 64-bit features are available in 64-bit mode.
464 if (!HasX86_64) { HasX86_64 = true; ToggleFeature(X86::Feature64Bit); }
465 if (!HasCMov) { HasCMov = true; ToggleFeature(X86::FeatureCMOV); }
467 if (X86SSELevel < SSE2) {
469 ToggleFeature(X86::FeatureSSE1);
470 ToggleFeature(X86::FeatureSSE2);
475 // CPUName may have been set by the CPU detection code. Make sure the
476 // new MCSchedModel is used.
477 InitCPUSchedModel(CPUName);
479 if (X86ProcFamily == IntelAtom || X86ProcFamily == IntelSLM)
480 PostRAScheduler = true;
482 InstrItins = getInstrItineraryForCPU(CPUName);
484 // It's important to keep the MCSubtargetInfo feature bits in sync with
485 // target data structure which is shared with MC code emitter, etc.
487 ToggleFeature(X86::Mode64Bit);
488 else if (In32BitMode)
489 ToggleFeature(X86::Mode32Bit);
490 else if (In16BitMode)
491 ToggleFeature(X86::Mode16Bit);
493 llvm_unreachable("Not 16-bit, 32-bit or 64-bit mode!");
495 DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
496 << ", 3DNowLevel " << X863DNowLevel
497 << ", 64bit " << HasX86_64 << "\n");
498 assert((!In64BitMode || HasX86_64) &&
499 "64-bit code requested on a subtarget that doesn't support it!");
501 // Stack alignment is 16 bytes on Darwin, Linux and Solaris (both
502 // 32 and 64 bit) and for all 64-bit targets.
503 if (StackAlignOverride)
504 stackAlignment = StackAlignOverride;
505 else if (isTargetDarwin() || isTargetLinux() || isTargetSolaris() ||
510 void X86Subtarget::initializeEnvironment() {
511 X86SSELevel = NoMMXSSE;
512 X863DNowLevel = NoThreeDNow;
542 HasVectorUAMem = false;
543 HasCmpxchg16b = false;
545 HasSlowDivide = false;
546 PostRAScheduler = false;
547 PadShortFunctions = false;
548 CallRegIndirect = false;
551 // FIXME: this is a known good value for Yonah. How about others?
552 MaxInlineSizeThreshold = 128;
555 X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
556 const std::string &FS,
557 unsigned StackAlignOverride)
558 : X86GenSubtargetInfo(TT, CPU, FS)
559 , X86ProcFamily(Others)
560 , PICStyle(PICStyles::None)
562 , StackAlignOverride(StackAlignOverride)
563 , In64BitMode(TargetTriple.getArch() == Triple::x86_64)
564 , In32BitMode(TargetTriple.getArch() == Triple::x86 &&
565 TargetTriple.getEnvironment() != Triple::CODE16)
566 , In16BitMode(TargetTriple.getArch() == Triple::x86 &&
567 TargetTriple.getEnvironment() == Triple::CODE16) {
568 initializeEnvironment();
569 resetSubtargetFeatures(CPU, FS);
572 bool X86Subtarget::enablePostRAScheduler(
573 CodeGenOpt::Level OptLevel,
574 TargetSubtargetInfo::AntiDepBreakMode& Mode,
575 RegClassVector& CriticalPathRCs) const {
576 Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
577 CriticalPathRCs.clear();
578 return PostRAScheduler && OptLevel >= CodeGenOpt::Default;