1 //===-- X86Subtarget.cpp - X86 Subtarget Information ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86 specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "subtarget"
15 #include "X86Subtarget.h"
16 #include "X86GenSubtarget.inc"
17 #include "llvm/Module.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetOptions.h"
24 static cl::opt<X86Subtarget::AsmWriterFlavorTy>
25 AsmWriterFlavor("x86-asm-syntax", cl::init(X86Subtarget::Unset),
26 cl::desc("Choose style of code to emit from X86 backend:"),
28 clEnumValN(X86Subtarget::ATT, "att", "Emit AT&T-style assembly"),
29 clEnumValN(X86Subtarget::Intel, "intel", "Emit Intel-style assembly"),
33 /// True if accessing the GV requires an extra load. For Windows, dllimported
34 /// symbols are indirect, loading the value at address GV rather then the
35 /// value of GV itself. This means that the GlobalAddress must be in the base
36 /// or index register of the address, not the GV offset field.
37 bool X86Subtarget::GVRequiresExtraLoad(const GlobalValue* GV,
38 const TargetMachine& TM,
39 bool isDirectCall) const
42 if (TM.getRelocationModel() != Reloc::Static &&
43 TM.getCodeModel() != CodeModel::Large) {
44 if (isTargetDarwin()) {
47 bool isDecl = GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode();
48 if (GV->hasHiddenVisibility() &&
49 (Is64Bit || (!isDecl && !GV->hasCommonLinkage())))
50 // If symbol visibility is hidden, the extra load is not needed if
51 // target is x86-64 or the symbol is definitely defined in the current
54 return !isDirectCall && (isDecl || GV->isWeakForLinker());
55 } else if (isTargetELF()) {
56 // Extra load is needed for all externally visible.
59 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
62 } else if (isTargetCygMing() || isTargetWindows()) {
63 return (GV->hasDLLImportLinkage());
69 /// True if accessing the GV requires a register. This is a superset of the
70 /// cases where GVRequiresExtraLoad is true. Some variations of PIC require
71 /// a register, but not an extra load.
72 bool X86Subtarget::GVRequiresRegister(const GlobalValue *GV,
73 const TargetMachine& TM,
74 bool isDirectCall) const
76 if (GVRequiresExtraLoad(GV, TM, isDirectCall))
78 // Code below here need only consider cases where GVRequiresExtraLoad
80 if (TM.getRelocationModel() == Reloc::PIC_)
81 return !isDirectCall &&
82 (GV->hasLocalLinkage() || GV->hasExternalLinkage());
86 /// getBZeroEntry - This function returns the name of a function which has an
87 /// interface like the non-standard bzero function, if such a function exists on
88 /// the current subtarget and it is considered prefereable over memset with zero
89 /// passed as the second argument. Otherwise it returns null.
90 const char *X86Subtarget::getBZeroEntry() const {
91 // Darwin 10 has a __bzero entry point for this purpose.
92 if (getDarwinVers() >= 10)
98 /// getSpecialAddressLatency - For targets where it is beneficial to
99 /// backschedule instructions that compute addresses, return a value
100 /// indicating the number of scheduling cycles of backscheduling that
101 /// should be attempted.
102 unsigned X86Subtarget::getSpecialAddressLatency() const {
103 // For x86 out-of-order targets, back-schedule address computations so
104 // that loads and stores aren't blocked.
105 // This value was chosen arbitrarily.
109 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
110 /// specified arguments. If we can't run cpuid on the host, return true.
111 bool X86::GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
112 unsigned *rECX, unsigned *rEDX) {
113 #if defined(__x86_64__)
114 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
115 asm ("movq\t%%rbx, %%rsi\n\t"
117 "xchgq\t%%rbx, %%rsi\n\t"
124 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
125 #if defined(__GNUC__)
126 asm ("movl\t%%ebx, %%esi\n\t"
128 "xchgl\t%%ebx, %%esi\n\t"
135 #elif defined(_MSC_VER)
140 mov dword ptr [esi],eax
142 mov dword ptr [esi],ebx
144 mov dword ptr [esi],ecx
146 mov dword ptr [esi],edx
154 static void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model) {
155 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
156 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
157 if (Family == 6 || Family == 0xf) {
159 // Examine extended family ID if family ID is F.
160 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
161 // Examine extended model ID if family ID is 6 or F.
162 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
166 void X86Subtarget::AutoDetectSubtargetFeatures() {
167 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
173 if (X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
176 X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
178 if ((EDX >> 23) & 0x1) X86SSELevel = MMX;
179 if ((EDX >> 25) & 0x1) X86SSELevel = SSE1;
180 if ((EDX >> 26) & 0x1) X86SSELevel = SSE2;
181 if (ECX & 0x1) X86SSELevel = SSE3;
182 if ((ECX >> 9) & 0x1) X86SSELevel = SSSE3;
183 if ((ECX >> 19) & 0x1) X86SSELevel = SSE41;
184 if ((ECX >> 20) & 0x1) X86SSELevel = SSE42;
186 bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
187 bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
188 if (IsIntel || IsAMD) {
189 // Determine if bit test memory instructions are slow.
192 DetectFamilyModel(EAX, Family, Model);
193 IsBTMemSlow = IsAMD || (Family == 6 && Model >= 13);
195 X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
196 HasX86_64 = (EDX >> 29) & 0x1;
200 static const char *GetCurrentX86CPU() {
201 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
202 if (X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
206 DetectFamilyModel(EAX, Family, Model);
208 X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
209 bool Em64T = (EDX >> 29) & 0x1;
216 X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
217 if (memcmp(text.c, "GenuineIntel", 12) == 0) {
225 case 4: return "pentium-mmx";
226 default: return "pentium";
230 case 1: return "pentiumpro";
233 case 6: return "pentium2";
237 case 11: return "pentium3";
239 case 13: return "pentium-m";
240 case 14: return "yonah";
242 case 22: // Celeron M 540
244 case 23: // 45nm: Penryn , Wolfdale, Yorkfield (XE)
246 default: return "i686";
252 case 6: // same as 4, but 65nm
253 return (Em64T) ? "nocona" : "prescott";
259 return (Em64T) ? "x86-64" : "pentium4";
266 } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
267 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
268 // appears to be no way to generate the wide variety of AMD-specific targets
269 // from the information returned from CPUID.
277 case 8: return "k6-2";
279 case 13: return "k6-3";
280 default: return "pentium";
284 case 4: return "athlon-tbird";
287 case 8: return "athlon-mp";
288 case 10: return "athlon-xp";
289 default: return "athlon";
293 case 1: return "opteron";
294 case 5: return "athlon-fx"; // also opteron
295 default: return "athlon64";
305 X86Subtarget::X86Subtarget(const Module &M, const std::string &FS, bool is64Bit)
306 : AsmFlavor(AsmWriterFlavor)
307 , PICStyle(PICStyles::None)
308 , X86SSELevel(NoMMXSSE)
309 , X863DNowLevel(NoThreeDNow)
315 // FIXME: this is a known good value for Yonah. How about others?
316 , MaxInlineSizeThreshold(128)
318 , TargetType(isELF) { // Default to ELF unless otherwise specified.
320 // Determine default and user specified characteristics
322 // If feature string is not empty, parse features string.
323 std::string CPU = GetCurrentX86CPU();
324 ParseSubtargetFeatures(FS, CPU);
325 // All X86-64 CPUs also have SSE2, however user might request no SSE via
326 // -mattr, so don't force SSELevel here.
328 // Otherwise, use CPUID to auto-detect feature set.
329 AutoDetectSubtargetFeatures();
330 // Make sure SSE2 is enabled; it is available on all X86-64 CPUs.
331 if (Is64Bit && X86SSELevel < SSE2)
335 // If requesting codegen for X86-64, make sure that 64-bit features
340 DOUT << "Subtarget features: SSELevel " << X86SSELevel
341 << ", 3DNowLevel " << X863DNowLevel
342 << ", 64bit " << HasX86_64 << "\n";
343 assert((!Is64Bit || HasX86_64) &&
344 "64-bit code requested on a subtarget that doesn't support it!");
346 // Set the boolean corresponding to the current target triple, or the default
347 // if one cannot be determined, to true.
348 const std::string& TT = M.getTargetTriple();
349 if (TT.length() > 5) {
351 if ((Pos = TT.find("-darwin")) != std::string::npos) {
352 TargetType = isDarwin;
354 // Compute the darwin version number.
355 if (isdigit(TT[Pos+7]))
356 DarwinVers = atoi(&TT[Pos+7]);
358 DarwinVers = 8; // Minimum supported darwin is Tiger.
359 } else if (TT.find("linux") != std::string::npos) {
360 // Linux doesn't imply ELF, but we don't currently support anything else.
363 } else if (TT.find("cygwin") != std::string::npos) {
364 TargetType = isCygwin;
365 } else if (TT.find("mingw") != std::string::npos) {
366 TargetType = isMingw;
367 } else if (TT.find("win32") != std::string::npos) {
368 TargetType = isWindows;
369 } else if (TT.find("windows") != std::string::npos) {
370 TargetType = isWindows;
372 else if (TT.find("-cl") != std::string::npos) {
373 TargetType = isDarwin;
376 } else if (TT.empty()) {
377 #if defined(__CYGWIN__)
378 TargetType = isCygwin;
379 #elif defined(__MINGW32__) || defined(__MINGW64__)
380 TargetType = isMingw;
381 #elif defined(__APPLE__)
382 TargetType = isDarwin;
383 #if __APPLE_CC__ > 5400
384 DarwinVers = 9; // GCC 5400+ is Leopard.
386 DarwinVers = 8; // Minimum supported darwin is Tiger.
389 #elif defined(_WIN32) || defined(_WIN64)
390 TargetType = isWindows;
391 #elif defined(__linux__)
392 // Linux doesn't imply ELF, but we don't currently support anything else.
398 // If the asm syntax hasn't been overridden on the command line, use whatever
400 if (AsmFlavor == X86Subtarget::Unset) {
401 AsmFlavor = (TargetType == isWindows)
402 ? X86Subtarget::Intel : X86Subtarget::ATT;
405 // Stack alignment is 16 bytes on Darwin (both 32 and 64 bit) and for all 64
407 if (TargetType == isDarwin || Is64Bit)
411 stackAlignment = StackAlignment;