1 //===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "subtarget"
15 #include "X86Subtarget.h"
16 #include "X86InstrInfo.h"
17 #include "llvm/IR/GlobalValue.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Support/Host.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetOptions.h"
25 #define GET_SUBTARGETINFO_TARGET_DESC
26 #define GET_SUBTARGETINFO_CTOR
27 #include "X86GenSubtargetInfo.inc"
35 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
36 /// current subtarget according to how we should reference it in a non-pcrel
38 unsigned char X86Subtarget::
39 ClassifyBlockAddressReference() const {
40 if (isPICStyleGOT()) // 32-bit ELF targets.
41 return X86II::MO_GOTOFF;
43 if (isPICStyleStubPIC()) // Darwin/32 in PIC mode.
44 return X86II::MO_PIC_BASE_OFFSET;
46 // Direct static reference to label.
47 return X86II::MO_NO_FLAG;
50 /// ClassifyGlobalReference - Classify a global variable reference for the
51 /// current subtarget according to how we should reference it in a non-pcrel
53 unsigned char X86Subtarget::
54 ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
55 // DLLImport only exists on windows, it is implemented as a load from a
57 if (GV->hasDLLImportLinkage())
58 return X86II::MO_DLLIMPORT;
60 // Determine whether this is a reference to a definition or a declaration.
61 // Materializable GVs (in JIT lazy compilation mode) do not require an extra
63 bool isDecl = GV->hasAvailableExternallyLinkage();
64 if (GV->isDeclaration() && !GV->isMaterializable())
67 // X86-64 in PIC mode.
68 if (isPICStyleRIPRel()) {
69 // Large model never uses stubs.
70 if (TM.getCodeModel() == CodeModel::Large)
71 return X86II::MO_NO_FLAG;
73 if (isTargetDarwin()) {
74 // If symbol visibility is hidden, the extra load is not needed if
75 // target is x86-64 or the symbol is definitely defined in the current
77 if (GV->hasDefaultVisibility() &&
78 (isDecl || GV->isWeakForLinker()))
79 return X86II::MO_GOTPCREL;
80 } else if (!isTargetWin64()) {
81 assert(isTargetELF() && "Unknown rip-relative target");
83 // Extra load is needed for all externally visible.
84 if (!GV->hasLocalLinkage() && GV->hasDefaultVisibility())
85 return X86II::MO_GOTPCREL;
88 return X86II::MO_NO_FLAG;
91 if (isPICStyleGOT()) { // 32-bit ELF targets.
92 // Extra load is needed for all externally visible.
93 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
94 return X86II::MO_GOTOFF;
98 if (isPICStyleStubPIC()) { // Darwin/32 in PIC mode.
99 // Determine whether we have a stub reference and/or whether the reference
100 // is relative to the PIC base or not.
102 // If this is a strong reference to a definition, it is definitely not
104 if (!isDecl && !GV->isWeakForLinker())
105 return X86II::MO_PIC_BASE_OFFSET;
107 // Unless we have a symbol with hidden visibility, we have to go through a
108 // normal $non_lazy_ptr stub because this symbol might be resolved late.
109 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
110 return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
112 // If symbol visibility is hidden, we have a stub for common symbol
113 // references and external declarations.
114 if (isDecl || GV->hasCommonLinkage()) {
115 // Hidden $non_lazy_ptr reference.
116 return X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE;
119 // Otherwise, no stub.
120 return X86II::MO_PIC_BASE_OFFSET;
123 if (isPICStyleStubNoDynamic()) { // Darwin/32 in -mdynamic-no-pic mode.
124 // Determine whether we have a stub reference.
126 // If this is a strong reference to a definition, it is definitely not
128 if (!isDecl && !GV->isWeakForLinker())
129 return X86II::MO_NO_FLAG;
131 // Unless we have a symbol with hidden visibility, we have to go through a
132 // normal $non_lazy_ptr stub because this symbol might be resolved late.
133 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
134 return X86II::MO_DARWIN_NONLAZY;
136 // Otherwise, no stub.
137 return X86II::MO_NO_FLAG;
140 // Direct static reference to global.
141 return X86II::MO_NO_FLAG;
145 /// getBZeroEntry - This function returns the name of a function which has an
146 /// interface like the non-standard bzero function, if such a function exists on
147 /// the current subtarget and it is considered prefereable over memset with zero
148 /// passed as the second argument. Otherwise it returns null.
149 const char *X86Subtarget::getBZeroEntry() const {
150 // Darwin 10 has a __bzero entry point for this purpose.
151 if (getTargetTriple().isMacOSX() &&
152 !getTargetTriple().isMacOSXVersionLT(10, 6))
158 bool X86Subtarget::hasSinCos() const {
159 return getTargetTriple().isMacOSX() &&
160 !getTargetTriple().isMacOSXVersionLT(10, 9) &&
164 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
165 /// to immediate address.
166 bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
169 return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
172 void X86Subtarget::AutoDetectSubtargetFeatures() {
173 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
180 if (X86_MC::GetCpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) ||
184 X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
186 if ((EDX >> 15) & 1) { HasCMov = true; ToggleFeature(X86::FeatureCMOV); }
187 if ((EDX >> 23) & 1) { X86SSELevel = MMX; ToggleFeature(X86::FeatureMMX); }
188 if ((EDX >> 25) & 1) { X86SSELevel = SSE1; ToggleFeature(X86::FeatureSSE1); }
189 if ((EDX >> 26) & 1) { X86SSELevel = SSE2; ToggleFeature(X86::FeatureSSE2); }
190 if (ECX & 0x1) { X86SSELevel = SSE3; ToggleFeature(X86::FeatureSSE3); }
191 if ((ECX >> 9) & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);}
192 if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);}
193 if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);}
194 if ((ECX >> 28) & 1) { X86SSELevel = AVX; ToggleFeature(X86::FeatureAVX); }
196 bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
197 bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
199 if ((ECX >> 1) & 0x1) {
201 ToggleFeature(X86::FeaturePCLMUL);
203 if ((ECX >> 12) & 0x1) {
205 ToggleFeature(X86::FeatureFMA);
207 if (IsIntel && ((ECX >> 22) & 0x1)) {
209 ToggleFeature(X86::FeatureMOVBE);
211 if ((ECX >> 23) & 0x1) {
213 ToggleFeature(X86::FeaturePOPCNT);
215 if ((ECX >> 25) & 0x1) {
217 ToggleFeature(X86::FeatureAES);
219 if ((ECX >> 29) & 0x1) {
221 ToggleFeature(X86::FeatureF16C);
223 if (IsIntel && ((ECX >> 30) & 0x1)) {
225 ToggleFeature(X86::FeatureRDRAND);
228 if ((ECX >> 13) & 0x1) {
229 HasCmpxchg16b = true;
230 ToggleFeature(X86::FeatureCMPXCHG16B);
233 if (IsIntel || IsAMD) {
234 // Determine if bit test memory instructions are slow.
237 X86_MC::DetectFamilyModel(EAX, Family, Model);
238 if (IsAMD || (Family == 6 && Model >= 13)) {
240 ToggleFeature(X86::FeatureSlowBTMem);
243 // If it's an Intel chip since Nehalem and not an Atom chip, unaligned
244 // memory access is fast. We hard code model numbers here because they
245 // aren't strictly increasing for Intel chips it seems.
247 ((Family == 6 && Model == 0x1E) || // Nehalem: Clarksfield, Lynnfield,
249 (Family == 6 && Model == 0x1A) || // Nehalem: Bloomfield, Nehalem-EP
250 (Family == 6 && Model == 0x2E) || // Nehalem: Nehalem-EX
251 (Family == 6 && Model == 0x25) || // Westmere: Arrandale, Clarksdale
252 (Family == 6 && Model == 0x2C) || // Westmere: Gulftown, Westmere-EP
253 (Family == 6 && Model == 0x2F) || // Westmere: Westmere-EX
254 (Family == 6 && Model == 0x2A) || // SandyBridge
255 (Family == 6 && Model == 0x2D) || // SandyBridge: SandyBridge-E*
256 (Family == 6 && Model == 0x3A))) {// IvyBridge
258 ToggleFeature(X86::FeatureFastUAMem);
261 // Set processor type. Currently only Atom is detected.
263 (Model == 28 || Model == 38 || Model == 39
264 || Model == 53 || Model == 54)) {
265 X86ProcFamily = IntelAtom;
268 ToggleFeature(X86::FeatureLeaForSP);
271 unsigned MaxExtLevel;
272 X86_MC::GetCpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
274 if (MaxExtLevel >= 0x80000001) {
275 X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
276 if ((EDX >> 29) & 0x1) {
278 ToggleFeature(X86::Feature64Bit);
280 if ((ECX >> 5) & 0x1) {
282 ToggleFeature(X86::FeatureLZCNT);
285 if ((ECX >> 6) & 0x1) {
287 ToggleFeature(X86::FeatureSSE4A);
289 if ((ECX >> 11) & 0x1) {
291 ToggleFeature(X86::FeatureXOP);
293 if ((ECX >> 16) & 0x1) {
295 ToggleFeature(X86::FeatureFMA4);
302 if (!X86_MC::GetCpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX)) {
303 if (IsIntel && (EBX & 0x1)) {
305 ToggleFeature(X86::FeatureFSGSBase);
307 if ((EBX >> 3) & 0x1) {
309 ToggleFeature(X86::FeatureBMI);
311 if (IsIntel && ((EBX >> 5) & 0x1)) {
313 ToggleFeature(X86::FeatureAVX2);
315 if (IsIntel && ((EBX >> 8) & 0x1)) {
317 ToggleFeature(X86::FeatureBMI2);
319 if (IsIntel && ((EBX >> 11) & 0x1)) {
321 ToggleFeature(X86::FeatureRTM);
327 X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
328 const std::string &FS,
329 unsigned StackAlignOverride, bool is64Bit)
330 : X86GenSubtargetInfo(TT, CPU, FS)
331 , X86ProcFamily(Others)
332 , PICStyle(PICStyles::None)
333 , X86SSELevel(NoMMXSSE)
334 , X863DNowLevel(NoThreeDNow)
355 , HasVectorUAMem(false)
356 , HasCmpxchg16b(false)
358 , HasSlowDivide(false)
359 , PostRAScheduler(false)
360 , PadShortFunctions(false)
362 // FIXME: this is a known good value for Yonah. How about others?
363 , MaxInlineSizeThreshold(128)
365 , In64BitMode(is64Bit) {
366 // Determine default and user specified characteristics
367 std::string CPUName = CPU;
368 if (!FS.empty() || !CPU.empty()) {
369 if (CPUName.empty()) {
370 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
371 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
372 CPUName = sys::getHostCPUName();
378 // Make sure 64-bit features are available in 64-bit mode. (But make sure
379 // SSE2 can be turned off explicitly.)
380 std::string FullFS = FS;
383 FullFS = "+64bit,+sse2," + FullFS;
385 FullFS = "+64bit,+sse2";
388 // If feature string is not empty, parse features string.
389 ParseSubtargetFeatures(CPUName, FullFS);
391 if (CPUName.empty()) {
392 #if defined (__x86_64__) || defined(__i386__)
393 CPUName = sys::getHostCPUName();
398 // Otherwise, use CPUID to auto-detect feature set.
399 AutoDetectSubtargetFeatures();
401 // Make sure 64-bit features are available in 64-bit mode.
403 HasX86_64 = true; ToggleFeature(X86::Feature64Bit);
404 HasCMov = true; ToggleFeature(X86::FeatureCMOV);
406 if (X86SSELevel < SSE2) {
408 ToggleFeature(X86::FeatureSSE1);
409 ToggleFeature(X86::FeatureSSE2);
414 // CPUName may have been set by the CPU detection code. Make sure the
415 // new MCSchedModel is used.
416 InitMCProcessorInfo(CPUName, FS);
418 if (X86ProcFamily == IntelAtom)
419 PostRAScheduler = true;
421 InstrItins = getInstrItineraryForCPU(CPUName);
423 // It's important to keep the MCSubtargetInfo feature bits in sync with
424 // target data structure which is shared with MC code emitter, etc.
426 ToggleFeature(X86::Mode64Bit);
428 DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
429 << ", 3DNowLevel " << X863DNowLevel
430 << ", 64bit " << HasX86_64 << "\n");
431 assert((!In64BitMode || HasX86_64) &&
432 "64-bit code requested on a subtarget that doesn't support it!");
434 // Stack alignment is 16 bytes on Darwin, Linux and Solaris (both
435 // 32 and 64 bit) and for all 64-bit targets.
436 if (StackAlignOverride)
437 stackAlignment = StackAlignOverride;
438 else if (isTargetDarwin() || isTargetLinux() || isTargetSolaris() ||
443 bool X86Subtarget::enablePostRAScheduler(
444 CodeGenOpt::Level OptLevel,
445 TargetSubtargetInfo::AntiDepBreakMode& Mode,
446 RegClassVector& CriticalPathRCs) const {
447 Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
448 CriticalPathRCs.clear();
449 return PostRAScheduler && OptLevel >= CodeGenOpt::Default;