1 //===-- X86Subtarget.cpp - X86 Subtarget Information ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86 specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "subtarget"
15 #include "X86Subtarget.h"
16 #include "X86GenSubtarget.inc"
17 #include "llvm/Module.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetOptions.h"
28 static cl::opt<X86Subtarget::AsmWriterFlavorTy>
29 AsmWriterFlavor("x86-asm-syntax", cl::init(X86Subtarget::Unset),
30 cl::desc("Choose style of code to emit from X86 backend:"),
32 clEnumValN(X86Subtarget::ATT, "att", "Emit AT&T-style assembly"),
33 clEnumValN(X86Subtarget::Intel, "intel", "Emit Intel-style assembly"),
37 /// True if accessing the GV requires an extra load. For Windows, dllimported
38 /// symbols are indirect, loading the value at address GV rather then the
39 /// value of GV itself. This means that the GlobalAddress must be in the base
40 /// or index register of the address, not the GV offset field.
41 bool X86Subtarget::GVRequiresExtraLoad(const GlobalValue* GV,
42 const TargetMachine& TM,
43 bool isDirectCall) const {
44 // Windows targets only require an extra load for DLLImport linkage values,
45 // and they need these regardless of whether we're in PIC mode or not.
46 if (isTargetCygMing() || isTargetWindows())
47 return GV->hasDLLImportLinkage();
49 if (TM.getRelocationModel() == Reloc::Static ||
50 TM.getCodeModel() == CodeModel::Large)
53 if (isTargetDarwin()) {
56 bool isDecl = GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode();
57 if (GV->hasHiddenVisibility() &&
58 (Is64Bit || (!isDecl && !GV->hasCommonLinkage())))
59 // If symbol visibility is hidden, the extra load is not needed if
60 // target is x86-64 or the symbol is definitely defined in the current
63 return !isDirectCall && (isDecl || GV->isWeakForLinker());
64 } else if (isTargetELF()) {
65 // Extra load is needed for all externally visible.
68 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
75 /// True if accessing the GV requires a register. This is a superset of the
76 /// cases where GVRequiresExtraLoad is true. Some variations of PIC require
77 /// a register, but not an extra load.
78 bool X86Subtarget::GVRequiresRegister(const GlobalValue *GV,
79 const TargetMachine& TM,
80 bool isDirectCall) const {
81 if (GVRequiresExtraLoad(GV, TM, isDirectCall))
83 // Code below here need only consider cases where GVRequiresExtraLoad
85 if (TM.getRelocationModel() == Reloc::PIC_)
86 return !isDirectCall &&
87 (GV->hasLocalLinkage() || GV->hasExternalLinkage());
91 /// getBZeroEntry - This function returns the name of a function which has an
92 /// interface like the non-standard bzero function, if such a function exists on
93 /// the current subtarget and it is considered prefereable over memset with zero
94 /// passed as the second argument. Otherwise it returns null.
95 const char *X86Subtarget::getBZeroEntry() const {
96 // Darwin 10 has a __bzero entry point for this purpose.
97 if (getDarwinVers() >= 10)
103 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
104 /// to immediate address.
105 bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
108 return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
111 /// getSpecialAddressLatency - For targets where it is beneficial to
112 /// backschedule instructions that compute addresses, return a value
113 /// indicating the number of scheduling cycles of backscheduling that
114 /// should be attempted.
115 unsigned X86Subtarget::getSpecialAddressLatency() const {
116 // For x86 out-of-order targets, back-schedule address computations so
117 // that loads and stores aren't blocked.
118 // This value was chosen arbitrarily.
122 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
123 /// specified arguments. If we can't run cpuid on the host, return true.
124 bool X86::GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
125 unsigned *rECX, unsigned *rEDX) {
126 #if defined(__x86_64__) || defined(_M_AMD64)
127 #if defined(__GNUC__)
128 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
129 asm ("movq\t%%rbx, %%rsi\n\t"
131 "xchgq\t%%rbx, %%rsi\n\t"
138 #elif defined(_MSC_VER)
140 __cpuid(registers, value);
141 *rEAX = registers[0];
142 *rEBX = registers[1];
143 *rECX = registers[2];
144 *rEDX = registers[3];
147 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
148 #if defined(__GNUC__)
149 asm ("movl\t%%ebx, %%esi\n\t"
151 "xchgl\t%%ebx, %%esi\n\t"
158 #elif defined(_MSC_VER)
163 mov dword ptr [esi],eax
165 mov dword ptr [esi],ebx
167 mov dword ptr [esi],ecx
169 mov dword ptr [esi],edx
177 static void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model) {
178 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
179 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
180 if (Family == 6 || Family == 0xf) {
182 // Examine extended family ID if family ID is F.
183 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
184 // Examine extended model ID if family ID is 6 or F.
185 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
189 void X86Subtarget::AutoDetectSubtargetFeatures() {
190 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
196 if (X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
199 X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
201 if ((EDX >> 23) & 0x1) X86SSELevel = MMX;
202 if ((EDX >> 25) & 0x1) X86SSELevel = SSE1;
203 if ((EDX >> 26) & 0x1) X86SSELevel = SSE2;
204 if (ECX & 0x1) X86SSELevel = SSE3;
205 if ((ECX >> 9) & 0x1) X86SSELevel = SSSE3;
206 if ((ECX >> 19) & 0x1) X86SSELevel = SSE41;
207 if ((ECX >> 20) & 0x1) X86SSELevel = SSE42;
209 bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
210 bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
212 HasFMA3 = IsIntel && ((ECX >> 12) & 0x1);
213 HasAVX = ((ECX >> 28) & 0x1);
215 if (IsIntel || IsAMD) {
216 // Determine if bit test memory instructions are slow.
219 DetectFamilyModel(EAX, Family, Model);
220 IsBTMemSlow = IsAMD || (Family == 6 && Model >= 13);
222 X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
223 HasX86_64 = (EDX >> 29) & 0x1;
224 HasSSE4A = IsAMD && ((ECX >> 6) & 0x1);
225 HasFMA4 = IsAMD && ((ECX >> 16) & 0x1);
229 static const char *GetCurrentX86CPU() {
230 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
231 if (X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
235 DetectFamilyModel(EAX, Family, Model);
237 X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
238 bool Em64T = (EDX >> 29) & 0x1;
239 bool HasSSE3 = (ECX & 0x1);
246 X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
247 if (memcmp(text.c, "GenuineIntel", 12) == 0) {
255 case 4: return "pentium-mmx";
256 default: return "pentium";
260 case 1: return "pentiumpro";
263 case 6: return "pentium2";
267 case 11: return "pentium3";
269 case 13: return "pentium-m";
270 case 14: return "yonah";
272 case 22: // Celeron M 540
274 case 23: // 45nm: Penryn , Wolfdale, Yorkfield (XE)
276 default: return "i686";
282 case 6: // same as 4, but 65nm
283 return (Em64T) ? "nocona" : "prescott";
289 return (Em64T) ? "x86-64" : "pentium4";
296 } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
297 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
298 // appears to be no way to generate the wide variety of AMD-specific targets
299 // from the information returned from CPUID.
307 case 8: return "k6-2";
309 case 13: return "k6-3";
310 default: return "pentium";
314 case 4: return "athlon-tbird";
317 case 8: return "athlon-mp";
318 case 10: return "athlon-xp";
319 default: return "athlon";
324 default: return "k8-sse3";
328 case 1: return "opteron";
329 case 5: return "athlon-fx"; // also opteron
330 default: return "athlon64";
335 default: return "amdfam10";
345 X86Subtarget::X86Subtarget(const Module &M, const std::string &FS, bool is64Bit)
346 : AsmFlavor(AsmWriterFlavor)
347 , PICStyle(PICStyles::None)
348 , X86SSELevel(NoMMXSSE)
349 , X863DNowLevel(NoThreeDNow)
359 // FIXME: this is a known good value for Yonah. How about others?
360 , MaxInlineSizeThreshold(128)
362 , TargetType(isELF) { // Default to ELF unless otherwise specified.
364 // default to hard float ABI
365 if (FloatABIType == FloatABI::Default)
366 FloatABIType = FloatABI::Hard;
368 // Determine default and user specified characteristics
370 // If feature string is not empty, parse features string.
371 std::string CPU = GetCurrentX86CPU();
372 ParseSubtargetFeatures(FS, CPU);
373 // All X86-64 CPUs also have SSE2, however user might request no SSE via
374 // -mattr, so don't force SSELevel here.
376 // Otherwise, use CPUID to auto-detect feature set.
377 AutoDetectSubtargetFeatures();
378 // Make sure SSE2 is enabled; it is available on all X86-64 CPUs.
379 if (Is64Bit && X86SSELevel < SSE2)
383 // If requesting codegen for X86-64, make sure that 64-bit features
388 DOUT << "Subtarget features: SSELevel " << X86SSELevel
389 << ", 3DNowLevel " << X863DNowLevel
390 << ", 64bit " << HasX86_64 << "\n";
391 assert((!Is64Bit || HasX86_64) &&
392 "64-bit code requested on a subtarget that doesn't support it!");
394 // Set the boolean corresponding to the current target triple, or the default
395 // if one cannot be determined, to true.
396 const std::string& TT = M.getTargetTriple();
397 if (TT.length() > 5) {
399 if ((Pos = TT.find("-darwin")) != std::string::npos) {
400 TargetType = isDarwin;
402 // Compute the darwin version number.
403 if (isdigit(TT[Pos+7]))
404 DarwinVers = atoi(&TT[Pos+7]);
406 DarwinVers = 8; // Minimum supported darwin is Tiger.
407 } else if (TT.find("linux") != std::string::npos) {
408 // Linux doesn't imply ELF, but we don't currently support anything else.
411 } else if (TT.find("cygwin") != std::string::npos) {
412 TargetType = isCygwin;
413 } else if (TT.find("mingw") != std::string::npos) {
414 TargetType = isMingw;
415 } else if (TT.find("win32") != std::string::npos) {
416 TargetType = isWindows;
417 } else if (TT.find("windows") != std::string::npos) {
418 TargetType = isWindows;
420 else if (TT.find("-cl") != std::string::npos) {
421 TargetType = isDarwin;
424 } else if (TT.empty()) {
425 #if defined(__CYGWIN__)
426 TargetType = isCygwin;
427 #elif defined(__MINGW32__) || defined(__MINGW64__)
428 TargetType = isMingw;
429 #elif defined(__APPLE__)
430 TargetType = isDarwin;
431 #if __APPLE_CC__ > 5400
432 DarwinVers = 9; // GCC 5400+ is Leopard.
434 DarwinVers = 8; // Minimum supported darwin is Tiger.
437 #elif defined(_WIN32) || defined(_WIN64)
438 TargetType = isWindows;
439 #elif defined(__linux__)
440 // Linux doesn't imply ELF, but we don't currently support anything else.
446 // If the asm syntax hasn't been overridden on the command line, use whatever
448 if (AsmFlavor == X86Subtarget::Unset) {
449 AsmFlavor = (TargetType == isWindows)
450 ? X86Subtarget::Intel : X86Subtarget::ATT;
453 // Stack alignment is 16 bytes on Darwin (both 32 and 64 bit) and for all 64
455 if (TargetType == isDarwin || Is64Bit)
459 stackAlignment = StackAlignment;