1 //===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "subtarget"
15 #include "X86Subtarget.h"
16 #include "X86InstrInfo.h"
17 #include "llvm/GlobalValue.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Support/raw_ostream.h"
21 #include "llvm/Support/Host.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/ADT/SmallVector.h"
26 #define GET_SUBTARGETINFO_TARGET_DESC
27 #define GET_SUBTARGETINFO_CTOR
28 #include "X86GenSubtargetInfo.inc"
36 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
37 /// current subtarget according to how we should reference it in a non-pcrel
39 unsigned char X86Subtarget::
40 ClassifyBlockAddressReference() const {
41 if (isPICStyleGOT()) // 32-bit ELF targets.
42 return X86II::MO_GOTOFF;
44 if (isPICStyleStubPIC()) // Darwin/32 in PIC mode.
45 return X86II::MO_PIC_BASE_OFFSET;
47 // Direct static reference to label.
48 return X86II::MO_NO_FLAG;
51 /// ClassifyGlobalReference - Classify a global variable reference for the
52 /// current subtarget according to how we should reference it in a non-pcrel
54 unsigned char X86Subtarget::
55 ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
56 // DLLImport only exists on windows, it is implemented as a load from a
58 if (GV->hasDLLImportLinkage())
59 return X86II::MO_DLLIMPORT;
61 // Determine whether this is a reference to a definition or a declaration.
62 // Materializable GVs (in JIT lazy compilation mode) do not require an extra
64 bool isDecl = GV->hasAvailableExternallyLinkage();
65 if (GV->isDeclaration() && !GV->isMaterializable())
68 // X86-64 in PIC mode.
69 if (isPICStyleRIPRel()) {
70 // Large model never uses stubs.
71 if (TM.getCodeModel() == CodeModel::Large)
72 return X86II::MO_NO_FLAG;
74 if (isTargetDarwin()) {
75 // If symbol visibility is hidden, the extra load is not needed if
76 // target is x86-64 or the symbol is definitely defined in the current
78 if (GV->hasDefaultVisibility() &&
79 (isDecl || GV->isWeakForLinker()))
80 return X86II::MO_GOTPCREL;
81 } else if (!isTargetWin64()) {
82 assert(isTargetELF() && "Unknown rip-relative target");
84 // Extra load is needed for all externally visible.
85 if (!GV->hasLocalLinkage() && GV->hasDefaultVisibility())
86 return X86II::MO_GOTPCREL;
89 return X86II::MO_NO_FLAG;
92 if (isPICStyleGOT()) { // 32-bit ELF targets.
93 // Extra load is needed for all externally visible.
94 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
95 return X86II::MO_GOTOFF;
99 if (isPICStyleStubPIC()) { // Darwin/32 in PIC mode.
100 // Determine whether we have a stub reference and/or whether the reference
101 // is relative to the PIC base or not.
103 // If this is a strong reference to a definition, it is definitely not
105 if (!isDecl && !GV->isWeakForLinker())
106 return X86II::MO_PIC_BASE_OFFSET;
108 // Unless we have a symbol with hidden visibility, we have to go through a
109 // normal $non_lazy_ptr stub because this symbol might be resolved late.
110 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
111 return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
113 // If symbol visibility is hidden, we have a stub for common symbol
114 // references and external declarations.
115 if (isDecl || GV->hasCommonLinkage()) {
116 // Hidden $non_lazy_ptr reference.
117 return X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE;
120 // Otherwise, no stub.
121 return X86II::MO_PIC_BASE_OFFSET;
124 if (isPICStyleStubNoDynamic()) { // Darwin/32 in -mdynamic-no-pic mode.
125 // Determine whether we have a stub reference.
127 // If this is a strong reference to a definition, it is definitely not
129 if (!isDecl && !GV->isWeakForLinker())
130 return X86II::MO_NO_FLAG;
132 // Unless we have a symbol with hidden visibility, we have to go through a
133 // normal $non_lazy_ptr stub because this symbol might be resolved late.
134 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
135 return X86II::MO_DARWIN_NONLAZY;
137 // Otherwise, no stub.
138 return X86II::MO_NO_FLAG;
141 // Direct static reference to global.
142 return X86II::MO_NO_FLAG;
146 /// getBZeroEntry - This function returns the name of a function which has an
147 /// interface like the non-standard bzero function, if such a function exists on
148 /// the current subtarget and it is considered prefereable over memset with zero
149 /// passed as the second argument. Otherwise it returns null.
150 const char *X86Subtarget::getBZeroEntry() const {
151 // Darwin 10 has a __bzero entry point for this purpose.
152 if (getTargetTriple().isMacOSX() &&
153 !getTargetTriple().isMacOSXVersionLT(10, 6))
159 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
160 /// to immediate address.
161 bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
164 return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
167 /// getSpecialAddressLatency - For targets where it is beneficial to
168 /// backschedule instructions that compute addresses, return a value
169 /// indicating the number of scheduling cycles of backscheduling that
170 /// should be attempted.
171 unsigned X86Subtarget::getSpecialAddressLatency() const {
172 // For x86 out-of-order targets, back-schedule address computations so
173 // that loads and stores aren't blocked.
174 // This value was chosen arbitrarily.
178 void X86Subtarget::AutoDetectSubtargetFeatures() {
179 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
186 if (X86_MC::GetCpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) ||
190 X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
192 if ((EDX >> 15) & 1) { HasCMov = true; ToggleFeature(X86::FeatureCMOV); }
193 if ((EDX >> 23) & 1) { X86SSELevel = MMX; ToggleFeature(X86::FeatureMMX); }
194 if ((EDX >> 25) & 1) { X86SSELevel = SSE1; ToggleFeature(X86::FeatureSSE1); }
195 if ((EDX >> 26) & 1) { X86SSELevel = SSE2; ToggleFeature(X86::FeatureSSE2); }
196 if (ECX & 0x1) { X86SSELevel = SSE3; ToggleFeature(X86::FeatureSSE3); }
197 if ((ECX >> 9) & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);}
198 if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);}
199 if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);}
200 // FIXME: AVX codegen support is not ready.
201 //if ((ECX >> 28) & 1) { X86SSELevel = AVX; ToggleFeature(X86::FeatureAVX); }
203 bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
204 bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
206 if (IsIntel && ((ECX >> 1) & 0x1)) {
208 ToggleFeature(X86::FeatureCLMUL);
210 if (IsIntel && ((ECX >> 12) & 0x1)) {
212 ToggleFeature(X86::FeatureFMA3);
214 if (IsIntel && ((ECX >> 22) & 0x1)) {
216 ToggleFeature(X86::FeatureMOVBE);
218 if (IsIntel && ((ECX >> 23) & 0x1)) {
220 ToggleFeature(X86::FeaturePOPCNT);
222 if (IsIntel && ((ECX >> 25) & 0x1)) {
224 ToggleFeature(X86::FeatureAES);
226 if (IsIntel && ((ECX >> 29) & 0x1)) {
228 ToggleFeature(X86::FeatureF16C);
230 if (IsIntel && ((ECX >> 30) & 0x1)) {
232 ToggleFeature(X86::FeatureRDRAND);
235 if ((ECX >> 13) & 0x1) {
236 HasCmpxchg16b = true;
237 ToggleFeature(X86::FeatureCMPXCHG16B);
240 if (IsIntel || IsAMD) {
241 // Determine if bit test memory instructions are slow.
244 X86_MC::DetectFamilyModel(EAX, Family, Model);
245 if (IsAMD || (Family == 6 && Model >= 13)) {
247 ToggleFeature(X86::FeatureSlowBTMem);
249 // If it's Nehalem, unaligned memory access is fast.
250 // FIXME: Nehalem is family 6. Also include Westmere and later processors?
251 if (Family == 15 && Model == 26) {
253 ToggleFeature(X86::FeatureFastUAMem);
256 unsigned MaxExtLevel;
257 X86_MC::GetCpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
259 if (MaxExtLevel >= 0x80000001) {
260 X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
261 if ((EDX >> 29) & 0x1) {
263 ToggleFeature(X86::Feature64Bit);
265 if ((ECX >> 5) & 0x1) {
267 ToggleFeature(X86::FeatureLZCNT);
270 if ((ECX >> 6) & 0x1) {
272 ToggleFeature(X86::FeatureSSE4A);
274 if ((ECX >> 11) & 0x1) {
276 ToggleFeature(X86::FeatureXOP);
278 if ((ECX >> 16) & 0x1) {
280 ToggleFeature(X86::FeatureFMA4);
286 if (IsIntel && MaxLevel >= 7) {
287 if (!X86_MC::GetCpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX)) {
290 ToggleFeature(X86::FeatureFSGSBase);
292 if ((EBX >> 3) & 0x1) {
294 ToggleFeature(X86::FeatureBMI);
296 // FIXME: AVX2 codegen support is not ready.
297 //if ((EBX >> 5) & 0x1) {
298 // X86SSELevel = AVX2;;
299 // ToggleFeature(X86::FeatureAVX2);
301 if ((EBX >> 8) & 0x1) {
303 ToggleFeature(X86::FeatureBMI2);
309 X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
310 const std::string &FS,
311 unsigned StackAlignOverride, bool is64Bit)
312 : X86GenSubtargetInfo(TT, CPU, FS)
313 , PICStyle(PICStyles::None)
314 , X86SSELevel(NoMMXSSE)
315 , X863DNowLevel(NoThreeDNow)
334 , HasVectorUAMem(false)
335 , HasCmpxchg16b(false)
337 // FIXME: this is a known good value for Yonah. How about others?
338 , MaxInlineSizeThreshold(128)
340 , In64BitMode(is64Bit) {
341 // Determine default and user specified characteristics
342 if (!FS.empty() || !CPU.empty()) {
343 std::string CPUName = CPU;
344 if (CPUName.empty()) {
345 #if defined (__x86_64__) || defined(__i386__)
346 CPUName = sys::getHostCPUName();
352 // Make sure 64-bit features are available in 64-bit mode. (But make sure
353 // SSE2 can be turned off explicitly.)
354 std::string FullFS = FS;
357 FullFS = "+64bit,+sse2," + FullFS;
359 FullFS = "+64bit,+sse2";
362 // If feature string is not empty, parse features string.
363 ParseSubtargetFeatures(CPUName, FullFS);
365 // Otherwise, use CPUID to auto-detect feature set.
366 AutoDetectSubtargetFeatures();
368 // Make sure 64-bit features are available in 64-bit mode.
370 HasX86_64 = true; ToggleFeature(X86::Feature64Bit);
371 HasCMov = true; ToggleFeature(X86::FeatureCMOV);
373 if (X86SSELevel < SSE2) {
375 ToggleFeature(X86::FeatureSSE1);
376 ToggleFeature(X86::FeatureSSE2);
381 // It's important to keep the MCSubtargetInfo feature bits in sync with
382 // target data structure which is shared with MC code emitter, etc.
384 ToggleFeature(X86::Mode64Bit);
386 DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
387 << ", 3DNowLevel " << X863DNowLevel
388 << ", 64bit " << HasX86_64 << "\n");
389 assert((!In64BitMode || HasX86_64) &&
390 "64-bit code requested on a subtarget that doesn't support it!");
392 // Stack alignment is 16 bytes on Darwin, FreeBSD, Linux and Solaris (both
393 // 32 and 64 bit) and for all 64-bit targets.
394 if (StackAlignOverride)
395 stackAlignment = StackAlignOverride;
396 else if (isTargetDarwin() || isTargetFreeBSD() || isTargetLinux() ||
397 isTargetSolaris() || In64BitMode)