1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86SUBTARGET_H
15 #define X86SUBTARGET_H
17 #include "llvm/ADT/Triple.h"
18 #include "llvm/IR/CallingConv.h"
19 #include "llvm/Target/TargetSubtargetInfo.h"
22 #define GET_SUBTARGETINFO_HEADER
23 #include "X86GenSubtargetInfo.inc"
30 /// PICStyles - The X86 backend supports a number of different styles of PIC.
34 StubPIC, // Used on i386-darwin in -fPIC mode.
35 StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
36 GOT, // Used on many 32-bit unices in -fPIC mode.
37 RIPRel, // Used on X86-64 when not in -static mode.
38 None // Set when in -static mode (not PIC or DynamicNoPIC mode).
42 class X86Subtarget : public X86GenSubtargetInfo {
45 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
49 NoThreeDNow, ThreeDNow, ThreeDNowA
52 enum X86ProcFamilyEnum {
56 /// X86ProcFamily - X86 processor family: Intel Atom, and others
57 X86ProcFamilyEnum X86ProcFamily;
59 /// PICStyle - Which PIC style to use
61 PICStyles::Style PICStyle;
63 /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
65 X86SSEEnum X86SSELevel;
67 /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
69 X863DNowEnum X863DNowLevel;
71 /// HasCMov - True if this processor has conditional move instructions
72 /// (generally pentium pro+).
75 /// HasX86_64 - True if the processor supports X86-64 instructions.
79 /// HasPOPCNT - True if the processor supports POPCNT.
82 /// HasSSE4A - True if the processor supports SSE4A instructions.
85 /// HasAES - Target has AES instructions
88 /// HasPCLMUL - Target has carry-less multiplication
91 /// HasFMA - Target has 3-operand fused multiply-add
94 /// HasFMA4 - Target has 4-operand fused multiply-add
97 /// HasXOP - Target has XOP instructions
100 /// HasMOVBE - True if the processor has the MOVBE instruction.
103 /// HasRDRAND - True if the processor has the RDRAND instruction.
106 /// HasF16C - Processor has 16-bit floating point conversion instructions.
109 /// HasFSGSBase - Processor has FS/GS base insturctions.
112 /// HasLZCNT - Processor has LZCNT instruction.
115 /// HasBMI - Processor has BMI1 instructions.
118 /// HasBMI2 - Processor has BMI2 instructions.
121 /// HasRTM - Processor has RTM instructions.
124 /// HasADX - Processor has ADX instructions.
127 /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
130 /// IsUAMemFast - True if unaligned memory access is fast.
133 /// HasVectorUAMem - True if SIMD operations can have unaligned memory
134 /// operands. This may require setting a feature bit in the processor.
137 /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction;
138 /// this is true for most x86-64 chips, but not the first AMD chips.
141 /// UseLeaForSP - True if the LEA instruction should be used for adjusting
142 /// the stack pointer. This is an optimization for Intel Atom processors.
145 /// HasSlowDivide - True if smaller divides are significantly faster than
146 /// full divides and should be used when possible.
149 /// PostRAScheduler - True if using post-register-allocation scheduler.
150 bool PostRAScheduler;
152 /// PadShortFunctions - True if the short functions should be padded to prevent
153 /// a stall when returning too early.
154 bool PadShortFunctions;
156 /// stackAlignment - The minimum alignment known to hold of the stack frame on
157 /// entry to the function and which must be maintained by every function.
158 unsigned stackAlignment;
160 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
162 unsigned MaxInlineSizeThreshold;
164 /// TargetTriple - What processor and OS we're targeting.
167 /// Instruction itineraries for scheduling
168 InstrItineraryData InstrItins;
171 /// In64BitMode - True if compiling for 64-bit, false for 32-bit.
176 /// This constructor initializes the data members to match that
177 /// of the specified triple.
179 X86Subtarget(const std::string &TT, const std::string &CPU,
180 const std::string &FS,
181 unsigned StackAlignOverride, bool is64Bit);
183 /// getStackAlignment - Returns the minimum alignment known to hold of the
184 /// stack frame on entry to the function and which must be maintained by every
185 /// function for this subtarget.
186 unsigned getStackAlignment() const { return stackAlignment; }
188 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
189 /// that still makes it profitable to inline the call.
190 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
192 /// ParseSubtargetFeatures - Parses features string setting specified
193 /// subtarget options. Definition of function is auto generated by tblgen.
194 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
196 /// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID
198 void AutoDetectSubtargetFeatures();
200 /// Is this x86_64? (disregarding specific ABI / programming model)
201 bool is64Bit() const {
205 /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
206 bool isTarget64BitILP32() const {
207 return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32);
210 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
211 bool isTarget64BitLP64() const {
212 return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32);
215 PICStyles::Style getPICStyle() const { return PICStyle; }
216 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
218 bool hasCMov() const { return HasCMov; }
219 bool hasMMX() const { return X86SSELevel >= MMX; }
220 bool hasSSE1() const { return X86SSELevel >= SSE1; }
221 bool hasSSE2() const { return X86SSELevel >= SSE2; }
222 bool hasSSE3() const { return X86SSELevel >= SSE3; }
223 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
224 bool hasSSE41() const { return X86SSELevel >= SSE41; }
225 bool hasSSE42() const { return X86SSELevel >= SSE42; }
226 bool hasAVX() const { return X86SSELevel >= AVX; }
227 bool hasAVX2() const { return X86SSELevel >= AVX2; }
228 bool hasFp256() const { return hasAVX(); }
229 bool hasInt256() const { return hasAVX2(); }
230 bool hasSSE4A() const { return HasSSE4A; }
231 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
232 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
233 bool hasPOPCNT() const { return HasPOPCNT; }
234 bool hasAES() const { return HasAES; }
235 bool hasPCLMUL() const { return HasPCLMUL; }
236 bool hasFMA() const { return HasFMA; }
237 // FIXME: Favor FMA when both are enabled. Is this the right thing to do?
238 bool hasFMA4() const { return HasFMA4 && !HasFMA; }
239 bool hasXOP() const { return HasXOP; }
240 bool hasMOVBE() const { return HasMOVBE; }
241 bool hasRDRAND() const { return HasRDRAND; }
242 bool hasF16C() const { return HasF16C; }
243 bool hasFSGSBase() const { return HasFSGSBase; }
244 bool hasLZCNT() const { return HasLZCNT; }
245 bool hasBMI() const { return HasBMI; }
246 bool hasBMI2() const { return HasBMI2; }
247 bool hasRTM() const { return HasRTM; }
248 bool hasADX() const { return HasADX; }
249 bool isBTMemSlow() const { return IsBTMemSlow; }
250 bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
251 bool hasVectorUAMem() const { return HasVectorUAMem; }
252 bool hasCmpxchg16b() const { return HasCmpxchg16b; }
253 bool useLeaForSP() const { return UseLeaForSP; }
254 bool hasSlowDivide() const { return HasSlowDivide; }
255 bool padShortFunctions() const { return PadShortFunctions; }
257 bool isAtom() const { return X86ProcFamily == IntelAtom; }
259 const Triple &getTargetTriple() const { return TargetTriple; }
261 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
262 bool isTargetFreeBSD() const {
263 return TargetTriple.getOS() == Triple::FreeBSD;
265 bool isTargetSolaris() const {
266 return TargetTriple.getOS() == Triple::Solaris;
268 bool isTargetELF() const {
269 return (TargetTriple.getEnvironment() == Triple::ELF ||
270 TargetTriple.isOSBinFormatELF());
272 bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; }
273 bool isTargetNaCl() const {
274 return TargetTriple.getOS() == Triple::NaCl;
276 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
277 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
278 bool isTargetWindows() const { return TargetTriple.getOS() == Triple::Win32; }
279 bool isTargetMingw() const { return TargetTriple.getOS() == Triple::MinGW32; }
280 bool isTargetCygwin() const { return TargetTriple.getOS() == Triple::Cygwin; }
281 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
282 bool isTargetCOFF() const {
283 return (TargetTriple.getEnvironment() != Triple::ELF &&
284 TargetTriple.isOSBinFormatCOFF());
286 bool isTargetEnvMacho() const { return TargetTriple.isEnvironmentMachO(); }
288 bool isTargetWin64() const {
289 // FIXME: x86_64-cygwin has not been released yet.
290 return In64BitMode && TargetTriple.isOSWindows();
293 bool isTargetWin32() const {
294 // FIXME: Cygwin is included for isTargetWin64 -- should it be included
296 return !In64BitMode && (isTargetMingw() || isTargetWindows());
299 bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
300 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
301 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
303 bool isPICStyleStubPIC() const {
304 return PICStyle == PICStyles::StubPIC;
307 bool isPICStyleStubNoDynamic() const {
308 return PICStyle == PICStyles::StubDynamicNoPIC;
310 bool isPICStyleStubAny() const {
311 return PICStyle == PICStyles::StubDynamicNoPIC ||
312 PICStyle == PICStyles::StubPIC; }
314 /// ClassifyGlobalReference - Classify a global variable reference for the
315 /// current subtarget according to how we should reference it in a non-pcrel
317 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
318 const TargetMachine &TM)const;
320 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
321 /// current subtarget according to how we should reference it in a non-pcrel
323 unsigned char ClassifyBlockAddressReference() const;
325 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
326 /// to immediate address.
327 bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
329 /// This function returns the name of a function which has an interface
330 /// like the non-standard bzero function, if such a function exists on
331 /// the current subtarget and it is considered prefereable over
332 /// memset with zero passed as the second argument. Otherwise it
334 const char *getBZeroEntry() const;
336 /// This function returns true if the target has sincos() routine in its
337 /// compiler runtime or math libraries.
338 bool hasSinCos() const;
340 /// enablePostRAScheduler - run for Atom optimization.
341 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
342 TargetSubtargetInfo::AntiDepBreakMode& Mode,
343 RegClassVector& CriticalPathRCs) const;
345 bool postRAScheduler() const { return PostRAScheduler; }
347 /// getInstrItins = Return the instruction itineraries based on the
348 /// subtarget selection.
349 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
352 } // End llvm namespace