1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86SUBTARGET_H
15 #define X86SUBTARGET_H
17 #include "llvm/CallingConv.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/Target/TargetSubtargetInfo.h"
22 #define GET_SUBTARGETINFO_HEADER
23 #include "X86GenSubtargetInfo.inc"
30 /// PICStyles - The X86 backend supports a number of different styles of PIC.
34 StubPIC, // Used on i386-darwin in -fPIC mode.
35 StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
36 GOT, // Used on many 32-bit unices in -fPIC mode.
37 RIPRel, // Used on X86-64 when not in -static mode.
38 None // Set when in -static mode (not PIC or DynamicNoPIC mode).
42 class X86Subtarget : public X86GenSubtargetInfo {
45 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
49 NoThreeDNow, ThreeDNow, ThreeDNowA
52 enum X86ProcFamilyEnum {
56 /// X86ProcFamily - X86 processor family: Intel Atom, and others
57 X86ProcFamilyEnum X86ProcFamily;
59 /// PICStyle - Which PIC style to use
61 PICStyles::Style PICStyle;
63 /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
65 X86SSEEnum X86SSELevel;
67 /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
69 X863DNowEnum X863DNowLevel;
71 /// HasCMov - True if this processor has conditional move instructions
72 /// (generally pentium pro+).
75 /// HasX86_64 - True if the processor supports X86-64 instructions.
79 /// HasPOPCNT - True if the processor supports POPCNT.
82 /// HasSSE4A - True if the processor supports SSE4A instructions.
85 /// HasAES - Target has AES instructions
88 /// HasPCLMUL - Target has carry-less multiplication
91 /// HasFMA - Target has 3-operand fused multiply-add
94 /// HasFMA4 - Target has 4-operand fused multiply-add
97 /// HasXOP - Target has XOP instructions
100 /// HasMOVBE - True if the processor has the MOVBE instruction.
103 /// HasRDRAND - True if the processor has the RDRAND instruction.
106 /// HasF16C - Processor has 16-bit floating point conversion instructions.
109 /// HasFSGSBase - Processor has FS/GS base insturctions.
112 /// HasLZCNT - Processor has LZCNT instruction.
115 /// HasBMI - Processor has BMI1 instructions.
118 /// HasBMI2 - Processor has BMI2 instructions.
121 /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
124 /// IsUAMemFast - True if unaligned memory access is fast.
127 /// HasVectorUAMem - True if SIMD operations can have unaligned memory
128 /// operands. This may require setting a feature bit in the processor.
131 /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction;
132 /// this is true for most x86-64 chips, but not the first AMD chips.
135 /// UseLeaForSP - True if the LEA instruction should be used for adjusting
136 /// the stack pointer. This is an optimization for Intel Atom processors.
139 /// PostRAScheduler - True if using post-register-allocation scheduler.
140 bool PostRAScheduler;
142 /// stackAlignment - The minimum alignment known to hold of the stack frame on
143 /// entry to the function and which must be maintained by every function.
144 unsigned stackAlignment;
146 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
148 unsigned MaxInlineSizeThreshold;
150 /// TargetTriple - What processor and OS we're targeting.
153 /// Instruction itineraries for scheduling
154 InstrItineraryData InstrItins;
157 /// In64BitMode - True if compiling for 64-bit, false for 32-bit.
162 /// This constructor initializes the data members to match that
163 /// of the specified triple.
165 X86Subtarget(const std::string &TT, const std::string &CPU,
166 const std::string &FS,
167 unsigned StackAlignOverride, bool is64Bit);
169 /// getStackAlignment - Returns the minimum alignment known to hold of the
170 /// stack frame on entry to the function and which must be maintained by every
171 /// function for this subtarget.
172 unsigned getStackAlignment() const { return stackAlignment; }
174 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
175 /// that still makes it profitable to inline the call.
176 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
178 /// ParseSubtargetFeatures - Parses features string setting specified
179 /// subtarget options. Definition of function is auto generated by tblgen.
180 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
182 /// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID
184 void AutoDetectSubtargetFeatures();
186 bool is64Bit() const { return In64BitMode; }
188 PICStyles::Style getPICStyle() const { return PICStyle; }
189 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
191 bool hasCMov() const { return HasCMov; }
192 bool hasMMX() const { return X86SSELevel >= MMX; }
193 bool hasSSE1() const { return X86SSELevel >= SSE1; }
194 bool hasSSE2() const { return X86SSELevel >= SSE2; }
195 bool hasSSE3() const { return X86SSELevel >= SSE3; }
196 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
197 bool hasSSE41() const { return X86SSELevel >= SSE41; }
198 bool hasSSE42() const { return X86SSELevel >= SSE42; }
199 bool hasAVX() const { return X86SSELevel >= AVX; }
200 bool hasAVX2() const { return X86SSELevel >= AVX2; }
201 bool hasSSE4A() const { return HasSSE4A; }
202 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
203 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
204 bool hasPOPCNT() const { return HasPOPCNT; }
205 bool hasAES() const { return HasAES; }
206 bool hasPCLMUL() const { return HasPCLMUL; }
207 bool hasFMA() const { return HasFMA; }
208 // FIXME: Favor FMA when both are enabled. Is this right?
209 bool hasFMA4() const { return HasFMA4 && !HasFMA; }
210 bool hasXOP() const { return HasXOP; }
211 bool hasMOVBE() const { return HasMOVBE; }
212 bool hasRDRAND() const { return HasRDRAND; }
213 bool hasF16C() const { return HasF16C; }
214 bool hasFSGSBase() const { return HasFSGSBase; }
215 bool hasLZCNT() const { return HasLZCNT; }
216 bool hasBMI() const { return HasBMI; }
217 bool hasBMI2() const { return HasBMI2; }
218 bool isBTMemSlow() const { return IsBTMemSlow; }
219 bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
220 bool hasVectorUAMem() const { return HasVectorUAMem; }
221 bool hasCmpxchg16b() const { return HasCmpxchg16b; }
222 bool useLeaForSP() const { return UseLeaForSP; }
224 bool isAtom() const { return X86ProcFamily == IntelAtom; }
226 const Triple &getTargetTriple() const { return TargetTriple; }
228 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
229 bool isTargetFreeBSD() const {
230 return TargetTriple.getOS() == Triple::FreeBSD;
232 bool isTargetSolaris() const {
233 return TargetTriple.getOS() == Triple::Solaris;
236 // ELF is a reasonably sane default and the only other X86 targets we
237 // support are Darwin and Windows. Just use "not those".
238 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
239 bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; }
240 bool isTargetNaCl() const {
241 return TargetTriple.getOS() == Triple::NativeClient;
243 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
244 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
245 bool isTargetWindows() const { return TargetTriple.getOS() == Triple::Win32; }
246 bool isTargetMingw() const { return TargetTriple.getOS() == Triple::MinGW32; }
247 bool isTargetCygwin() const { return TargetTriple.getOS() == Triple::Cygwin; }
248 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
249 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
250 bool isTargetEnvMacho() const { return TargetTriple.isEnvironmentMachO(); }
252 bool isTargetWin64() const {
253 // FIXME: x86_64-cygwin has not been released yet.
254 return In64BitMode && TargetTriple.isOSWindows();
257 bool isTargetWin32() const {
258 // FIXME: Cygwin is included for isTargetWin64 -- should it be included
260 return !In64BitMode && (isTargetMingw() || isTargetWindows());
263 bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
264 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
265 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
267 bool isPICStyleStubPIC() const {
268 return PICStyle == PICStyles::StubPIC;
271 bool isPICStyleStubNoDynamic() const {
272 return PICStyle == PICStyles::StubDynamicNoPIC;
274 bool isPICStyleStubAny() const {
275 return PICStyle == PICStyles::StubDynamicNoPIC ||
276 PICStyle == PICStyles::StubPIC; }
278 /// ClassifyGlobalReference - Classify a global variable reference for the
279 /// current subtarget according to how we should reference it in a non-pcrel
281 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
282 const TargetMachine &TM)const;
284 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
285 /// current subtarget according to how we should reference it in a non-pcrel
287 unsigned char ClassifyBlockAddressReference() const;
289 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
290 /// to immediate address.
291 bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
293 /// This function returns the name of a function which has an interface
294 /// like the non-standard bzero function, if such a function exists on
295 /// the current subtarget and it is considered prefereable over
296 /// memset with zero passed as the second argument. Otherwise it
298 const char *getBZeroEntry() const;
300 /// getSpecialAddressLatency - For targets where it is beneficial to
301 /// backschedule instructions that compute addresses, return a value
302 /// indicating the number of scheduling cycles of backscheduling that
303 /// should be attempted.
304 unsigned getSpecialAddressLatency() const;
306 /// enablePostRAScheduler - run for Atom optimization.
307 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
308 TargetSubtargetInfo::AntiDepBreakMode& Mode,
309 RegClassVector& CriticalPathRCs) const;
311 bool postRAScheduler() const { return PostRAScheduler; }
313 /// getInstrItins = Return the instruction itineraries based on the
314 /// subtarget selection.
315 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
318 } // End llvm namespace