1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
15 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
17 #include "X86FrameLowering.h"
18 #include "X86ISelLowering.h"
19 #include "X86InstrInfo.h"
20 #include "X86JITInfo.h"
21 #include "X86SelectionDAGInfo.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/IR/CallingConv.h"
24 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "X86GenSubtargetInfo.inc"
35 /// PICStyles - The X86 backend supports a number of different styles of PIC.
39 StubPIC, // Used on i386-darwin in -fPIC mode.
40 StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
41 GOT, // Used on many 32-bit unices in -fPIC mode.
42 RIPRel, // Used on X86-64 when not in -static mode.
43 None // Set when in -static mode (not PIC or DynamicNoPIC mode).
47 class X86Subtarget final : public X86GenSubtargetInfo {
51 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
55 NoThreeDNow, ThreeDNow, ThreeDNowA
58 enum X86ProcFamilyEnum {
59 Others, IntelAtom, IntelSLM
62 /// X86ProcFamily - X86 processor family: Intel Atom, and others
63 X86ProcFamilyEnum X86ProcFamily;
65 /// PICStyle - Which PIC style to use
67 PICStyles::Style PICStyle;
69 /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
71 X86SSEEnum X86SSELevel;
73 /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
75 X863DNowEnum X863DNowLevel;
77 /// HasCMov - True if this processor has conditional move instructions
78 /// (generally pentium pro+).
81 /// HasX86_64 - True if the processor supports X86-64 instructions.
85 /// HasPOPCNT - True if the processor supports POPCNT.
88 /// HasSSE4A - True if the processor supports SSE4A instructions.
91 /// HasAES - Target has AES instructions
94 /// HasPCLMUL - Target has carry-less multiplication
97 /// HasFMA - Target has 3-operand fused multiply-add
100 /// HasFMA4 - Target has 4-operand fused multiply-add
103 /// HasXOP - Target has XOP instructions
106 /// HasTBM - Target has TBM instructions.
109 /// HasMOVBE - True if the processor has the MOVBE instruction.
112 /// HasRDRAND - True if the processor has the RDRAND instruction.
115 /// HasF16C - Processor has 16-bit floating point conversion instructions.
118 /// HasFSGSBase - Processor has FS/GS base insturctions.
121 /// HasLZCNT - Processor has LZCNT instruction.
124 /// HasBMI - Processor has BMI1 instructions.
127 /// HasBMI2 - Processor has BMI2 instructions.
130 /// HasRTM - Processor has RTM instructions.
133 /// HasHLE - Processor has HLE.
136 /// HasADX - Processor has ADX instructions.
139 /// HasSHA - Processor has SHA instructions.
142 /// HasSGX - Processor has SGX instructions.
145 /// HasPRFCHW - Processor has PRFCHW instructions.
148 /// HasRDSEED - Processor has RDSEED instructions.
151 /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
154 /// IsSHLDSlow - True if SHLD instructions are slow.
157 /// IsUAMemFast - True if unaligned memory access is fast.
160 /// HasVectorUAMem - True if SIMD operations can have unaligned memory
161 /// operands. This may require setting a feature bit in the processor.
164 /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction;
165 /// this is true for most x86-64 chips, but not the first AMD chips.
168 /// UseLeaForSP - True if the LEA instruction should be used for adjusting
169 /// the stack pointer. This is an optimization for Intel Atom processors.
172 /// HasSlowDivide - True if smaller divides are significantly faster than
173 /// full divides and should be used when possible.
176 /// PadShortFunctions - True if the short functions should be padded to prevent
177 /// a stall when returning too early.
178 bool PadShortFunctions;
180 /// CallRegIndirect - True if the Calls with memory reference should be converted
181 /// to a register-based indirect call.
182 bool CallRegIndirect;
183 /// LEAUsesAG - True if the LEA instruction inputs have to be ready at
184 /// address generation (AG) time.
187 /// SlowLEA - True if the LEA instruction with certain arguments is slow
190 /// SlowIncDec - True if INC and DEC instructions are slow when writing to flags
193 /// Processor has AVX-512 PreFetch Instructions
196 /// Processor has AVX-512 Exponential and Reciprocal Instructions
199 /// Processor has AVX-512 Conflict Detection Instructions
202 /// Processor has AVX-512 Doubleword and Quadword instructions
205 /// Processor has AVX-512 Byte and Word instructions
208 /// Processor has AVX-512 Vector Length eXtenstions
211 /// stackAlignment - The minimum alignment known to hold of the stack frame on
212 /// entry to the function and which must be maintained by every function.
213 unsigned stackAlignment;
215 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
217 unsigned MaxInlineSizeThreshold;
219 /// TargetTriple - What processor and OS we're targeting.
222 /// Instruction itineraries for scheduling
223 InstrItineraryData InstrItins;
226 // Calculates type size & alignment
229 /// StackAlignOverride - Override the stack alignment.
230 unsigned StackAlignOverride;
232 /// In64BitMode - True if compiling for 64-bit, false for 16-bit or 32-bit.
235 /// In32BitMode - True if compiling for 32-bit, false for 16-bit or 64-bit.
238 /// In16BitMode - True if compiling for 16-bit, false for 32-bit or 64-bit.
241 X86SelectionDAGInfo TSInfo;
242 // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
243 // X86TargetLowering needs.
244 X86InstrInfo InstrInfo;
245 X86TargetLowering TLInfo;
246 X86FrameLowering FrameLowering;
250 /// This constructor initializes the data members to match that
251 /// of the specified triple.
253 X86Subtarget(const std::string &TT, const std::string &CPU,
254 const std::string &FS, X86TargetMachine &TM,
255 unsigned StackAlignOverride);
257 const X86TargetLowering *getTargetLowering() const override {
260 const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
261 const DataLayout *getDataLayout() const override { return &DL; }
262 const X86FrameLowering *getFrameLowering() const override {
263 return &FrameLowering;
265 const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
268 const X86RegisterInfo *getRegisterInfo() const override {
269 return &getInstrInfo()->getRegisterInfo();
271 X86JITInfo *getJITInfo() override { return &JITInfo; }
273 /// getStackAlignment - Returns the minimum alignment known to hold of the
274 /// stack frame on entry to the function and which must be maintained by every
275 /// function for this subtarget.
276 unsigned getStackAlignment() const { return stackAlignment; }
278 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
279 /// that still makes it profitable to inline the call.
280 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
282 /// ParseSubtargetFeatures - Parses features string setting specified
283 /// subtarget options. Definition of function is auto generated by tblgen.
284 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
286 /// \brief Reset the features for the X86 target.
287 void resetSubtargetFeatures(const MachineFunction *MF) override;
289 /// \brief Initialize the full set of dependencies so we can use an initializer
290 /// list for X86Subtarget.
291 X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
292 void initializeEnvironment();
293 void resetSubtargetFeatures(StringRef CPU, StringRef FS);
295 /// Is this x86_64? (disregarding specific ABI / programming model)
296 bool is64Bit() const {
300 bool is32Bit() const {
304 bool is16Bit() const {
308 /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
309 bool isTarget64BitILP32() const {
310 return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
311 TargetTriple.getOS() == Triple::NaCl);
314 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
315 bool isTarget64BitLP64() const {
316 return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
317 TargetTriple.getOS() != Triple::NaCl);
320 PICStyles::Style getPICStyle() const { return PICStyle; }
321 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
323 bool hasCMov() const { return HasCMov; }
324 bool hasMMX() const { return X86SSELevel >= MMX; }
325 bool hasSSE1() const { return X86SSELevel >= SSE1; }
326 bool hasSSE2() const { return X86SSELevel >= SSE2; }
327 bool hasSSE3() const { return X86SSELevel >= SSE3; }
328 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
329 bool hasSSE41() const { return X86SSELevel >= SSE41; }
330 bool hasSSE42() const { return X86SSELevel >= SSE42; }
331 bool hasAVX() const { return X86SSELevel >= AVX; }
332 bool hasAVX2() const { return X86SSELevel >= AVX2; }
333 bool hasAVX512() const { return X86SSELevel >= AVX512F; }
334 bool hasFp256() const { return hasAVX(); }
335 bool hasInt256() const { return hasAVX2(); }
336 bool hasSSE4A() const { return HasSSE4A; }
337 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
338 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
339 bool hasPOPCNT() const { return HasPOPCNT; }
340 bool hasAES() const { return HasAES; }
341 bool hasPCLMUL() const { return HasPCLMUL; }
342 bool hasFMA() const { return HasFMA; }
343 // FIXME: Favor FMA when both are enabled. Is this the right thing to do?
344 bool hasFMA4() const { return HasFMA4 && !HasFMA; }
345 bool hasXOP() const { return HasXOP; }
346 bool hasTBM() const { return HasTBM; }
347 bool hasMOVBE() const { return HasMOVBE; }
348 bool hasRDRAND() const { return HasRDRAND; }
349 bool hasF16C() const { return HasF16C; }
350 bool hasFSGSBase() const { return HasFSGSBase; }
351 bool hasLZCNT() const { return HasLZCNT; }
352 bool hasBMI() const { return HasBMI; }
353 bool hasBMI2() const { return HasBMI2; }
354 bool hasRTM() const { return HasRTM; }
355 bool hasHLE() const { return HasHLE; }
356 bool hasADX() const { return HasADX; }
357 bool hasSHA() const { return HasSHA; }
358 bool hasSGX() const { return HasSGX; }
359 bool hasPRFCHW() const { return HasPRFCHW; }
360 bool hasRDSEED() const { return HasRDSEED; }
361 bool isBTMemSlow() const { return IsBTMemSlow; }
362 bool isSHLDSlow() const { return IsSHLDSlow; }
363 bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
364 bool hasVectorUAMem() const { return HasVectorUAMem; }
365 bool hasCmpxchg16b() const { return HasCmpxchg16b; }
366 bool useLeaForSP() const { return UseLeaForSP; }
367 bool hasSlowDivide() const { return HasSlowDivide; }
368 bool padShortFunctions() const { return PadShortFunctions; }
369 bool callRegIndirect() const { return CallRegIndirect; }
370 bool LEAusesAG() const { return LEAUsesAG; }
371 bool slowLEA() const { return SlowLEA; }
372 bool slowIncDec() const { return SlowIncDec; }
373 bool hasCDI() const { return HasCDI; }
374 bool hasPFI() const { return HasPFI; }
375 bool hasERI() const { return HasERI; }
376 bool hasDQI() const { return HasDQI; }
377 bool hasBWI() const { return HasBWI; }
378 bool hasVLX() const { return HasVLX; }
380 bool isAtom() const { return X86ProcFamily == IntelAtom; }
381 bool isSLM() const { return X86ProcFamily == IntelSLM; }
383 const Triple &getTargetTriple() const { return TargetTriple; }
385 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
386 bool isTargetFreeBSD() const {
387 return TargetTriple.getOS() == Triple::FreeBSD;
389 bool isTargetSolaris() const {
390 return TargetTriple.getOS() == Triple::Solaris;
393 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
394 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
395 bool isTargetMacho() const { return TargetTriple.isOSBinFormatMachO(); }
397 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
398 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
399 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
400 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
402 bool isTargetWindowsMSVC() const {
403 return TargetTriple.isWindowsMSVCEnvironment();
406 bool isTargetKnownWindowsMSVC() const {
407 return TargetTriple.isKnownWindowsMSVCEnvironment();
410 bool isTargetWindowsCygwin() const {
411 return TargetTriple.isWindowsCygwinEnvironment();
414 bool isTargetWindowsGNU() const {
415 return TargetTriple.isWindowsGNUEnvironment();
418 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
420 bool isOSWindows() const { return TargetTriple.isOSWindows(); }
422 bool isTargetWin64() const {
423 return In64BitMode && TargetTriple.isOSWindows();
426 bool isTargetWin32() const {
427 return !In64BitMode && (isTargetCygMing() || isTargetKnownWindowsMSVC());
430 bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
431 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
432 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
434 bool isPICStyleStubPIC() const {
435 return PICStyle == PICStyles::StubPIC;
438 bool isPICStyleStubNoDynamic() const {
439 return PICStyle == PICStyles::StubDynamicNoPIC;
441 bool isPICStyleStubAny() const {
442 return PICStyle == PICStyles::StubDynamicNoPIC ||
443 PICStyle == PICStyles::StubPIC;
446 bool isCallingConvWin64(CallingConv::ID CC) const {
447 return (isTargetWin64() && CC != CallingConv::X86_64_SysV) ||
448 CC == CallingConv::X86_64_Win64;
451 /// ClassifyGlobalReference - Classify a global variable reference for the
452 /// current subtarget according to how we should reference it in a non-pcrel
454 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
455 const TargetMachine &TM)const;
457 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
458 /// current subtarget according to how we should reference it in a non-pcrel
460 unsigned char ClassifyBlockAddressReference() const;
462 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
463 /// to immediate address.
464 bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
466 /// This function returns the name of a function which has an interface
467 /// like the non-standard bzero function, if such a function exists on
468 /// the current subtarget and it is considered prefereable over
469 /// memset with zero passed as the second argument. Otherwise it
471 const char *getBZeroEntry() const;
473 /// This function returns true if the target has sincos() routine in its
474 /// compiler runtime or math libraries.
475 bool hasSinCos() const;
477 /// Enable the MachineScheduler pass for all X86 subtargets.
478 bool enableMachineScheduler() const override { return true; }
480 bool enableEarlyIfConversion() const override;
482 /// getInstrItins = Return the instruction itineraries based on the
483 /// subtarget selection.
484 const InstrItineraryData *getInstrItineraryData() const override {
488 AntiDepBreakMode getAntiDepBreakMode() const override {
489 return TargetSubtargetInfo::ANTIDEP_CRITICAL;
493 } // End llvm namespace