1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
15 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
17 #include "X86FrameLowering.h"
18 #include "X86ISelLowering.h"
19 #include "X86InstrInfo.h"
20 #include "X86SelectionDAGInfo.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/Target/TargetSubtargetInfo.h"
26 #define GET_SUBTARGETINFO_HEADER
27 #include "X86GenSubtargetInfo.inc"
34 /// The X86 backend supports a number of different styles of PIC.
38 StubPIC, // Used on i386-darwin in -fPIC mode.
39 StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
40 GOT, // Used on many 32-bit unices in -fPIC mode.
41 RIPRel, // Used on X86-64 when not in -static mode.
42 None // Set when in -static mode (not PIC or DynamicNoPIC mode).
46 class X86Subtarget final : public X86GenSubtargetInfo {
50 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
54 NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
57 enum X86ProcFamilyEnum {
58 Others, IntelAtom, IntelSLM
61 /// X86 processor family: Intel Atom, and others
62 X86ProcFamilyEnum X86ProcFamily;
64 /// Which PIC style to use
65 PICStyles::Style PICStyle;
67 /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
68 X86SSEEnum X86SSELevel;
70 /// MMX, 3DNow, 3DNow Athlon, or none supported.
71 X863DNowEnum X863DNowLevel;
73 /// True if this processor has conditional move instructions
74 /// (generally pentium pro+).
77 /// True if the processor supports X86-64 instructions.
80 /// True if the processor supports POPCNT.
83 /// True if the processor supports SSE4A instructions.
86 /// Target has AES instructions
89 /// Target has FXSAVE/FXRESTOR instructions
92 /// Target has XSAVE instructions
94 /// Target has XSAVEOPT instructions
96 /// Target has XSAVEC instructions
98 /// Target has XSAVES instructions
101 /// Target has carry-less multiplication
104 /// Target has 3-operand fused multiply-add
107 /// Target has 4-operand fused multiply-add
110 /// Target has XOP instructions
113 /// Target has TBM instructions.
116 /// True if the processor has the MOVBE instruction.
119 /// True if the processor has the RDRAND instruction.
122 /// Processor has 16-bit floating point conversion instructions.
125 /// Processor has FS/GS base insturctions.
128 /// Processor has LZCNT instruction.
131 /// Processor has BMI1 instructions.
134 /// Processor has BMI2 instructions.
137 /// Processor has RTM instructions.
140 /// Processor has HLE.
143 /// Processor has ADX instructions.
146 /// Processor has SHA instructions.
149 /// Processor has PRFCHW instructions.
152 /// Processor has RDSEED instructions.
155 /// True if BT (bit test) of memory instructions are slow.
158 /// True if SHLD instructions are slow.
161 /// True if unaligned memory accesses of 16-bytes are slow.
164 /// True if unaligned memory accesses of 32-bytes are slow.
167 /// True if SSE operations can have unaligned memory operands.
168 /// This may require setting a configuration bit in the processor.
169 bool HasSSEUnalignedMem;
171 /// True if this processor has the CMPXCHG16B instruction;
172 /// this is true for most x86-64 chips, but not the first AMD chips.
175 /// True if the LEA instruction should be used for adjusting
176 /// the stack pointer. This is an optimization for Intel Atom processors.
179 /// True if 8-bit divisions are significantly faster than
180 /// 32-bit divisions and should be used when possible.
181 bool HasSlowDivide32;
183 /// True if 16-bit divides are significantly faster than
184 /// 64-bit divisions and should be used when possible.
185 bool HasSlowDivide64;
187 /// True if the short functions should be padded to prevent
188 /// a stall when returning too early.
189 bool PadShortFunctions;
191 /// True if the Calls with memory reference should be converted
192 /// to a register-based indirect call.
193 bool CallRegIndirect;
195 /// True if the LEA instruction inputs have to be ready at address generation
199 /// True if the LEA instruction with certain arguments is slow
202 /// True if INC and DEC instructions are slow when writing to flags
205 /// Processor has AVX-512 PreFetch Instructions
208 /// Processor has AVX-512 Exponential and Reciprocal Instructions
211 /// Processor has AVX-512 Conflict Detection Instructions
214 /// Processor has AVX-512 Doubleword and Quadword instructions
217 /// Processor has AVX-512 Byte and Word instructions
220 /// Processor has AVX-512 Vector Length eXtenstions
223 /// Processot supports MPX - Memory Protection Extensions
226 /// Use software floating point for code generation.
229 /// The minimum alignment known to hold of the stack frame on
230 /// entry to the function and which must be maintained by every function.
231 unsigned stackAlignment;
233 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
235 unsigned MaxInlineSizeThreshold;
237 /// What processor and OS we're targeting.
240 /// Instruction itineraries for scheduling
241 InstrItineraryData InstrItins;
245 /// Override the stack alignment.
246 unsigned StackAlignOverride;
248 /// True if compiling for 64-bit, false for 16-bit or 32-bit.
251 /// True if compiling for 32-bit, false for 16-bit or 64-bit.
254 /// True if compiling for 16-bit, false for 32-bit or 64-bit.
257 X86SelectionDAGInfo TSInfo;
258 // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
259 // X86TargetLowering needs.
260 X86InstrInfo InstrInfo;
261 X86TargetLowering TLInfo;
262 X86FrameLowering FrameLowering;
265 /// This constructor initializes the data members to match that
266 /// of the specified triple.
268 X86Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
269 const X86TargetMachine &TM, unsigned StackAlignOverride);
271 const X86TargetLowering *getTargetLowering() const override {
274 const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
275 const X86FrameLowering *getFrameLowering() const override {
276 return &FrameLowering;
278 const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
281 const X86RegisterInfo *getRegisterInfo() const override {
282 return &getInstrInfo()->getRegisterInfo();
285 /// Returns the minimum alignment known to hold of the
286 /// stack frame on entry to the function and which must be maintained by every
287 /// function for this subtarget.
288 unsigned getStackAlignment() const { return stackAlignment; }
290 /// Returns the maximum memset / memcpy size
291 /// that still makes it profitable to inline the call.
292 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
294 /// ParseSubtargetFeatures - Parses features string setting specified
295 /// subtarget options. Definition of function is auto generated by tblgen.
296 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
299 /// Initialize the full set of dependencies so we can use an initializer
300 /// list for X86Subtarget.
301 X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
302 void initializeEnvironment();
303 void initSubtargetFeatures(StringRef CPU, StringRef FS);
305 /// Is this x86_64? (disregarding specific ABI / programming model)
306 bool is64Bit() const {
310 bool is32Bit() const {
314 bool is16Bit() const {
318 /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
319 bool isTarget64BitILP32() const {
320 return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
321 TargetTriple.isOSNaCl());
324 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
325 bool isTarget64BitLP64() const {
326 return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
327 !TargetTriple.isOSNaCl());
330 PICStyles::Style getPICStyle() const { return PICStyle; }
331 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
333 bool hasCMov() const { return HasCMov; }
334 bool hasSSE1() const { return X86SSELevel >= SSE1; }
335 bool hasSSE2() const { return X86SSELevel >= SSE2; }
336 bool hasSSE3() const { return X86SSELevel >= SSE3; }
337 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
338 bool hasSSE41() const { return X86SSELevel >= SSE41; }
339 bool hasSSE42() const { return X86SSELevel >= SSE42; }
340 bool hasAVX() const { return X86SSELevel >= AVX; }
341 bool hasAVX2() const { return X86SSELevel >= AVX2; }
342 bool hasAVX512() const { return X86SSELevel >= AVX512F; }
343 bool hasFp256() const { return hasAVX(); }
344 bool hasInt256() const { return hasAVX2(); }
345 bool hasSSE4A() const { return HasSSE4A; }
346 bool hasMMX() const { return X863DNowLevel >= MMX; }
347 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
348 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
349 bool hasPOPCNT() const { return HasPOPCNT; }
350 bool hasAES() const { return HasAES; }
351 bool hasFXSR() const { return HasFXSR; }
352 bool hasXSAVE() const { return HasXSAVE; }
353 bool hasXSAVEOPT() const { return HasXSAVEOPT; }
354 bool hasXSAVEC() const { return HasXSAVEC; }
355 bool hasXSAVES() const { return HasXSAVES; }
356 bool hasPCLMUL() const { return HasPCLMUL; }
357 bool hasFMA() const { return HasFMA; }
358 // FIXME: Favor FMA when both are enabled. Is this the right thing to do?
359 bool hasFMA4() const { return HasFMA4 && !HasFMA; }
360 bool hasXOP() const { return HasXOP; }
361 bool hasTBM() const { return HasTBM; }
362 bool hasMOVBE() const { return HasMOVBE; }
363 bool hasRDRAND() const { return HasRDRAND; }
364 bool hasF16C() const { return HasF16C; }
365 bool hasFSGSBase() const { return HasFSGSBase; }
366 bool hasLZCNT() const { return HasLZCNT; }
367 bool hasBMI() const { return HasBMI; }
368 bool hasBMI2() const { return HasBMI2; }
369 bool hasRTM() const { return HasRTM; }
370 bool hasHLE() const { return HasHLE; }
371 bool hasADX() const { return HasADX; }
372 bool hasSHA() const { return HasSHA; }
373 bool hasPRFCHW() const { return HasPRFCHW; }
374 bool hasRDSEED() const { return HasRDSEED; }
375 bool isBTMemSlow() const { return IsBTMemSlow; }
376 bool isSHLDSlow() const { return IsSHLDSlow; }
377 bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
378 bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
379 bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
380 bool hasCmpxchg16b() const { return HasCmpxchg16b; }
381 bool useLeaForSP() const { return UseLeaForSP; }
382 bool hasSlowDivide32() const { return HasSlowDivide32; }
383 bool hasSlowDivide64() const { return HasSlowDivide64; }
384 bool padShortFunctions() const { return PadShortFunctions; }
385 bool callRegIndirect() const { return CallRegIndirect; }
386 bool LEAusesAG() const { return LEAUsesAG; }
387 bool slowLEA() const { return SlowLEA; }
388 bool slowIncDec() const { return SlowIncDec; }
389 bool hasCDI() const { return HasCDI; }
390 bool hasPFI() const { return HasPFI; }
391 bool hasERI() const { return HasERI; }
392 bool hasDQI() const { return HasDQI; }
393 bool hasBWI() const { return HasBWI; }
394 bool hasVLX() const { return HasVLX; }
395 bool hasMPX() const { return HasMPX; }
397 bool isAtom() const { return X86ProcFamily == IntelAtom; }
398 bool isSLM() const { return X86ProcFamily == IntelSLM; }
399 bool useSoftFloat() const { return UseSoftFloat; }
401 const Triple &getTargetTriple() const { return TargetTriple; }
403 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
404 bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
405 bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
406 bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
407 bool isTargetPS4() const { return TargetTriple.isPS4(); }
409 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
410 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
411 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
413 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
414 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
415 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
416 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
417 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
418 bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
420 bool isTargetWindowsMSVC() const {
421 return TargetTriple.isWindowsMSVCEnvironment();
424 bool isTargetKnownWindowsMSVC() const {
425 return TargetTriple.isKnownWindowsMSVCEnvironment();
428 bool isTargetWindowsCoreCLR() const {
429 return TargetTriple.isWindowsCoreCLREnvironment();
432 bool isTargetWindowsCygwin() const {
433 return TargetTriple.isWindowsCygwinEnvironment();
436 bool isTargetWindowsGNU() const {
437 return TargetTriple.isWindowsGNUEnvironment();
440 bool isTargetWindowsItanium() const {
441 return TargetTriple.isWindowsItaniumEnvironment();
444 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
446 bool isOSWindows() const { return TargetTriple.isOSWindows(); }
448 bool isTargetWin64() const {
449 return In64BitMode && TargetTriple.isOSWindows();
452 bool isTargetWin32() const {
453 return !In64BitMode && (isTargetCygMing() || isTargetKnownWindowsMSVC());
456 bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
457 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
458 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
460 bool isPICStyleStubPIC() const {
461 return PICStyle == PICStyles::StubPIC;
464 bool isPICStyleStubNoDynamic() const {
465 return PICStyle == PICStyles::StubDynamicNoPIC;
467 bool isPICStyleStubAny() const {
468 return PICStyle == PICStyles::StubDynamicNoPIC ||
469 PICStyle == PICStyles::StubPIC;
472 bool isCallingConvWin64(CallingConv::ID CC) const {
474 // On Win64, all these conventions just use the default convention.
476 case CallingConv::Fast:
477 case CallingConv::X86_FastCall:
478 case CallingConv::X86_StdCall:
479 case CallingConv::X86_ThisCall:
480 case CallingConv::X86_VectorCall:
481 case CallingConv::Intel_OCL_BI:
482 return isTargetWin64();
483 // This convention allows using the Win64 convention on other targets.
484 case CallingConv::X86_64_Win64:
486 // This convention allows using the SysV convention on Windows targets.
487 case CallingConv::X86_64_SysV:
489 // Otherwise, who knows what this is.
495 /// ClassifyGlobalReference - Classify a global variable reference for the
496 /// current subtarget according to how we should reference it in a non-pcrel
498 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
499 const TargetMachine &TM)const;
501 /// Classify a blockaddress reference for the current subtarget according to
502 /// how we should reference it in a non-pcrel context.
503 unsigned char ClassifyBlockAddressReference() const;
505 /// Return true if the subtarget allows calls to immediate address.
506 bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
508 /// This function returns the name of a function which has an interface
509 /// like the non-standard bzero function, if such a function exists on
510 /// the current subtarget and it is considered prefereable over
511 /// memset with zero passed as the second argument. Otherwise it
513 const char *getBZeroEntry() const;
515 /// This function returns true if the target has sincos() routine in its
516 /// compiler runtime or math libraries.
517 bool hasSinCos() const;
519 /// Enable the MachineScheduler pass for all X86 subtargets.
520 bool enableMachineScheduler() const override { return true; }
522 bool enableEarlyIfConversion() const override;
524 /// Return the instruction itineraries based on the subtarget selection.
525 const InstrItineraryData *getInstrItineraryData() const override {
529 AntiDepBreakMode getAntiDepBreakMode() const override {
530 return TargetSubtargetInfo::ANTIDEP_CRITICAL;
534 } // End llvm namespace