1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86SUBTARGET_H
15 #define X86SUBTARGET_H
17 #include "X86FrameLowering.h"
18 #include "X86ISelLowering.h"
19 #include "X86InstrInfo.h"
20 #include "X86SelectionDAGInfo.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/Target/TargetSubtargetInfo.h"
26 #define GET_SUBTARGETINFO_HEADER
27 #include "X86GenSubtargetInfo.inc"
34 /// PICStyles - The X86 backend supports a number of different styles of PIC.
38 StubPIC, // Used on i386-darwin in -fPIC mode.
39 StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
40 GOT, // Used on many 32-bit unices in -fPIC mode.
41 RIPRel, // Used on X86-64 when not in -static mode.
42 None // Set when in -static mode (not PIC or DynamicNoPIC mode).
46 class X86Subtarget final : public X86GenSubtargetInfo {
50 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
54 NoThreeDNow, ThreeDNow, ThreeDNowA
57 enum X86ProcFamilyEnum {
58 Others, IntelAtom, IntelSLM
61 /// X86ProcFamily - X86 processor family: Intel Atom, and others
62 X86ProcFamilyEnum X86ProcFamily;
64 /// PICStyle - Which PIC style to use
66 PICStyles::Style PICStyle;
68 /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
70 X86SSEEnum X86SSELevel;
72 /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
74 X863DNowEnum X863DNowLevel;
76 /// HasCMov - True if this processor has conditional move instructions
77 /// (generally pentium pro+).
80 /// HasX86_64 - True if the processor supports X86-64 instructions.
84 /// HasPOPCNT - True if the processor supports POPCNT.
87 /// HasSSE4A - True if the processor supports SSE4A instructions.
90 /// HasAES - Target has AES instructions
93 /// HasPCLMUL - Target has carry-less multiplication
96 /// HasFMA - Target has 3-operand fused multiply-add
99 /// HasFMA4 - Target has 4-operand fused multiply-add
102 /// HasXOP - Target has XOP instructions
105 /// HasTBM - Target has TBM instructions.
108 /// HasMOVBE - True if the processor has the MOVBE instruction.
111 /// HasRDRAND - True if the processor has the RDRAND instruction.
114 /// HasF16C - Processor has 16-bit floating point conversion instructions.
117 /// HasFSGSBase - Processor has FS/GS base insturctions.
120 /// HasLZCNT - Processor has LZCNT instruction.
123 /// HasBMI - Processor has BMI1 instructions.
126 /// HasBMI2 - Processor has BMI2 instructions.
129 /// HasRTM - Processor has RTM instructions.
132 /// HasHLE - Processor has HLE.
135 /// HasADX - Processor has ADX instructions.
138 /// HasSHA - Processor has SHA instructions.
141 /// HasSGX - Processor has SGX instructions.
144 /// HasPRFCHW - Processor has PRFCHW instructions.
147 /// HasRDSEED - Processor has RDSEED instructions.
150 /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
153 /// IsSHLDSlow - True if SHLD instructions are slow.
156 /// IsUAMemFast - True if unaligned memory access is fast.
159 /// HasVectorUAMem - True if SIMD operations can have unaligned memory
160 /// operands. This may require setting a feature bit in the processor.
163 /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction;
164 /// this is true for most x86-64 chips, but not the first AMD chips.
167 /// UseLeaForSP - True if the LEA instruction should be used for adjusting
168 /// the stack pointer. This is an optimization for Intel Atom processors.
171 /// HasSlowDivide - True if smaller divides are significantly faster than
172 /// full divides and should be used when possible.
175 /// PadShortFunctions - True if the short functions should be padded to prevent
176 /// a stall when returning too early.
177 bool PadShortFunctions;
179 /// CallRegIndirect - True if the Calls with memory reference should be converted
180 /// to a register-based indirect call.
181 bool CallRegIndirect;
182 /// LEAUsesAG - True if the LEA instruction inputs have to be ready at
183 /// address generation (AG) time.
186 /// SlowLEA - True if the LEA instruction with certain arguments is slow
189 /// SlowIncDec - True if INC and DEC instructions are slow when writing to flags
192 /// Processor has AVX-512 PreFetch Instructions
195 /// Processor has AVX-512 Exponential and Reciprocal Instructions
198 /// Processor has AVX-512 Conflict Detection Instructions
201 /// Processor has AVX-512 Doubleword and Quadword instructions
204 /// Processor has AVX-512 Byte and Word instructions
207 /// Processor has AVX-512 Vector Length eXtenstions
210 /// stackAlignment - The minimum alignment known to hold of the stack frame on
211 /// entry to the function and which must be maintained by every function.
212 unsigned stackAlignment;
214 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
216 unsigned MaxInlineSizeThreshold;
218 /// TargetTriple - What processor and OS we're targeting.
221 /// Instruction itineraries for scheduling
222 InstrItineraryData InstrItins;
225 /// StackAlignOverride - Override the stack alignment.
226 unsigned StackAlignOverride;
228 /// In64BitMode - True if compiling for 64-bit, false for 16-bit or 32-bit.
231 /// In32BitMode - True if compiling for 32-bit, false for 16-bit or 64-bit.
234 /// In16BitMode - True if compiling for 16-bit, false for 32-bit or 64-bit.
237 // Calculates type size & alignment
239 X86SelectionDAGInfo TSInfo;
240 // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
241 // X86TargetLowering needs.
242 X86InstrInfo InstrInfo;
243 X86TargetLowering TLInfo;
244 X86FrameLowering FrameLowering;
247 /// This constructor initializes the data members to match that
248 /// of the specified triple.
250 X86Subtarget(const std::string &TT, const std::string &CPU,
251 const std::string &FS, X86TargetMachine &TM,
252 unsigned StackAlignOverride);
254 const X86TargetLowering *getTargetLowering() const override {
257 const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
258 const DataLayout *getDataLayout() const override { return &DL; }
259 const X86FrameLowering *getFrameLowering() const override {
260 return &FrameLowering;
262 const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
265 const X86RegisterInfo *getRegisterInfo() const override {
266 return &getInstrInfo()->getRegisterInfo();
269 /// getStackAlignment - Returns the minimum alignment known to hold of the
270 /// stack frame on entry to the function and which must be maintained by every
271 /// function for this subtarget.
272 unsigned getStackAlignment() const { return stackAlignment; }
274 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
275 /// that still makes it profitable to inline the call.
276 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
278 /// ParseSubtargetFeatures - Parses features string setting specified
279 /// subtarget options. Definition of function is auto generated by tblgen.
280 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
282 /// \brief Reset the features for the X86 target.
283 void resetSubtargetFeatures(const MachineFunction *MF) override;
285 /// \brief Initialize the full set of dependencies so we can use an initializer
286 /// list for X86Subtarget.
287 X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
288 void initializeEnvironment();
289 void resetSubtargetFeatures(StringRef CPU, StringRef FS);
291 /// Is this x86_64? (disregarding specific ABI / programming model)
292 bool is64Bit() const {
296 bool is32Bit() const {
300 bool is16Bit() const {
304 /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
305 bool isTarget64BitILP32() const {
306 return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
307 TargetTriple.getOS() == Triple::NaCl);
310 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
311 bool isTarget64BitLP64() const {
312 return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
313 TargetTriple.getOS() != Triple::NaCl);
316 PICStyles::Style getPICStyle() const { return PICStyle; }
317 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
319 bool hasCMov() const { return HasCMov; }
320 bool hasMMX() const { return X86SSELevel >= MMX; }
321 bool hasSSE1() const { return X86SSELevel >= SSE1; }
322 bool hasSSE2() const { return X86SSELevel >= SSE2; }
323 bool hasSSE3() const { return X86SSELevel >= SSE3; }
324 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
325 bool hasSSE41() const { return X86SSELevel >= SSE41; }
326 bool hasSSE42() const { return X86SSELevel >= SSE42; }
327 bool hasAVX() const { return X86SSELevel >= AVX; }
328 bool hasAVX2() const { return X86SSELevel >= AVX2; }
329 bool hasAVX512() const { return X86SSELevel >= AVX512F; }
330 bool hasFp256() const { return hasAVX(); }
331 bool hasInt256() const { return hasAVX2(); }
332 bool hasSSE4A() const { return HasSSE4A; }
333 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
334 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
335 bool hasPOPCNT() const { return HasPOPCNT; }
336 bool hasAES() const { return HasAES; }
337 bool hasPCLMUL() const { return HasPCLMUL; }
338 bool hasFMA() const { return HasFMA; }
339 // FIXME: Favor FMA when both are enabled. Is this the right thing to do?
340 bool hasFMA4() const { return HasFMA4 && !HasFMA; }
341 bool hasXOP() const { return HasXOP; }
342 bool hasTBM() const { return HasTBM; }
343 bool hasMOVBE() const { return HasMOVBE; }
344 bool hasRDRAND() const { return HasRDRAND; }
345 bool hasF16C() const { return HasF16C; }
346 bool hasFSGSBase() const { return HasFSGSBase; }
347 bool hasLZCNT() const { return HasLZCNT; }
348 bool hasBMI() const { return HasBMI; }
349 bool hasBMI2() const { return HasBMI2; }
350 bool hasRTM() const { return HasRTM; }
351 bool hasHLE() const { return HasHLE; }
352 bool hasADX() const { return HasADX; }
353 bool hasSHA() const { return HasSHA; }
354 bool hasSGX() const { return HasSGX; }
355 bool hasPRFCHW() const { return HasPRFCHW; }
356 bool hasRDSEED() const { return HasRDSEED; }
357 bool isBTMemSlow() const { return IsBTMemSlow; }
358 bool isSHLDSlow() const { return IsSHLDSlow; }
359 bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
360 bool hasVectorUAMem() const { return HasVectorUAMem; }
361 bool hasCmpxchg16b() const { return HasCmpxchg16b; }
362 bool useLeaForSP() const { return UseLeaForSP; }
363 bool hasSlowDivide() const { return HasSlowDivide; }
364 bool padShortFunctions() const { return PadShortFunctions; }
365 bool callRegIndirect() const { return CallRegIndirect; }
366 bool LEAusesAG() const { return LEAUsesAG; }
367 bool slowLEA() const { return SlowLEA; }
368 bool slowIncDec() const { return SlowIncDec; }
369 bool hasCDI() const { return HasCDI; }
370 bool hasPFI() const { return HasPFI; }
371 bool hasERI() const { return HasERI; }
372 bool hasDQI() const { return HasDQI; }
373 bool hasBWI() const { return HasBWI; }
374 bool hasVLX() const { return HasVLX; }
376 bool isAtom() const { return X86ProcFamily == IntelAtom; }
377 bool isSLM() const { return X86ProcFamily == IntelSLM; }
379 const Triple &getTargetTriple() const { return TargetTriple; }
381 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
382 bool isTargetFreeBSD() const {
383 return TargetTriple.getOS() == Triple::FreeBSD;
385 bool isTargetSolaris() const {
386 return TargetTriple.getOS() == Triple::Solaris;
389 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
390 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
391 bool isTargetMacho() const { return TargetTriple.isOSBinFormatMachO(); }
393 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
394 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
395 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
396 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
398 bool isTargetWindowsMSVC() const {
399 return TargetTriple.isWindowsMSVCEnvironment();
402 bool isTargetKnownWindowsMSVC() const {
403 return TargetTriple.isKnownWindowsMSVCEnvironment();
406 bool isTargetWindowsCygwin() const {
407 return TargetTriple.isWindowsCygwinEnvironment();
410 bool isTargetWindowsGNU() const {
411 return TargetTriple.isWindowsGNUEnvironment();
414 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
416 bool isOSWindows() const { return TargetTriple.isOSWindows(); }
418 bool isTargetWin64() const {
419 return In64BitMode && TargetTriple.isOSWindows();
422 bool isTargetWin32() const {
423 return !In64BitMode && (isTargetCygMing() || isTargetKnownWindowsMSVC());
426 bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
427 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
428 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
430 bool isPICStyleStubPIC() const {
431 return PICStyle == PICStyles::StubPIC;
434 bool isPICStyleStubNoDynamic() const {
435 return PICStyle == PICStyles::StubDynamicNoPIC;
437 bool isPICStyleStubAny() const {
438 return PICStyle == PICStyles::StubDynamicNoPIC ||
439 PICStyle == PICStyles::StubPIC;
442 bool isCallingConvWin64(CallingConv::ID CC) const {
443 return (isTargetWin64() && CC != CallingConv::X86_64_SysV) ||
444 CC == CallingConv::X86_64_Win64;
447 /// ClassifyGlobalReference - Classify a global variable reference for the
448 /// current subtarget according to how we should reference it in a non-pcrel
450 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
451 const TargetMachine &TM)const;
453 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
454 /// current subtarget according to how we should reference it in a non-pcrel
456 unsigned char ClassifyBlockAddressReference() const;
458 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
459 /// to immediate address.
460 bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
462 /// This function returns the name of a function which has an interface
463 /// like the non-standard bzero function, if such a function exists on
464 /// the current subtarget and it is considered prefereable over
465 /// memset with zero passed as the second argument. Otherwise it
467 const char *getBZeroEntry() const;
469 /// This function returns true if the target has sincos() routine in its
470 /// compiler runtime or math libraries.
471 bool hasSinCos() const;
473 /// Enable the MachineScheduler pass for all X86 subtargets.
474 bool enableMachineScheduler() const override { return true; }
476 bool enableEarlyIfConversion() const override;
478 /// getInstrItins = Return the instruction itineraries based on the
479 /// subtarget selection.
480 const InstrItineraryData *getInstrItineraryData() const override {
484 AntiDepBreakMode getAntiDepBreakMode() const override {
485 return TargetSubtargetInfo::ANTIDEP_CRITICAL;
489 } // End llvm namespace