1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86SUBTARGET_H
15 #define X86SUBTARGET_H
17 #include "llvm/ADT/Triple.h"
18 #include "llvm/IR/CallingConv.h"
19 #include "llvm/Target/TargetSubtargetInfo.h"
22 #define GET_SUBTARGETINFO_HEADER
23 #include "X86GenSubtargetInfo.inc"
30 /// PICStyles - The X86 backend supports a number of different styles of PIC.
34 StubPIC, // Used on i386-darwin in -fPIC mode.
35 StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
36 GOT, // Used on many 32-bit unices in -fPIC mode.
37 RIPRel, // Used on X86-64 when not in -static mode.
38 None // Set when in -static mode (not PIC or DynamicNoPIC mode).
42 class X86Subtarget : public X86GenSubtargetInfo {
45 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
49 NoThreeDNow, ThreeDNow, ThreeDNowA
52 enum X86ProcFamilyEnum {
56 /// X86ProcFamily - X86 processor family: Intel Atom, and others
57 X86ProcFamilyEnum X86ProcFamily;
59 /// PICStyle - Which PIC style to use
61 PICStyles::Style PICStyle;
63 /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
65 X86SSEEnum X86SSELevel;
67 /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
69 X863DNowEnum X863DNowLevel;
71 /// HasCMov - True if this processor has conditional move instructions
72 /// (generally pentium pro+).
75 /// HasX86_64 - True if the processor supports X86-64 instructions.
79 /// HasPOPCNT - True if the processor supports POPCNT.
82 /// HasSSE4A - True if the processor supports SSE4A instructions.
85 /// HasAES - Target has AES instructions
88 /// HasPCLMUL - Target has carry-less multiplication
91 /// HasFMA - Target has 3-operand fused multiply-add
94 /// HasFMA4 - Target has 4-operand fused multiply-add
97 /// HasXOP - Target has XOP instructions
100 /// HasMOVBE - True if the processor has the MOVBE instruction.
103 /// HasRDRAND - True if the processor has the RDRAND instruction.
106 /// HasF16C - Processor has 16-bit floating point conversion instructions.
109 /// HasFSGSBase - Processor has FS/GS base insturctions.
112 /// HasLZCNT - Processor has LZCNT instruction.
115 /// HasBMI - Processor has BMI1 instructions.
118 /// HasBMI2 - Processor has BMI2 instructions.
121 /// HasRTM - Processor has RTM instructions.
124 /// HasHLE - Processor has HLE.
127 /// HasADX - Processor has ADX instructions.
130 /// HasPRFCHW - Processor has PRFCHW instructions.
133 /// HasRDSEED - Processor has RDSEED instructions.
136 /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
139 /// IsUAMemFast - True if unaligned memory access is fast.
142 /// HasVectorUAMem - True if SIMD operations can have unaligned memory
143 /// operands. This may require setting a feature bit in the processor.
146 /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction;
147 /// this is true for most x86-64 chips, but not the first AMD chips.
150 /// UseLeaForSP - True if the LEA instruction should be used for adjusting
151 /// the stack pointer. This is an optimization for Intel Atom processors.
154 /// HasSlowDivide - True if smaller divides are significantly faster than
155 /// full divides and should be used when possible.
158 /// PostRAScheduler - True if using post-register-allocation scheduler.
159 bool PostRAScheduler;
161 /// PadShortFunctions - True if the short functions should be padded to prevent
162 /// a stall when returning too early.
163 bool PadShortFunctions;
165 /// CallRegIndirect - True if the Calls with memory reference should be converted
166 /// to a register-based indirect call.
167 bool CallRegIndirect;
169 /// stackAlignment - The minimum alignment known to hold of the stack frame on
170 /// entry to the function and which must be maintained by every function.
171 unsigned stackAlignment;
173 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
175 unsigned MaxInlineSizeThreshold;
177 /// TargetTriple - What processor and OS we're targeting.
180 /// Instruction itineraries for scheduling
181 InstrItineraryData InstrItins;
184 /// StackAlignOverride - Override the stack alignment.
185 unsigned StackAlignOverride;
187 /// In64BitMode - True if compiling for 64-bit, false for 32-bit.
191 /// This constructor initializes the data members to match that
192 /// of the specified triple.
194 X86Subtarget(const std::string &TT, const std::string &CPU,
195 const std::string &FS,
196 unsigned StackAlignOverride, bool is64Bit);
198 /// getStackAlignment - Returns the minimum alignment known to hold of the
199 /// stack frame on entry to the function and which must be maintained by every
200 /// function for this subtarget.
201 unsigned getStackAlignment() const { return stackAlignment; }
203 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
204 /// that still makes it profitable to inline the call.
205 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
207 /// ParseSubtargetFeatures - Parses features string setting specified
208 /// subtarget options. Definition of function is auto generated by tblgen.
209 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
211 /// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID
213 void AutoDetectSubtargetFeatures();
215 /// \brief Reset the features for the X86 target.
216 virtual void resetSubtargetFeatures(const MachineFunction *MF);
218 void initializeEnvironment();
219 void resetSubtargetFeatures(StringRef CPU, StringRef FS);
221 /// Is this x86_64? (disregarding specific ABI / programming model)
222 bool is64Bit() const {
226 /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
227 bool isTarget64BitILP32() const {
228 return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32);
231 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
232 bool isTarget64BitLP64() const {
233 return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32);
236 PICStyles::Style getPICStyle() const { return PICStyle; }
237 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
239 bool hasCMov() const { return HasCMov; }
240 bool hasMMX() const { return X86SSELevel >= MMX; }
241 bool hasSSE1() const { return X86SSELevel >= SSE1; }
242 bool hasSSE2() const { return X86SSELevel >= SSE2; }
243 bool hasSSE3() const { return X86SSELevel >= SSE3; }
244 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
245 bool hasSSE41() const { return X86SSELevel >= SSE41; }
246 bool hasSSE42() const { return X86SSELevel >= SSE42; }
247 bool hasAVX() const { return X86SSELevel >= AVX; }
248 bool hasAVX2() const { return X86SSELevel >= AVX2; }
249 bool hasFp256() const { return hasAVX(); }
250 bool hasInt256() const { return hasAVX2(); }
251 bool hasSSE4A() const { return HasSSE4A; }
252 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
253 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
254 bool hasPOPCNT() const { return HasPOPCNT; }
255 bool hasAES() const { return HasAES; }
256 bool hasPCLMUL() const { return HasPCLMUL; }
257 bool hasFMA() const { return HasFMA; }
258 // FIXME: Favor FMA when both are enabled. Is this the right thing to do?
259 bool hasFMA4() const { return HasFMA4 && !HasFMA; }
260 bool hasXOP() const { return HasXOP; }
261 bool hasMOVBE() const { return HasMOVBE; }
262 bool hasRDRAND() const { return HasRDRAND; }
263 bool hasF16C() const { return HasF16C; }
264 bool hasFSGSBase() const { return HasFSGSBase; }
265 bool hasLZCNT() const { return HasLZCNT; }
266 bool hasBMI() const { return HasBMI; }
267 bool hasBMI2() const { return HasBMI2; }
268 bool hasRTM() const { return HasRTM; }
269 bool hasHLE() const { return HasHLE; }
270 bool hasADX() const { return HasADX; }
271 bool hasPRFCHW() const { return HasPRFCHW; }
272 bool hasRDSEED() const { return HasRDSEED; }
273 bool isBTMemSlow() const { return IsBTMemSlow; }
274 bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
275 bool hasVectorUAMem() const { return HasVectorUAMem; }
276 bool hasCmpxchg16b() const { return HasCmpxchg16b; }
277 bool useLeaForSP() const { return UseLeaForSP; }
278 bool hasSlowDivide() const { return HasSlowDivide; }
279 bool padShortFunctions() const { return PadShortFunctions; }
280 bool callRegIndirect() const { return CallRegIndirect; }
282 bool isAtom() const { return X86ProcFamily == IntelAtom; }
284 const Triple &getTargetTriple() const { return TargetTriple; }
286 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
287 bool isTargetFreeBSD() const {
288 return TargetTriple.getOS() == Triple::FreeBSD;
290 bool isTargetSolaris() const {
291 return TargetTriple.getOS() == Triple::Solaris;
293 bool isTargetELF() const {
294 return (TargetTriple.getEnvironment() == Triple::ELF ||
295 TargetTriple.isOSBinFormatELF());
297 bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; }
298 bool isTargetNaCl() const {
299 return TargetTriple.getOS() == Triple::NaCl;
301 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
302 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
303 bool isTargetWindows() const { return TargetTriple.getOS() == Triple::Win32; }
304 bool isTargetMingw() const { return TargetTriple.getOS() == Triple::MinGW32; }
305 bool isTargetCygwin() const { return TargetTriple.getOS() == Triple::Cygwin; }
306 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
307 bool isTargetCOFF() const {
308 return (TargetTriple.getEnvironment() != Triple::ELF &&
309 TargetTriple.isOSBinFormatCOFF());
311 bool isTargetEnvMacho() const { return TargetTriple.isEnvironmentMachO(); }
313 bool isTargetWin64() const {
314 // FIXME: x86_64-cygwin has not been released yet.
315 return In64BitMode && TargetTriple.isOSWindows();
318 bool isTargetWin32() const {
319 // FIXME: Cygwin is included for isTargetWin64 -- should it be included
321 return !In64BitMode && (isTargetMingw() || isTargetWindows());
324 bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
325 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
326 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
328 bool isPICStyleStubPIC() const {
329 return PICStyle == PICStyles::StubPIC;
332 bool isPICStyleStubNoDynamic() const {
333 return PICStyle == PICStyles::StubDynamicNoPIC;
335 bool isPICStyleStubAny() const {
336 return PICStyle == PICStyles::StubDynamicNoPIC ||
337 PICStyle == PICStyles::StubPIC; }
339 /// ClassifyGlobalReference - Classify a global variable reference for the
340 /// current subtarget according to how we should reference it in a non-pcrel
342 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
343 const TargetMachine &TM)const;
345 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
346 /// current subtarget according to how we should reference it in a non-pcrel
348 unsigned char ClassifyBlockAddressReference() const;
350 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
351 /// to immediate address.
352 bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
354 /// This function returns the name of a function which has an interface
355 /// like the non-standard bzero function, if such a function exists on
356 /// the current subtarget and it is considered prefereable over
357 /// memset with zero passed as the second argument. Otherwise it
359 const char *getBZeroEntry() const;
361 /// This function returns true if the target has sincos() routine in its
362 /// compiler runtime or math libraries.
363 bool hasSinCos() const;
365 /// enablePostRAScheduler - run for Atom optimization.
366 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
367 TargetSubtargetInfo::AntiDepBreakMode& Mode,
368 RegClassVector& CriticalPathRCs) const;
370 bool postRAScheduler() const { return PostRAScheduler; }
372 /// getInstrItins = Return the instruction itineraries based on the
373 /// subtarget selection.
374 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
377 } // End llvm namespace