1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
15 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
17 #include "X86FrameLowering.h"
18 #include "X86ISelLowering.h"
19 #include "X86InstrInfo.h"
20 #include "X86SelectionDAGInfo.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/Target/TargetSubtargetInfo.h"
26 #define GET_SUBTARGETINFO_HEADER
27 #include "X86GenSubtargetInfo.inc"
34 /// The X86 backend supports a number of different styles of PIC.
38 StubPIC, // Used on i386-darwin in -fPIC mode.
39 StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
40 GOT, // Used on many 32-bit unices in -fPIC mode.
41 RIPRel, // Used on X86-64 when not in -static mode.
42 None // Set when in -static mode (not PIC or DynamicNoPIC mode).
46 class X86Subtarget final : public X86GenSubtargetInfo {
50 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
54 NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
57 enum X86ProcFamilyEnum {
58 Others, IntelAtom, IntelSLM
61 /// X86 processor family: Intel Atom, and others
62 X86ProcFamilyEnum X86ProcFamily;
64 /// Which PIC style to use
65 PICStyles::Style PICStyle;
67 /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
68 X86SSEEnum X86SSELevel;
70 /// MMX, 3DNow, 3DNow Athlon, or none supported.
71 X863DNowEnum X863DNowLevel;
73 /// True if this processor has conditional move instructions
74 /// (generally pentium pro+).
77 /// True if the processor supports X86-64 instructions.
80 /// True if the processor supports POPCNT.
83 /// True if the processor supports SSE4A instructions.
86 /// Target has AES instructions
89 /// Target has FXSAVE/FXRESTOR instructions
92 /// Target has XSAVE instructions
94 /// Target has XSAVEOPT instructions
96 /// Target has XSAVEC instructions
98 /// Target has XSAVES instructions
101 /// Target has carry-less multiplication
104 /// Target has 3-operand fused multiply-add
107 /// Target has 4-operand fused multiply-add
110 /// Target has XOP instructions
113 /// Target has TBM instructions.
116 /// True if the processor has the MOVBE instruction.
119 /// True if the processor has the RDRAND instruction.
122 /// Processor has 16-bit floating point conversion instructions.
125 /// Processor has FS/GS base insturctions.
128 /// Processor has LZCNT instruction.
131 /// Processor has BMI1 instructions.
134 /// Processor has BMI2 instructions.
137 /// Processor has RTM instructions.
140 /// Processor has HLE.
143 /// Processor has ADX instructions.
146 /// Processor has SHA instructions.
149 /// Processor has PRFCHW instructions.
152 /// Processor has RDSEED instructions.
155 /// Processor has LAHF/SAHF instructions.
158 /// True if BT (bit test) of memory instructions are slow.
161 /// True if SHLD instructions are slow.
164 /// True if unaligned memory accesses of 16-bytes are slow.
167 /// True if unaligned memory accesses of 32-bytes are slow.
170 /// True if SSE operations can have unaligned memory operands.
171 /// This may require setting a configuration bit in the processor.
172 bool HasSSEUnalignedMem;
174 /// True if this processor has the CMPXCHG16B instruction;
175 /// this is true for most x86-64 chips, but not the first AMD chips.
178 /// True if the LEA instruction should be used for adjusting
179 /// the stack pointer. This is an optimization for Intel Atom processors.
182 /// True if 8-bit divisions are significantly faster than
183 /// 32-bit divisions and should be used when possible.
184 bool HasSlowDivide32;
186 /// True if 16-bit divides are significantly faster than
187 /// 64-bit divisions and should be used when possible.
188 bool HasSlowDivide64;
190 /// True if the short functions should be padded to prevent
191 /// a stall when returning too early.
192 bool PadShortFunctions;
194 /// True if the Calls with memory reference should be converted
195 /// to a register-based indirect call.
196 bool CallRegIndirect;
198 /// True if the LEA instruction inputs have to be ready at address generation
202 /// True if the LEA instruction with certain arguments is slow
205 /// True if INC and DEC instructions are slow when writing to flags
208 /// Processor has AVX-512 PreFetch Instructions
211 /// Processor has AVX-512 Exponential and Reciprocal Instructions
214 /// Processor has AVX-512 Conflict Detection Instructions
217 /// Processor has AVX-512 Doubleword and Quadword instructions
220 /// Processor has AVX-512 Byte and Word instructions
223 /// Processor has AVX-512 Vector Length eXtenstions
226 /// Processot supports MPX - Memory Protection Extensions
229 /// Use software floating point for code generation.
232 /// The minimum alignment known to hold of the stack frame on
233 /// entry to the function and which must be maintained by every function.
234 unsigned stackAlignment;
236 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
238 unsigned MaxInlineSizeThreshold;
240 /// What processor and OS we're targeting.
243 /// Instruction itineraries for scheduling
244 InstrItineraryData InstrItins;
248 /// Override the stack alignment.
249 unsigned StackAlignOverride;
251 /// True if compiling for 64-bit, false for 16-bit or 32-bit.
254 /// True if compiling for 32-bit, false for 16-bit or 64-bit.
257 /// True if compiling for 16-bit, false for 32-bit or 64-bit.
260 X86SelectionDAGInfo TSInfo;
261 // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
262 // X86TargetLowering needs.
263 X86InstrInfo InstrInfo;
264 X86TargetLowering TLInfo;
265 X86FrameLowering FrameLowering;
268 /// This constructor initializes the data members to match that
269 /// of the specified triple.
271 X86Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
272 const X86TargetMachine &TM, unsigned StackAlignOverride);
274 const X86TargetLowering *getTargetLowering() const override {
277 const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
278 const X86FrameLowering *getFrameLowering() const override {
279 return &FrameLowering;
281 const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
284 const X86RegisterInfo *getRegisterInfo() const override {
285 return &getInstrInfo()->getRegisterInfo();
288 /// Returns the minimum alignment known to hold of the
289 /// stack frame on entry to the function and which must be maintained by every
290 /// function for this subtarget.
291 unsigned getStackAlignment() const { return stackAlignment; }
293 /// Returns the maximum memset / memcpy size
294 /// that still makes it profitable to inline the call.
295 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
297 /// ParseSubtargetFeatures - Parses features string setting specified
298 /// subtarget options. Definition of function is auto generated by tblgen.
299 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
302 /// Initialize the full set of dependencies so we can use an initializer
303 /// list for X86Subtarget.
304 X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
305 void initializeEnvironment();
306 void initSubtargetFeatures(StringRef CPU, StringRef FS);
308 /// Is this x86_64? (disregarding specific ABI / programming model)
309 bool is64Bit() const {
313 bool is32Bit() const {
317 bool is16Bit() const {
321 /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
322 bool isTarget64BitILP32() const {
323 return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
324 TargetTriple.isOSNaCl());
327 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
328 bool isTarget64BitLP64() const {
329 return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
330 !TargetTriple.isOSNaCl());
333 PICStyles::Style getPICStyle() const { return PICStyle; }
334 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
336 bool hasCMov() const { return HasCMov; }
337 bool hasSSE1() const { return X86SSELevel >= SSE1; }
338 bool hasSSE2() const { return X86SSELevel >= SSE2; }
339 bool hasSSE3() const { return X86SSELevel >= SSE3; }
340 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
341 bool hasSSE41() const { return X86SSELevel >= SSE41; }
342 bool hasSSE42() const { return X86SSELevel >= SSE42; }
343 bool hasAVX() const { return X86SSELevel >= AVX; }
344 bool hasAVX2() const { return X86SSELevel >= AVX2; }
345 bool hasAVX512() const { return X86SSELevel >= AVX512F; }
346 bool hasFp256() const { return hasAVX(); }
347 bool hasInt256() const { return hasAVX2(); }
348 bool hasSSE4A() const { return HasSSE4A; }
349 bool hasMMX() const { return X863DNowLevel >= MMX; }
350 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
351 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
352 bool hasPOPCNT() const { return HasPOPCNT; }
353 bool hasAES() const { return HasAES; }
354 bool hasFXSR() const { return HasFXSR; }
355 bool hasXSAVE() const { return HasXSAVE; }
356 bool hasXSAVEOPT() const { return HasXSAVEOPT; }
357 bool hasXSAVEC() const { return HasXSAVEC; }
358 bool hasXSAVES() const { return HasXSAVES; }
359 bool hasPCLMUL() const { return HasPCLMUL; }
360 // Prefer FMA4 to FMA - its better for commutation/memory folding and
361 // has equal or better performance on all supported targets.
362 bool hasFMA() const { return HasFMA && !HasFMA4; }
363 bool hasFMA4() const { return HasFMA4; }
364 bool hasAnyFMA() const { return hasFMA() || hasFMA4() || hasAVX512(); }
365 bool hasXOP() const { return HasXOP; }
366 bool hasTBM() const { return HasTBM; }
367 bool hasMOVBE() const { return HasMOVBE; }
368 bool hasRDRAND() const { return HasRDRAND; }
369 bool hasF16C() const { return HasF16C; }
370 bool hasFSGSBase() const { return HasFSGSBase; }
371 bool hasLZCNT() const { return HasLZCNT; }
372 bool hasBMI() const { return HasBMI; }
373 bool hasBMI2() const { return HasBMI2; }
374 bool hasRTM() const { return HasRTM; }
375 bool hasHLE() const { return HasHLE; }
376 bool hasADX() const { return HasADX; }
377 bool hasSHA() const { return HasSHA; }
378 bool hasPRFCHW() const { return HasPRFCHW; }
379 bool hasRDSEED() const { return HasRDSEED; }
380 bool hasLAHFSAHF() const { return HasLAHFSAHF; }
381 bool isBTMemSlow() const { return IsBTMemSlow; }
382 bool isSHLDSlow() const { return IsSHLDSlow; }
383 bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
384 bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
385 bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
386 bool hasCmpxchg16b() const { return HasCmpxchg16b; }
387 bool useLeaForSP() const { return UseLeaForSP; }
388 bool hasSlowDivide32() const { return HasSlowDivide32; }
389 bool hasSlowDivide64() const { return HasSlowDivide64; }
390 bool padShortFunctions() const { return PadShortFunctions; }
391 bool callRegIndirect() const { return CallRegIndirect; }
392 bool LEAusesAG() const { return LEAUsesAG; }
393 bool slowLEA() const { return SlowLEA; }
394 bool slowIncDec() const { return SlowIncDec; }
395 bool hasCDI() const { return HasCDI; }
396 bool hasPFI() const { return HasPFI; }
397 bool hasERI() const { return HasERI; }
398 bool hasDQI() const { return HasDQI; }
399 bool hasBWI() const { return HasBWI; }
400 bool hasVLX() const { return HasVLX; }
401 bool hasMPX() const { return HasMPX; }
403 bool isAtom() const { return X86ProcFamily == IntelAtom; }
404 bool isSLM() const { return X86ProcFamily == IntelSLM; }
405 bool useSoftFloat() const { return UseSoftFloat; }
407 const Triple &getTargetTriple() const { return TargetTriple; }
409 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
410 bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
411 bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
412 bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
413 bool isTargetPS4() const { return TargetTriple.isPS4(); }
415 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
416 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
417 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
419 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
420 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
421 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
422 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
423 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
424 bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
426 bool isTargetWindowsMSVC() const {
427 return TargetTriple.isWindowsMSVCEnvironment();
430 bool isTargetKnownWindowsMSVC() const {
431 return TargetTriple.isKnownWindowsMSVCEnvironment();
434 bool isTargetWindowsCoreCLR() const {
435 return TargetTriple.isWindowsCoreCLREnvironment();
438 bool isTargetWindowsCygwin() const {
439 return TargetTriple.isWindowsCygwinEnvironment();
442 bool isTargetWindowsGNU() const {
443 return TargetTriple.isWindowsGNUEnvironment();
446 bool isTargetWindowsItanium() const {
447 return TargetTriple.isWindowsItaniumEnvironment();
450 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
452 bool isOSWindows() const { return TargetTriple.isOSWindows(); }
454 bool isTargetWin64() const {
455 return In64BitMode && TargetTriple.isOSWindows();
458 bool isTargetWin32() const {
459 return !In64BitMode && (isTargetCygMing() || isTargetKnownWindowsMSVC());
462 bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
463 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
464 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
466 bool isPICStyleStubPIC() const {
467 return PICStyle == PICStyles::StubPIC;
470 bool isPICStyleStubNoDynamic() const {
471 return PICStyle == PICStyles::StubDynamicNoPIC;
473 bool isPICStyleStubAny() const {
474 return PICStyle == PICStyles::StubDynamicNoPIC ||
475 PICStyle == PICStyles::StubPIC;
478 bool isCallingConvWin64(CallingConv::ID CC) const {
480 // On Win64, all these conventions just use the default convention.
482 case CallingConv::Fast:
483 case CallingConv::X86_FastCall:
484 case CallingConv::X86_StdCall:
485 case CallingConv::X86_ThisCall:
486 case CallingConv::X86_VectorCall:
487 case CallingConv::Intel_OCL_BI:
488 return isTargetWin64();
489 // This convention allows using the Win64 convention on other targets.
490 case CallingConv::X86_64_Win64:
492 // This convention allows using the SysV convention on Windows targets.
493 case CallingConv::X86_64_SysV:
495 // Otherwise, who knows what this is.
501 /// ClassifyGlobalReference - Classify a global variable reference for the
502 /// current subtarget according to how we should reference it in a non-pcrel
504 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
505 const TargetMachine &TM)const;
507 /// Classify a blockaddress reference for the current subtarget according to
508 /// how we should reference it in a non-pcrel context.
509 unsigned char ClassifyBlockAddressReference() const;
511 /// Return true if the subtarget allows calls to immediate address.
512 bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
514 /// This function returns the name of a function which has an interface
515 /// like the non-standard bzero function, if such a function exists on
516 /// the current subtarget and it is considered prefereable over
517 /// memset with zero passed as the second argument. Otherwise it
519 const char *getBZeroEntry() const;
521 /// This function returns true if the target has sincos() routine in its
522 /// compiler runtime or math libraries.
523 bool hasSinCos() const;
525 /// Enable the MachineScheduler pass for all X86 subtargets.
526 bool enableMachineScheduler() const override { return true; }
528 bool enableEarlyIfConversion() const override;
530 /// Return the instruction itineraries based on the subtarget selection.
531 const InstrItineraryData *getInstrItineraryData() const override {
535 AntiDepBreakMode getAntiDepBreakMode() const override {
536 return TargetSubtargetInfo::ANTIDEP_CRITICAL;
540 } // End llvm namespace