1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86SUBTARGET_H
15 #define X86SUBTARGET_H
17 #include "X86FrameLowering.h"
18 #include "X86ISelLowering.h"
19 #include "X86InstrInfo.h"
20 #include "X86JITInfo.h"
21 #include "X86SelectionDAGInfo.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/IR/CallingConv.h"
24 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "X86GenSubtargetInfo.inc"
35 /// PICStyles - The X86 backend supports a number of different styles of PIC.
39 StubPIC, // Used on i386-darwin in -fPIC mode.
40 StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
41 GOT, // Used on many 32-bit unices in -fPIC mode.
42 RIPRel, // Used on X86-64 when not in -static mode.
43 None // Set when in -static mode (not PIC or DynamicNoPIC mode).
47 class X86Subtarget final : public X86GenSubtargetInfo {
51 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
55 NoThreeDNow, ThreeDNow, ThreeDNowA
58 enum X86ProcFamilyEnum {
59 Others, IntelAtom, IntelSLM
62 /// X86ProcFamily - X86 processor family: Intel Atom, and others
63 X86ProcFamilyEnum X86ProcFamily;
65 /// PICStyle - Which PIC style to use
67 PICStyles::Style PICStyle;
69 /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
71 X86SSEEnum X86SSELevel;
73 /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
75 X863DNowEnum X863DNowLevel;
77 /// HasCMov - True if this processor has conditional move instructions
78 /// (generally pentium pro+).
81 /// HasX86_64 - True if the processor supports X86-64 instructions.
85 /// HasPOPCNT - True if the processor supports POPCNT.
88 /// HasSSE4A - True if the processor supports SSE4A instructions.
91 /// HasAES - Target has AES instructions
94 /// HasPCLMUL - Target has carry-less multiplication
97 /// HasFMA - Target has 3-operand fused multiply-add
100 /// HasFMA4 - Target has 4-operand fused multiply-add
103 /// HasXOP - Target has XOP instructions
106 /// HasTBM - Target has TBM instructions.
109 /// HasMOVBE - True if the processor has the MOVBE instruction.
112 /// HasRDRAND - True if the processor has the RDRAND instruction.
115 /// HasF16C - Processor has 16-bit floating point conversion instructions.
118 /// HasFSGSBase - Processor has FS/GS base insturctions.
121 /// HasLZCNT - Processor has LZCNT instruction.
124 /// HasBMI - Processor has BMI1 instructions.
127 /// HasBMI2 - Processor has BMI2 instructions.
130 /// HasRTM - Processor has RTM instructions.
133 /// HasHLE - Processor has HLE.
136 /// HasADX - Processor has ADX instructions.
139 /// HasSHA - Processor has SHA instructions.
142 /// HasPRFCHW - Processor has PRFCHW instructions.
145 /// HasRDSEED - Processor has RDSEED instructions.
148 /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
151 /// IsSHLDSlow - True if SHLD instructions are slow.
154 /// IsUAMemFast - True if unaligned memory access is fast.
157 /// HasVectorUAMem - True if SIMD operations can have unaligned memory
158 /// operands. This may require setting a feature bit in the processor.
161 /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction;
162 /// this is true for most x86-64 chips, but not the first AMD chips.
165 /// UseLeaForSP - True if the LEA instruction should be used for adjusting
166 /// the stack pointer. This is an optimization for Intel Atom processors.
169 /// HasSlowDivide - True if smaller divides are significantly faster than
170 /// full divides and should be used when possible.
173 /// PostRAScheduler - True if using post-register-allocation scheduler.
174 bool PostRAScheduler;
176 /// PadShortFunctions - True if the short functions should be padded to prevent
177 /// a stall when returning too early.
178 bool PadShortFunctions;
180 /// CallRegIndirect - True if the Calls with memory reference should be converted
181 /// to a register-based indirect call.
182 bool CallRegIndirect;
183 /// LEAUsesAG - True if the LEA instruction inputs have to be ready at
184 /// address generation (AG) time.
187 /// SlowLEA - True if the LEA instruction with certain arguments is slow
190 /// SlowIncDec - True if INC and DEC instructions are slow when writing to flags
193 /// Processor has AVX-512 PreFetch Instructions
196 /// Processor has AVX-512 Exponential and Reciprocal Instructions
199 /// Processor has AVX-512 Conflict Detection Instructions
202 /// stackAlignment - The minimum alignment known to hold of the stack frame on
203 /// entry to the function and which must be maintained by every function.
204 unsigned stackAlignment;
206 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
208 unsigned MaxInlineSizeThreshold;
210 /// TargetTriple - What processor and OS we're targeting.
213 /// Instruction itineraries for scheduling
214 InstrItineraryData InstrItins;
217 /// StackAlignOverride - Override the stack alignment.
218 unsigned StackAlignOverride;
220 /// In64BitMode - True if compiling for 64-bit, false for 16-bit or 32-bit.
223 /// In32BitMode - True if compiling for 32-bit, false for 16-bit or 64-bit.
226 /// In16BitMode - True if compiling for 16-bit, false for 32-bit or 64-bit.
229 // Calculates type size & alignment
231 X86SelectionDAGInfo TSInfo;
232 X86TargetLowering *TLInfo;
233 X86InstrInfo *InstrInfo;
234 X86FrameLowering *FrameLowering;
238 /// This constructor initializes the data members to match that
239 /// of the specified triple.
241 X86Subtarget(const std::string &TT, const std::string &CPU,
242 const std::string &FS, X86TargetMachine &TM,
243 unsigned StackAlignOverride);
246 const X86TargetLowering *getTargetLowering() const { return TLInfo; }
247 const X86InstrInfo *getInstrInfo() const { return InstrInfo; }
248 const DataLayout *getDataLayout() const { return &DL; }
249 const X86FrameLowering *getFrameLowering() const { return FrameLowering; }
250 const X86SelectionDAGInfo *getSelectionDAGInfo() const { return &TSInfo; }
251 X86JITInfo *getJITInfo() { return JITInfo; }
253 /// getStackAlignment - Returns the minimum alignment known to hold of the
254 /// stack frame on entry to the function and which must be maintained by every
255 /// function for this subtarget.
256 unsigned getStackAlignment() const { return stackAlignment; }
258 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
259 /// that still makes it profitable to inline the call.
260 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
262 /// ParseSubtargetFeatures - Parses features string setting specified
263 /// subtarget options. Definition of function is auto generated by tblgen.
264 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
266 /// \brief Reset the features for the X86 target.
267 void resetSubtargetFeatures(const MachineFunction *MF) override;
269 void initializeEnvironment();
270 void resetSubtargetFeatures(StringRef CPU, StringRef FS);
272 /// Is this x86_64? (disregarding specific ABI / programming model)
273 bool is64Bit() const {
277 bool is32Bit() const {
281 bool is16Bit() const {
285 /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
286 bool isTarget64BitILP32() const {
287 return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
288 TargetTriple.getOS() == Triple::NaCl);
291 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
292 bool isTarget64BitLP64() const {
293 return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32);
296 PICStyles::Style getPICStyle() const { return PICStyle; }
297 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
299 bool hasCMov() const { return HasCMov; }
300 bool hasMMX() const { return X86SSELevel >= MMX; }
301 bool hasSSE1() const { return X86SSELevel >= SSE1; }
302 bool hasSSE2() const { return X86SSELevel >= SSE2; }
303 bool hasSSE3() const { return X86SSELevel >= SSE3; }
304 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
305 bool hasSSE41() const { return X86SSELevel >= SSE41; }
306 bool hasSSE42() const { return X86SSELevel >= SSE42; }
307 bool hasAVX() const { return X86SSELevel >= AVX; }
308 bool hasAVX2() const { return X86SSELevel >= AVX2; }
309 bool hasAVX512() const { return X86SSELevel >= AVX512F; }
310 bool hasFp256() const { return hasAVX(); }
311 bool hasInt256() const { return hasAVX2(); }
312 bool hasSSE4A() const { return HasSSE4A; }
313 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
314 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
315 bool hasPOPCNT() const { return HasPOPCNT; }
316 bool hasAES() const { return HasAES; }
317 bool hasPCLMUL() const { return HasPCLMUL; }
318 bool hasFMA() const { return HasFMA; }
319 // FIXME: Favor FMA when both are enabled. Is this the right thing to do?
320 bool hasFMA4() const { return HasFMA4 && !HasFMA; }
321 bool hasXOP() const { return HasXOP; }
322 bool hasTBM() const { return HasTBM; }
323 bool hasMOVBE() const { return HasMOVBE; }
324 bool hasRDRAND() const { return HasRDRAND; }
325 bool hasF16C() const { return HasF16C; }
326 bool hasFSGSBase() const { return HasFSGSBase; }
327 bool hasLZCNT() const { return HasLZCNT; }
328 bool hasBMI() const { return HasBMI; }
329 bool hasBMI2() const { return HasBMI2; }
330 bool hasRTM() const { return HasRTM; }
331 bool hasHLE() const { return HasHLE; }
332 bool hasADX() const { return HasADX; }
333 bool hasSHA() const { return HasSHA; }
334 bool hasPRFCHW() const { return HasPRFCHW; }
335 bool hasRDSEED() const { return HasRDSEED; }
336 bool isBTMemSlow() const { return IsBTMemSlow; }
337 bool isSHLDSlow() const { return IsSHLDSlow; }
338 bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
339 bool hasVectorUAMem() const { return HasVectorUAMem; }
340 bool hasCmpxchg16b() const { return HasCmpxchg16b; }
341 bool useLeaForSP() const { return UseLeaForSP; }
342 bool hasSlowDivide() const { return HasSlowDivide; }
343 bool padShortFunctions() const { return PadShortFunctions; }
344 bool callRegIndirect() const { return CallRegIndirect; }
345 bool LEAusesAG() const { return LEAUsesAG; }
346 bool slowLEA() const { return SlowLEA; }
347 bool slowIncDec() const { return SlowIncDec; }
348 bool hasCDI() const { return HasCDI; }
349 bool hasPFI() const { return HasPFI; }
350 bool hasERI() const { return HasERI; }
352 bool isAtom() const { return X86ProcFamily == IntelAtom; }
353 bool isSLM() const { return X86ProcFamily == IntelSLM; }
355 const Triple &getTargetTriple() const { return TargetTriple; }
357 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
358 bool isTargetFreeBSD() const {
359 return TargetTriple.getOS() == Triple::FreeBSD;
361 bool isTargetSolaris() const {
362 return TargetTriple.getOS() == Triple::Solaris;
365 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
366 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
367 bool isTargetMacho() const { return TargetTriple.isOSBinFormatMachO(); }
369 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
370 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
371 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
372 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
374 bool isTargetWindowsMSVC() const {
375 return TargetTriple.isWindowsMSVCEnvironment();
378 bool isTargetKnownWindowsMSVC() const {
379 return TargetTriple.isKnownWindowsMSVCEnvironment();
382 bool isTargetWindowsCygwin() const {
383 return TargetTriple.isWindowsCygwinEnvironment();
386 bool isTargetWindowsGNU() const {
387 return TargetTriple.isWindowsGNUEnvironment();
390 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
392 bool isOSWindows() const { return TargetTriple.isOSWindows(); }
394 bool isTargetWin64() const {
395 return In64BitMode && TargetTriple.isOSWindows();
398 bool isTargetWin32() const {
399 return !In64BitMode && (isTargetCygMing() || isTargetKnownWindowsMSVC());
402 bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
403 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
404 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
406 bool isPICStyleStubPIC() const {
407 return PICStyle == PICStyles::StubPIC;
410 bool isPICStyleStubNoDynamic() const {
411 return PICStyle == PICStyles::StubDynamicNoPIC;
413 bool isPICStyleStubAny() const {
414 return PICStyle == PICStyles::StubDynamicNoPIC ||
415 PICStyle == PICStyles::StubPIC;
418 bool isCallingConvWin64(CallingConv::ID CC) const {
419 return (isTargetWin64() && CC != CallingConv::X86_64_SysV) ||
420 CC == CallingConv::X86_64_Win64;
423 /// ClassifyGlobalReference - Classify a global variable reference for the
424 /// current subtarget according to how we should reference it in a non-pcrel
426 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
427 const TargetMachine &TM)const;
429 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
430 /// current subtarget according to how we should reference it in a non-pcrel
432 unsigned char ClassifyBlockAddressReference() const;
434 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
435 /// to immediate address.
436 bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
438 /// This function returns the name of a function which has an interface
439 /// like the non-standard bzero function, if such a function exists on
440 /// the current subtarget and it is considered prefereable over
441 /// memset with zero passed as the second argument. Otherwise it
443 const char *getBZeroEntry() const;
445 /// This function returns true if the target has sincos() routine in its
446 /// compiler runtime or math libraries.
447 bool hasSinCos() const;
449 /// Enable the MachineScheduler pass for all X86 subtargets.
450 bool enableMachineScheduler() const override { return true; }
452 /// enablePostRAScheduler - run for Atom optimization.
453 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
454 TargetSubtargetInfo::AntiDepBreakMode& Mode,
455 RegClassVector& CriticalPathRCs) const override;
457 bool postRAScheduler() const { return PostRAScheduler; }
459 bool enableEarlyIfConversion() const override;
461 /// getInstrItins = Return the instruction itineraries based on the
462 /// subtarget selection.
463 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
466 } // End llvm namespace