1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
15 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
17 #include "X86FrameLowering.h"
18 #include "X86ISelLowering.h"
19 #include "X86InstrInfo.h"
20 #include "X86SelectionDAGInfo.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/Target/TargetSubtargetInfo.h"
26 #define GET_SUBTARGETINFO_HEADER
27 #include "X86GenSubtargetInfo.inc"
34 /// The X86 backend supports a number of different styles of PIC.
38 StubPIC, // Used on i386-darwin in -fPIC mode.
39 StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
40 GOT, // Used on many 32-bit unices in -fPIC mode.
41 RIPRel, // Used on X86-64 when not in -static mode.
42 None // Set when in -static mode (not PIC or DynamicNoPIC mode).
46 class X86Subtarget final : public X86GenSubtargetInfo {
50 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
54 NoThreeDNow, ThreeDNow, ThreeDNowA
57 enum X86ProcFamilyEnum {
58 Others, IntelAtom, IntelSLM
61 /// X86 processor family: Intel Atom, and others
62 X86ProcFamilyEnum X86ProcFamily;
64 /// Which PIC style to use
65 PICStyles::Style PICStyle;
67 /// MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
68 X86SSEEnum X86SSELevel;
70 /// 3DNow, 3DNow Athlon, or none supported.
71 X863DNowEnum X863DNowLevel;
73 /// True if this processor has conditional move instructions
74 /// (generally pentium pro+).
77 /// True if the processor supports X86-64 instructions.
80 /// True if the processor supports POPCNT.
83 /// True if the processor supports SSE4A instructions.
86 /// Target has AES instructions
89 /// Target has carry-less multiplication
92 /// Target has 3-operand fused multiply-add
95 /// Target has 4-operand fused multiply-add
98 /// Target has XOP instructions
101 /// Target has TBM instructions.
104 /// True if the processor has the MOVBE instruction.
107 /// True if the processor has the RDRAND instruction.
110 /// Processor has 16-bit floating point conversion instructions.
113 /// Processor has FS/GS base insturctions.
116 /// Processor has LZCNT instruction.
119 /// Processor has BMI1 instructions.
122 /// Processor has BMI2 instructions.
125 /// Processor has RTM instructions.
128 /// Processor has HLE.
131 /// Processor has ADX instructions.
134 /// Processor has SHA instructions.
137 /// Processor has PRFCHW instructions.
140 /// Processor has RDSEED instructions.
143 /// True if BT (bit test) of memory instructions are slow.
146 /// True if SHLD instructions are slow.
149 /// True if unaligned memory accesses of 16-bytes or smaller are slow.
150 bool IsUAMemUnder32Slow;
152 /// True if unaligned memory accesses of 32-bytes are slow.
155 /// True if SSE operations can have unaligned memory operands.
156 /// This may require setting a configuration bit in the processor.
157 bool HasSSEUnalignedMem;
159 /// True if this processor has the CMPXCHG16B instruction;
160 /// this is true for most x86-64 chips, but not the first AMD chips.
163 /// True if the LEA instruction should be used for adjusting
164 /// the stack pointer. This is an optimization for Intel Atom processors.
167 /// True if 8-bit divisions are significantly faster than
168 /// 32-bit divisions and should be used when possible.
169 bool HasSlowDivide32;
171 /// True if 16-bit divides are significantly faster than
172 /// 64-bit divisions and should be used when possible.
173 bool HasSlowDivide64;
175 /// True if the short functions should be padded to prevent
176 /// a stall when returning too early.
177 bool PadShortFunctions;
179 /// True if the Calls with memory reference should be converted
180 /// to a register-based indirect call.
181 bool CallRegIndirect;
183 /// True if the LEA instruction inputs have to be ready at address generation
187 /// True if the LEA instruction with certain arguments is slow
190 /// True if INC and DEC instructions are slow when writing to flags
193 /// Processor has AVX-512 PreFetch Instructions
196 /// Processor has AVX-512 Exponential and Reciprocal Instructions
199 /// Processor has AVX-512 Conflict Detection Instructions
202 /// Processor has AVX-512 Doubleword and Quadword instructions
205 /// Processor has AVX-512 Byte and Word instructions
208 /// Processor has AVX-512 Vector Length eXtenstions
211 /// Processot supports MPX - Memory Protection Extensions
214 /// Use software floating point for code generation.
217 /// The minimum alignment known to hold of the stack frame on
218 /// entry to the function and which must be maintained by every function.
219 unsigned stackAlignment;
221 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
223 unsigned MaxInlineSizeThreshold;
225 /// What processor and OS we're targeting.
228 /// Instruction itineraries for scheduling
229 InstrItineraryData InstrItins;
233 /// Override the stack alignment.
234 unsigned StackAlignOverride;
236 /// True if compiling for 64-bit, false for 16-bit or 32-bit.
239 /// True if compiling for 32-bit, false for 16-bit or 64-bit.
242 /// True if compiling for 16-bit, false for 32-bit or 64-bit.
245 X86SelectionDAGInfo TSInfo;
246 // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
247 // X86TargetLowering needs.
248 X86InstrInfo InstrInfo;
249 X86TargetLowering TLInfo;
250 X86FrameLowering FrameLowering;
253 /// This constructor initializes the data members to match that
254 /// of the specified triple.
256 X86Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
257 const X86TargetMachine &TM, unsigned StackAlignOverride);
259 const X86TargetLowering *getTargetLowering() const override {
262 const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
263 const X86FrameLowering *getFrameLowering() const override {
264 return &FrameLowering;
266 const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
269 const X86RegisterInfo *getRegisterInfo() const override {
270 return &getInstrInfo()->getRegisterInfo();
273 /// Returns the minimum alignment known to hold of the
274 /// stack frame on entry to the function and which must be maintained by every
275 /// function for this subtarget.
276 unsigned getStackAlignment() const { return stackAlignment; }
278 /// Returns the maximum memset / memcpy size
279 /// that still makes it profitable to inline the call.
280 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
282 /// ParseSubtargetFeatures - Parses features string setting specified
283 /// subtarget options. Definition of function is auto generated by tblgen.
284 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
287 /// Initialize the full set of dependencies so we can use an initializer
288 /// list for X86Subtarget.
289 X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
290 void initializeEnvironment();
291 void initSubtargetFeatures(StringRef CPU, StringRef FS);
293 /// Is this x86_64? (disregarding specific ABI / programming model)
294 bool is64Bit() const {
298 bool is32Bit() const {
302 bool is16Bit() const {
306 /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
307 bool isTarget64BitILP32() const {
308 return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
309 TargetTriple.isOSNaCl());
312 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
313 bool isTarget64BitLP64() const {
314 return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
315 !TargetTriple.isOSNaCl());
318 PICStyles::Style getPICStyle() const { return PICStyle; }
319 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
321 bool hasCMov() const { return HasCMov; }
322 bool hasMMX() const { return X86SSELevel >= MMX; }
323 bool hasSSE1() const { return X86SSELevel >= SSE1; }
324 bool hasSSE2() const { return X86SSELevel >= SSE2; }
325 bool hasSSE3() const { return X86SSELevel >= SSE3; }
326 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
327 bool hasSSE41() const { return X86SSELevel >= SSE41; }
328 bool hasSSE42() const { return X86SSELevel >= SSE42; }
329 bool hasAVX() const { return X86SSELevel >= AVX; }
330 bool hasAVX2() const { return X86SSELevel >= AVX2; }
331 bool hasAVX512() const { return X86SSELevel >= AVX512F; }
332 bool hasFp256() const { return hasAVX(); }
333 bool hasInt256() const { return hasAVX2(); }
334 bool hasSSE4A() const { return HasSSE4A; }
335 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
336 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
337 bool hasPOPCNT() const { return HasPOPCNT; }
338 bool hasAES() const { return HasAES; }
339 bool hasPCLMUL() const { return HasPCLMUL; }
340 bool hasFMA() const { return HasFMA; }
341 // FIXME: Favor FMA when both are enabled. Is this the right thing to do?
342 bool hasFMA4() const { return HasFMA4 && !HasFMA; }
343 bool hasXOP() const { return HasXOP; }
344 bool hasTBM() const { return HasTBM; }
345 bool hasMOVBE() const { return HasMOVBE; }
346 bool hasRDRAND() const { return HasRDRAND; }
347 bool hasF16C() const { return HasF16C; }
348 bool hasFSGSBase() const { return HasFSGSBase; }
349 bool hasLZCNT() const { return HasLZCNT; }
350 bool hasBMI() const { return HasBMI; }
351 bool hasBMI2() const { return HasBMI2; }
352 bool hasRTM() const { return HasRTM; }
353 bool hasHLE() const { return HasHLE; }
354 bool hasADX() const { return HasADX; }
355 bool hasSHA() const { return HasSHA; }
356 bool hasPRFCHW() const { return HasPRFCHW; }
357 bool hasRDSEED() const { return HasRDSEED; }
358 bool isBTMemSlow() const { return IsBTMemSlow; }
359 bool isSHLDSlow() const { return IsSHLDSlow; }
360 bool isUnalignedMemUnder32Slow() const { return IsUAMemUnder32Slow; }
361 bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
362 bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
363 bool hasCmpxchg16b() const { return HasCmpxchg16b; }
364 bool useLeaForSP() const { return UseLeaForSP; }
365 bool hasSlowDivide32() const { return HasSlowDivide32; }
366 bool hasSlowDivide64() const { return HasSlowDivide64; }
367 bool padShortFunctions() const { return PadShortFunctions; }
368 bool callRegIndirect() const { return CallRegIndirect; }
369 bool LEAusesAG() const { return LEAUsesAG; }
370 bool slowLEA() const { return SlowLEA; }
371 bool slowIncDec() const { return SlowIncDec; }
372 bool hasCDI() const { return HasCDI; }
373 bool hasPFI() const { return HasPFI; }
374 bool hasERI() const { return HasERI; }
375 bool hasDQI() const { return HasDQI; }
376 bool hasBWI() const { return HasBWI; }
377 bool hasVLX() const { return HasVLX; }
378 bool hasMPX() const { return HasMPX; }
380 bool isAtom() const { return X86ProcFamily == IntelAtom; }
381 bool isSLM() const { return X86ProcFamily == IntelSLM; }
382 bool useSoftFloat() const { return UseSoftFloat; }
384 const Triple &getTargetTriple() const { return TargetTriple; }
386 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
387 bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
388 bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
389 bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
390 bool isTargetPS4() const { return TargetTriple.isPS4(); }
392 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
393 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
394 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
396 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
397 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
398 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
399 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
401 bool isTargetWindowsMSVC() const {
402 return TargetTriple.isWindowsMSVCEnvironment();
405 bool isTargetKnownWindowsMSVC() const {
406 return TargetTriple.isKnownWindowsMSVCEnvironment();
409 bool isTargetWindowsCoreCLR() const {
410 return TargetTriple.isWindowsCoreCLREnvironment();
413 bool isTargetWindowsCygwin() const {
414 return TargetTriple.isWindowsCygwinEnvironment();
417 bool isTargetWindowsGNU() const {
418 return TargetTriple.isWindowsGNUEnvironment();
421 bool isTargetWindowsItanium() const {
422 return TargetTriple.isWindowsItaniumEnvironment();
425 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
427 bool isOSWindows() const { return TargetTriple.isOSWindows(); }
429 bool isTargetWin64() const {
430 return In64BitMode && TargetTriple.isOSWindows();
433 bool isTargetWin32() const {
434 return !In64BitMode && (isTargetCygMing() || isTargetKnownWindowsMSVC());
437 bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
438 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
439 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
441 bool isPICStyleStubPIC() const {
442 return PICStyle == PICStyles::StubPIC;
445 bool isPICStyleStubNoDynamic() const {
446 return PICStyle == PICStyles::StubDynamicNoPIC;
448 bool isPICStyleStubAny() const {
449 return PICStyle == PICStyles::StubDynamicNoPIC ||
450 PICStyle == PICStyles::StubPIC;
453 bool isCallingConvWin64(CallingConv::ID CC) const {
455 // On Win64, all these conventions just use the default convention.
457 case CallingConv::Fast:
458 case CallingConv::X86_FastCall:
459 case CallingConv::X86_StdCall:
460 case CallingConv::X86_ThisCall:
461 case CallingConv::X86_VectorCall:
462 case CallingConv::Intel_OCL_BI:
463 return isTargetWin64();
464 // This convention allows using the Win64 convention on other targets.
465 case CallingConv::X86_64_Win64:
467 // This convention allows using the SysV convention on Windows targets.
468 case CallingConv::X86_64_SysV:
470 // Otherwise, who knows what this is.
476 /// ClassifyGlobalReference - Classify a global variable reference for the
477 /// current subtarget according to how we should reference it in a non-pcrel
479 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
480 const TargetMachine &TM)const;
482 /// Classify a blockaddress reference for the current subtarget according to
483 /// how we should reference it in a non-pcrel context.
484 unsigned char ClassifyBlockAddressReference() const;
486 /// Return true if the subtarget allows calls to immediate address.
487 bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
489 /// This function returns the name of a function which has an interface
490 /// like the non-standard bzero function, if such a function exists on
491 /// the current subtarget and it is considered prefereable over
492 /// memset with zero passed as the second argument. Otherwise it
494 const char *getBZeroEntry() const;
496 /// This function returns true if the target has sincos() routine in its
497 /// compiler runtime or math libraries.
498 bool hasSinCos() const;
500 /// Enable the MachineScheduler pass for all X86 subtargets.
501 bool enableMachineScheduler() const override { return true; }
503 bool enableEarlyIfConversion() const override;
505 /// Return the instruction itineraries based on the subtarget selection.
506 const InstrItineraryData *getInstrItineraryData() const override {
510 AntiDepBreakMode getAntiDepBreakMode() const override {
511 return TargetSubtargetInfo::ANTIDEP_CRITICAL;
515 } // End llvm namespace