1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86SUBTARGET_H
15 #define X86SUBTARGET_H
17 #include "llvm/ADT/Triple.h"
18 #include "llvm/IR/CallingConv.h"
19 #include "llvm/Target/TargetSubtargetInfo.h"
22 #define GET_SUBTARGETINFO_HEADER
23 #include "X86GenSubtargetInfo.inc"
30 /// PICStyles - The X86 backend supports a number of different styles of PIC.
34 StubPIC, // Used on i386-darwin in -fPIC mode.
35 StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
36 GOT, // Used on many 32-bit unices in -fPIC mode.
37 RIPRel, // Used on X86-64 when not in -static mode.
38 None // Set when in -static mode (not PIC or DynamicNoPIC mode).
42 class X86Subtarget : public X86GenSubtargetInfo {
45 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
49 NoThreeDNow, ThreeDNow, ThreeDNowA
52 enum X86ProcFamilyEnum {
56 /// X86ProcFamily - X86 processor family: Intel Atom, and others
57 X86ProcFamilyEnum X86ProcFamily;
59 /// PICStyle - Which PIC style to use
61 PICStyles::Style PICStyle;
63 /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
65 X86SSEEnum X86SSELevel;
67 /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
69 X863DNowEnum X863DNowLevel;
71 /// HasCMov - True if this processor has conditional move instructions
72 /// (generally pentium pro+).
75 /// HasX86_64 - True if the processor supports X86-64 instructions.
79 /// HasPOPCNT - True if the processor supports POPCNT.
82 /// HasSSE4A - True if the processor supports SSE4A instructions.
85 /// HasAES - Target has AES instructions
88 /// HasPCLMUL - Target has carry-less multiplication
91 /// HasFMA - Target has 3-operand fused multiply-add
94 /// HasFMA4 - Target has 4-operand fused multiply-add
97 /// HasXOP - Target has XOP instructions
100 /// HasMOVBE - True if the processor has the MOVBE instruction.
103 /// HasRDRAND - True if the processor has the RDRAND instruction.
106 /// HasF16C - Processor has 16-bit floating point conversion instructions.
109 /// HasFSGSBase - Processor has FS/GS base insturctions.
112 /// HasLZCNT - Processor has LZCNT instruction.
115 /// HasBMI - Processor has BMI1 instructions.
118 /// HasBMI2 - Processor has BMI2 instructions.
121 /// HasRTM - Processor has RTM instructions.
124 /// HasADX - Processor has ADX instructions.
127 /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
130 /// IsUAMemFast - True if unaligned memory access is fast.
133 /// HasVectorUAMem - True if SIMD operations can have unaligned memory
134 /// operands. This may require setting a feature bit in the processor.
137 /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction;
138 /// this is true for most x86-64 chips, but not the first AMD chips.
141 /// UseLeaForSP - True if the LEA instruction should be used for adjusting
142 /// the stack pointer. This is an optimization for Intel Atom processors.
145 /// HasSlowDivide - True if smaller divides are significantly faster than
146 /// full divides and should be used when possible.
149 /// PostRAScheduler - True if using post-register-allocation scheduler.
150 bool PostRAScheduler;
152 /// PadShortFunctions - True if the short functions should be padded to prevent
153 /// a stall when returning too early.
154 bool PadShortFunctions;
156 /// stackAlignment - The minimum alignment known to hold of the stack frame on
157 /// entry to the function and which must be maintained by every function.
158 unsigned stackAlignment;
160 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
162 unsigned MaxInlineSizeThreshold;
164 /// TargetTriple - What processor and OS we're targeting.
167 /// Instruction itineraries for scheduling
168 InstrItineraryData InstrItins;
171 /// StackAlignOverride - Override the stack alignment.
172 unsigned StackAlignOverride;
174 /// In64BitMode - True if compiling for 64-bit, false for 32-bit.
178 /// This constructor initializes the data members to match that
179 /// of the specified triple.
181 X86Subtarget(const std::string &TT, const std::string &CPU,
182 const std::string &FS,
183 unsigned StackAlignOverride, bool is64Bit);
185 /// getStackAlignment - Returns the minimum alignment known to hold of the
186 /// stack frame on entry to the function and which must be maintained by every
187 /// function for this subtarget.
188 unsigned getStackAlignment() const { return stackAlignment; }
190 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
191 /// that still makes it profitable to inline the call.
192 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
194 /// ParseSubtargetFeatures - Parses features string setting specified
195 /// subtarget options. Definition of function is auto generated by tblgen.
196 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
198 /// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID
200 void AutoDetectSubtargetFeatures();
202 /// \brief Reset the features for the X86 target.
203 virtual void resetSubtargetFeatures(const MachineFunction *MF);
204 void resetSubtargetFeatures(StringRef CPU, StringRef FS);
206 /// Is this x86_64? (disregarding specific ABI / programming model)
207 bool is64Bit() const {
211 /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
212 bool isTarget64BitILP32() const {
213 return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32);
216 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
217 bool isTarget64BitLP64() const {
218 return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32);
221 PICStyles::Style getPICStyle() const { return PICStyle; }
222 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
224 bool hasCMov() const { return HasCMov; }
225 bool hasMMX() const { return X86SSELevel >= MMX; }
226 bool hasSSE1() const { return X86SSELevel >= SSE1; }
227 bool hasSSE2() const { return X86SSELevel >= SSE2; }
228 bool hasSSE3() const { return X86SSELevel >= SSE3; }
229 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
230 bool hasSSE41() const { return X86SSELevel >= SSE41; }
231 bool hasSSE42() const { return X86SSELevel >= SSE42; }
232 bool hasAVX() const { return X86SSELevel >= AVX; }
233 bool hasAVX2() const { return X86SSELevel >= AVX2; }
234 bool hasFp256() const { return hasAVX(); }
235 bool hasInt256() const { return hasAVX2(); }
236 bool hasSSE4A() const { return HasSSE4A; }
237 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
238 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
239 bool hasPOPCNT() const { return HasPOPCNT; }
240 bool hasAES() const { return HasAES; }
241 bool hasPCLMUL() const { return HasPCLMUL; }
242 bool hasFMA() const { return HasFMA; }
243 // FIXME: Favor FMA when both are enabled. Is this the right thing to do?
244 bool hasFMA4() const { return HasFMA4 && !HasFMA; }
245 bool hasXOP() const { return HasXOP; }
246 bool hasMOVBE() const { return HasMOVBE; }
247 bool hasRDRAND() const { return HasRDRAND; }
248 bool hasF16C() const { return HasF16C; }
249 bool hasFSGSBase() const { return HasFSGSBase; }
250 bool hasLZCNT() const { return HasLZCNT; }
251 bool hasBMI() const { return HasBMI; }
252 bool hasBMI2() const { return HasBMI2; }
253 bool hasRTM() const { return HasRTM; }
254 bool hasADX() const { return HasADX; }
255 bool isBTMemSlow() const { return IsBTMemSlow; }
256 bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
257 bool hasVectorUAMem() const { return HasVectorUAMem; }
258 bool hasCmpxchg16b() const { return HasCmpxchg16b; }
259 bool useLeaForSP() const { return UseLeaForSP; }
260 bool hasSlowDivide() const { return HasSlowDivide; }
261 bool padShortFunctions() const { return PadShortFunctions; }
263 bool isAtom() const { return X86ProcFamily == IntelAtom; }
265 const Triple &getTargetTriple() const { return TargetTriple; }
267 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
268 bool isTargetFreeBSD() const {
269 return TargetTriple.getOS() == Triple::FreeBSD;
271 bool isTargetSolaris() const {
272 return TargetTriple.getOS() == Triple::Solaris;
274 bool isTargetELF() const {
275 return (TargetTriple.getEnvironment() == Triple::ELF ||
276 TargetTriple.isOSBinFormatELF());
278 bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; }
279 bool isTargetNaCl() const {
280 return TargetTriple.getOS() == Triple::NaCl;
282 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
283 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
284 bool isTargetWindows() const { return TargetTriple.getOS() == Triple::Win32; }
285 bool isTargetMingw() const { return TargetTriple.getOS() == Triple::MinGW32; }
286 bool isTargetCygwin() const { return TargetTriple.getOS() == Triple::Cygwin; }
287 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
288 bool isTargetCOFF() const {
289 return (TargetTriple.getEnvironment() != Triple::ELF &&
290 TargetTriple.isOSBinFormatCOFF());
292 bool isTargetEnvMacho() const { return TargetTriple.isEnvironmentMachO(); }
294 bool isTargetWin64() const {
295 // FIXME: x86_64-cygwin has not been released yet.
296 return In64BitMode && TargetTriple.isOSWindows();
299 bool isTargetWin32() const {
300 // FIXME: Cygwin is included for isTargetWin64 -- should it be included
302 return !In64BitMode && (isTargetMingw() || isTargetWindows());
305 bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
306 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
307 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
309 bool isPICStyleStubPIC() const {
310 return PICStyle == PICStyles::StubPIC;
313 bool isPICStyleStubNoDynamic() const {
314 return PICStyle == PICStyles::StubDynamicNoPIC;
316 bool isPICStyleStubAny() const {
317 return PICStyle == PICStyles::StubDynamicNoPIC ||
318 PICStyle == PICStyles::StubPIC; }
320 /// ClassifyGlobalReference - Classify a global variable reference for the
321 /// current subtarget according to how we should reference it in a non-pcrel
323 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
324 const TargetMachine &TM)const;
326 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
327 /// current subtarget according to how we should reference it in a non-pcrel
329 unsigned char ClassifyBlockAddressReference() const;
331 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
332 /// to immediate address.
333 bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
335 /// This function returns the name of a function which has an interface
336 /// like the non-standard bzero function, if such a function exists on
337 /// the current subtarget and it is considered prefereable over
338 /// memset with zero passed as the second argument. Otherwise it
340 const char *getBZeroEntry() const;
342 /// This function returns true if the target has sincos() routine in its
343 /// compiler runtime or math libraries.
344 bool hasSinCos() const;
346 /// enablePostRAScheduler - run for Atom optimization.
347 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
348 TargetSubtargetInfo::AntiDepBreakMode& Mode,
349 RegClassVector& CriticalPathRCs) const;
351 bool postRAScheduler() const { return PostRAScheduler; }
353 /// getInstrItins = Return the instruction itineraries based on the
354 /// subtarget selection.
355 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
358 } // End llvm namespace