1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86SUBTARGET_H
15 #define X86SUBTARGET_H
17 #include "llvm/ADT/Triple.h"
18 #include "llvm/IR/CallingConv.h"
19 #include "llvm/Target/TargetSubtargetInfo.h"
22 #define GET_SUBTARGETINFO_HEADER
23 #include "X86GenSubtargetInfo.inc"
30 /// PICStyles - The X86 backend supports a number of different styles of PIC.
34 StubPIC, // Used on i386-darwin in -fPIC mode.
35 StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
36 GOT, // Used on many 32-bit unices in -fPIC mode.
37 RIPRel, // Used on X86-64 when not in -static mode.
38 None // Set when in -static mode (not PIC or DynamicNoPIC mode).
42 class X86Subtarget : public X86GenSubtargetInfo {
45 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
49 NoThreeDNow, ThreeDNow, ThreeDNowA
52 enum X86ProcFamilyEnum {
56 /// X86ProcFamily - X86 processor family: Intel Atom, and others
57 X86ProcFamilyEnum X86ProcFamily;
59 /// PICStyle - Which PIC style to use
61 PICStyles::Style PICStyle;
63 /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
65 X86SSEEnum X86SSELevel;
67 /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
69 X863DNowEnum X863DNowLevel;
71 /// HasCMov - True if this processor has conditional move instructions
72 /// (generally pentium pro+).
75 /// HasX86_64 - True if the processor supports X86-64 instructions.
79 /// HasPOPCNT - True if the processor supports POPCNT.
82 /// HasSSE4A - True if the processor supports SSE4A instructions.
85 /// HasAES - Target has AES instructions
88 /// HasPCLMUL - Target has carry-less multiplication
91 /// HasFMA - Target has 3-operand fused multiply-add
94 /// HasFMA4 - Target has 4-operand fused multiply-add
97 /// HasXOP - Target has XOP instructions
100 /// HasMOVBE - True if the processor has the MOVBE instruction.
103 /// HasRDRAND - True if the processor has the RDRAND instruction.
106 /// HasF16C - Processor has 16-bit floating point conversion instructions.
109 /// HasFSGSBase - Processor has FS/GS base insturctions.
112 /// HasLZCNT - Processor has LZCNT instruction.
115 /// HasBMI - Processor has BMI1 instructions.
118 /// HasBMI2 - Processor has BMI2 instructions.
121 /// HasRTM - Processor has RTM instructions.
124 /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
127 /// IsUAMemFast - True if unaligned memory access is fast.
130 /// HasVectorUAMem - True if SIMD operations can have unaligned memory
131 /// operands. This may require setting a feature bit in the processor.
134 /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction;
135 /// this is true for most x86-64 chips, but not the first AMD chips.
138 /// UseLeaForSP - True if the LEA instruction should be used for adjusting
139 /// the stack pointer. This is an optimization for Intel Atom processors.
142 /// HasSlowDivide - True if smaller divides are significantly faster than
143 /// full divides and should be used when possible.
146 /// PostRAScheduler - True if using post-register-allocation scheduler.
147 bool PostRAScheduler;
149 /// PadShortFunctions - True if the short functions should be padded to prevent
150 /// a stall when returning too early.
151 bool PadShortFunctions;
153 /// stackAlignment - The minimum alignment known to hold of the stack frame on
154 /// entry to the function and which must be maintained by every function.
155 unsigned stackAlignment;
157 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
159 unsigned MaxInlineSizeThreshold;
161 /// TargetTriple - What processor and OS we're targeting.
164 /// Instruction itineraries for scheduling
165 InstrItineraryData InstrItins;
168 /// In64BitMode - True if compiling for 64-bit, false for 32-bit.
173 /// This constructor initializes the data members to match that
174 /// of the specified triple.
176 X86Subtarget(const std::string &TT, const std::string &CPU,
177 const std::string &FS,
178 unsigned StackAlignOverride, bool is64Bit);
180 /// getStackAlignment - Returns the minimum alignment known to hold of the
181 /// stack frame on entry to the function and which must be maintained by every
182 /// function for this subtarget.
183 unsigned getStackAlignment() const { return stackAlignment; }
185 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
186 /// that still makes it profitable to inline the call.
187 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
189 /// ParseSubtargetFeatures - Parses features string setting specified
190 /// subtarget options. Definition of function is auto generated by tblgen.
191 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
193 /// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID
195 void AutoDetectSubtargetFeatures();
197 bool is64Bit() const { return In64BitMode; }
199 PICStyles::Style getPICStyle() const { return PICStyle; }
200 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
202 bool hasCMov() const { return HasCMov; }
203 bool hasMMX() const { return X86SSELevel >= MMX; }
204 bool hasSSE1() const { return X86SSELevel >= SSE1; }
205 bool hasSSE2() const { return X86SSELevel >= SSE2; }
206 bool hasSSE3() const { return X86SSELevel >= SSE3; }
207 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
208 bool hasSSE41() const { return X86SSELevel >= SSE41; }
209 bool hasSSE42() const { return X86SSELevel >= SSE42; }
210 bool hasAVX() const { return X86SSELevel >= AVX; }
211 bool hasAVX2() const { return X86SSELevel >= AVX2; }
212 bool hasFp256() const { return hasAVX(); }
213 bool hasInt256() const { return hasAVX2(); }
214 bool hasSSE4A() const { return HasSSE4A; }
215 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
216 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
217 bool hasPOPCNT() const { return HasPOPCNT; }
218 bool hasAES() const { return HasAES; }
219 bool hasPCLMUL() const { return HasPCLMUL; }
220 bool hasFMA() const { return HasFMA; }
221 // FIXME: Favor FMA when both are enabled. Is this the right thing to do?
222 bool hasFMA4() const { return HasFMA4 && !HasFMA; }
223 bool hasXOP() const { return HasXOP; }
224 bool hasMOVBE() const { return HasMOVBE; }
225 bool hasRDRAND() const { return HasRDRAND; }
226 bool hasF16C() const { return HasF16C; }
227 bool hasFSGSBase() const { return HasFSGSBase; }
228 bool hasLZCNT() const { return HasLZCNT; }
229 bool hasBMI() const { return HasBMI; }
230 bool hasBMI2() const { return HasBMI2; }
231 bool hasRTM() const { return HasRTM; }
232 bool isBTMemSlow() const { return IsBTMemSlow; }
233 bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
234 bool hasVectorUAMem() const { return HasVectorUAMem; }
235 bool hasCmpxchg16b() const { return HasCmpxchg16b; }
236 bool useLeaForSP() const { return UseLeaForSP; }
237 bool hasSlowDivide() const { return HasSlowDivide; }
238 bool padShortFunctions() const { return PadShortFunctions; }
240 bool isAtom() const { return X86ProcFamily == IntelAtom; }
242 const Triple &getTargetTriple() const { return TargetTriple; }
244 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
245 bool isTargetFreeBSD() const {
246 return TargetTriple.getOS() == Triple::FreeBSD;
248 bool isTargetSolaris() const {
249 return TargetTriple.getOS() == Triple::Solaris;
251 bool isTargetELF() const {
252 return (TargetTriple.getEnvironment() == Triple::ELF ||
253 TargetTriple.isOSBinFormatELF());
255 bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; }
256 bool isTargetNaCl() const {
257 return TargetTriple.getOS() == Triple::NaCl;
259 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
260 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
261 bool isTargetWindows() const { return TargetTriple.getOS() == Triple::Win32; }
262 bool isTargetMingw() const { return TargetTriple.getOS() == Triple::MinGW32; }
263 bool isTargetCygwin() const { return TargetTriple.getOS() == Triple::Cygwin; }
264 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
265 bool isTargetCOFF() const {
266 return (TargetTriple.getEnvironment() != Triple::ELF &&
267 TargetTriple.isOSBinFormatCOFF());
269 bool isTargetEnvMacho() const { return TargetTriple.isEnvironmentMachO(); }
271 bool isTargetWin64() const {
272 // FIXME: x86_64-cygwin has not been released yet.
273 return In64BitMode && TargetTriple.isOSWindows();
276 bool isTargetWin32() const {
277 // FIXME: Cygwin is included for isTargetWin64 -- should it be included
279 return !In64BitMode && (isTargetMingw() || isTargetWindows());
282 bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
283 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
284 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
286 bool isPICStyleStubPIC() const {
287 return PICStyle == PICStyles::StubPIC;
290 bool isPICStyleStubNoDynamic() const {
291 return PICStyle == PICStyles::StubDynamicNoPIC;
293 bool isPICStyleStubAny() const {
294 return PICStyle == PICStyles::StubDynamicNoPIC ||
295 PICStyle == PICStyles::StubPIC; }
297 /// ClassifyGlobalReference - Classify a global variable reference for the
298 /// current subtarget according to how we should reference it in a non-pcrel
300 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
301 const TargetMachine &TM)const;
303 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
304 /// current subtarget according to how we should reference it in a non-pcrel
306 unsigned char ClassifyBlockAddressReference() const;
308 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
309 /// to immediate address.
310 bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
312 /// This function returns the name of a function which has an interface
313 /// like the non-standard bzero function, if such a function exists on
314 /// the current subtarget and it is considered prefereable over
315 /// memset with zero passed as the second argument. Otherwise it
317 const char *getBZeroEntry() const;
319 /// enablePostRAScheduler - run for Atom optimization.
320 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
321 TargetSubtargetInfo::AntiDepBreakMode& Mode,
322 RegClassVector& CriticalPathRCs) const;
324 bool postRAScheduler() const { return PostRAScheduler; }
326 /// getInstrItins = Return the instruction itineraries based on the
327 /// subtarget selection.
328 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
331 } // End llvm namespace