lib/Target/X86/X86TargetMachine.cpp

   1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the X86 specific subclass of TargetMachine.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "X86TargetMachine.h"
  15 #include "X86.h"
  16 #include "llvm/PassManager.h"
  17 #include "llvm/CodeGen/MachineFunction.h"
  18 #include "llvm/CodeGen/Passes.h"
  19 #include "llvm/Support/CommandLine.h"
  20 #include "llvm/Support/FormattedStream.h"
  21 #include "llvm/Target/TargetOptions.h"
  22 #include "llvm/Support/TargetRegistry.h"
  23 using namespace llvm;
  24
  25 extern "C" void LLVMInitializeX86Target() {
  26   // Register the target.
  27   RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target);
  28   RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target);
  29 }
  30
  31
  32 X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
  33                                          StringRef CPU, StringRef FS,
  34                                          const TargetOptions &Options,
  35                                          Reloc::Model RM, CodeModel::Model CM,
  36                                          CodeGenOpt::Level OL)
  37   : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false),
  38     DataLayout(getSubtargetImpl()->isTargetDarwin() ?
  39                "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-"
  40                "n8:16:32-S128" :
  41                (getSubtargetImpl()->isTargetCygMing() ||
  42                 getSubtargetImpl()->isTargetWindows()) ?
  43                "e-p:32:32-f64:64:64-i64:64:64-f80:32:32-f128:128:128-"
  44                "n8:16:32-S32" :
  45                "e-p:32:32-f64:32:64-i64:32:64-f80:32:32-f128:128:128-"
  46                "n8:16:32-S128"),
  47     InstrInfo(*this),
  48     TSInfo(*this),
  49     TLInfo(*this),
  50     JITInfo(*this) {
  51 }
  52
  53
  54 X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
  55                                          StringRef CPU, StringRef FS,
  56                                          const TargetOptions &Options,
  57                                          Reloc::Model RM, CodeModel::Model CM,
  58                                          CodeGenOpt::Level OL)
  59   : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true),
  60     DataLayout("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-"
  61                "n8:16:32:64-S128"),
  62     InstrInfo(*this),
  63     TSInfo(*this),
  64     TLInfo(*this),
  65     JITInfo(*this) {
  66 }
  67
  68 /// X86TargetMachine ctor - Create an X86 target.
  69 ///
  70 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
  71                                    StringRef CPU, StringRef FS,
  72                                    const TargetOptions &Options,
  73                                    Reloc::Model RM, CodeModel::Model CM,
  74                                    CodeGenOpt::Level OL,
  75                                    bool is64Bit)
  76   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
  77     Subtarget(TT, CPU, FS, Options.StackAlignmentOverride, is64Bit),
  78     FrameLowering(*this, Subtarget),
  79     ELFWriterInfo(is64Bit, true) {
  80   // Determine the PICStyle based on the target selected.
  81   if (getRelocationModel() == Reloc::Static) {
  82     // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
  83     Subtarget.setPICStyle(PICStyles::None);
  84   } else if (Subtarget.is64Bit()) {
  85     // PIC in 64 bit mode is always rip-rel.
  86     Subtarget.setPICStyle(PICStyles::RIPRel);
  87   } else if (Subtarget.isTargetCygMing()) {
  88     Subtarget.setPICStyle(PICStyles::None);
  89   } else if (Subtarget.isTargetDarwin()) {
  90     if (getRelocationModel() == Reloc::PIC_)
  91       Subtarget.setPICStyle(PICStyles::StubPIC);
  92     else {
  93       assert(getRelocationModel() == Reloc::DynamicNoPIC);
  94       Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
  95     }
  96   } else if (Subtarget.isTargetELF()) {
  97     Subtarget.setPICStyle(PICStyles::GOT);
  98   }
  99
 100   // default to hard float ABI
 101   if (Options.FloatABIType == FloatABI::Default)
 102     this->Options.FloatABIType = FloatABI::Hard;
 103
 104   if (Options.EnableSegmentedStacks && !Subtarget.isTargetELF())
 105     report_fatal_error("Segmented stacks are only implemented on ELF.");
 106 }
 107
 108 //===----------------------------------------------------------------------===//
 109 // Command line options for x86
 110 //===----------------------------------------------------------------------===//
 111 static cl::opt<bool>
 112 UseVZeroUpper("x86-use-vzeroupper",
 113   cl::desc("Minimize AVX to SSE transition penalty"),
 114   cl::init(true));
 115
 116 //===----------------------------------------------------------------------===//
 117 // Pass Pipeline Configuration
 118 //===----------------------------------------------------------------------===//
 119
 120 bool X86TargetMachine::addInstSelector(PassManagerBase &PM) {
 121   // Install an instruction selector.
 122   PM.add(createX86ISelDag(*this, getOptLevel()));
 123
 124   // For 32-bit, prepend instructions to set the "global base reg" for PIC.
 125   if (!Subtarget.is64Bit())
 126     PM.add(createGlobalBaseRegPass());
 127
 128   return false;
 129 }
 130
 131 bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM) {
 132   PM.add(createX86MaxStackAlignmentHeuristicPass());
 133   return false;  // -print-machineinstr shouldn't print after this.
 134 }
 135
 136 bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM) {
 137   PM.add(createX86FloatingPointStackifierPass());
 138   return true;  // -print-machineinstr should print after this.
 139 }
 140
 141 bool X86TargetMachine::addPreEmitPass(PassManagerBase &PM) {
 142   bool ShouldPrint = false;
 143   if (getOptLevel() != CodeGenOpt::None && Subtarget.hasXMMInt()) {
 144     PM.add(createExecutionDependencyFixPass(&X86::VR128RegClass));
 145     ShouldPrint = true;
 146   }
 147
 148   if (Subtarget.hasAVX() && UseVZeroUpper) {
 149     PM.add(createX86IssueVZeroUpperPass());
 150     ShouldPrint = true;
 151   }
 152
 153   return ShouldPrint;
 154 }
 155
 156 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
 157                                       JITCodeEmitter &JCE) {
 158   PM.add(createX86JITCodeEmitterPass(*this, JCE));
 159
 160   return false;
 161 }